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library/jesd-align- remove signaltap interface

main
Rejeesh Kutty 2015-06-19 14:31:36 -04:00
parent af2ffbe0a0
commit 3e5a5504a7
2 changed files with 1 additions and 34 deletions
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16
library/util_jesd_align/util_jesd_align.v
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@ -45,10 +45,7 @@ module util_jesd_align (
rx_ip_sof,
rx_ip_data,
rx_sof,
rx_data,
rx_st_valid,
rx_st_data);
rx_data);
// parameters
@ -64,19 +61,8 @@ module util_jesd_align (
output [((NUM_OF_LANES* 1)-1):0] rx_sof;
output [((NUM_OF_LANES*32)-1):0] rx_data;
output [(ST_VALID_WIDTH-1):0] rx_st_valid;
output [(ST_DATA_WIDTH-1):0] rx_st_data;
// internal signals
wire [((NUM_OF_LANES*64)+3):0] rx_st_data_s;
// only for altera, xcvr+jesd do not frame align
assign rx_st_data_s = {rx_ip_sof, rx_ip_data, rx_data};
assign rx_st_data = rx_st_data_s[(ST_DATA_WIDTH-1):0];
assign rx_st_valid = 'd1;
genvar n;
generate
for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lane

19
library/util_jesd_align/util_jesd_align_hw.tcl
View File

@ -27,20 +27,6 @@ set_parameter_property NUM_OF_LANES TYPE INTEGER
set_parameter_property NUM_OF_LANES UNITS None
set_parameter_property NUM_OF_LANES HDL_PARAMETER true
add_parameter ST_VALID_WIDTH INTEGER 0
set_parameter_property ST_VALID_WIDTH DEFAULT_VALUE 1
set_parameter_property ST_VALID_WIDTH DISPLAY_NAME ST_VALID_WIDTH
set_parameter_property ST_VALID_WIDTH TYPE INTEGER
set_parameter_property ST_VALID_WIDTH UNITS None
set_parameter_property ST_VALID_WIDTH HDL_PARAMETER true
add_parameter ST_DATA_WIDTH INTEGER 0
set_parameter_property ST_DATA_WIDTH DEFAULT_VALUE 32
set_parameter_property ST_DATA_WIDTH DISPLAY_NAME ST_DATA_WIDTH
set_parameter_property ST_DATA_WIDTH TYPE INTEGER
set_parameter_property ST_DATA_WIDTH UNITS None
set_parameter_property ST_DATA_WIDTH HDL_PARAMETER true
# transceiver interface
add_interface if_rx_clk clock end
@ -55,11 +41,6 @@ add_interface_port if_rx_data rx_data data Output 32*NUM_OF_LANES
ad_alt_intf signal rx_ip_sof input 4 export
ad_alt_intf signal rx_sof output NUM_OF_LANES export
add_interface if_rx_st conduit end
set_interface_property if_rx_st associatedClock if_rx_clk
add_interface_port if_rx_st rx_st_valid acq_trigger_in output ST_VALID_WIDTH
add_interface_port if_rx_st rx_st_data acq_data_in output ST_DATA_WIDTH
proc p_util_jesd_align {} {
set p_num_of_lanes [get_parameter_value "NUM_OF_LANES"]