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enable/txnrx- tdd changes

main
Rejeesh Kutty 2015-05-18 14:27:58 -04:00
parent 0877c252ad
commit 3e51d29f75
5 changed files with 29 additions and 34 deletions
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12
projects/fmcomms2/common/fmcomms2_bd.tcl
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@ -15,8 +15,8 @@ create_bd_port -dir O tx_frame_out_n
create_bd_port -dir O -from 5 -to 0 tx_data_out_p
create_bd_port -dir O -from 5 -to 0 tx_data_out_n
create_bd_port -dir O axi_ad9361_enable
create_bd_port -dir O axi_ad9361_txnrx
create_bd_port -dir O enable
create_bd_port -dir O txnrx
# ad9361 core
@ -74,8 +74,8 @@ ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p
ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n
ad_connect tx_data_out_p axi_ad9361/tx_data_out_p
ad_connect tx_data_out_n axi_ad9361/tx_data_out_n
ad_connect axi_ad9361/tdd_enable axi_ad9361_enable
ad_connect axi_ad9361/tdd_txnrx axi_ad9361_txnrx
ad_connect axi_ad9361/enable enable
ad_connect axi_ad9361/txnrx txnrx
ad_connect axi_ad9361_clk util_adc_pack/clk
ad_connect axi_ad9361/adc_valid_i0 util_adc_pack/chan_valid_0
ad_connect axi_ad9361/adc_valid_q0 util_adc_pack/chan_valid_1
@ -143,8 +143,8 @@ set_property -dict [list CONFIG.C_PROBE5_WIDTH {1}] $ila_tdd
set_property -dict [list CONFIG.C_PROBE6_WIDTH {64}] $ila_tdd
ad_connect axi_ad9361_clk ila_tdd/clk
ad_connect axi_ad9361/tdd_enable ila_tdd/probe0
ad_connect axi_ad9361/tdd_txnrx ila_tdd/probe1
ad_connect axi_ad9361/enable ila_tdd/probe0
ad_connect axi_ad9361/txnrx ila_tdd/probe1
ad_connect axi_ad9361/tdd_dbg ila_tdd/probe2
ad_connect util_dac_unpack/fifo_valid ila_tdd/probe3
ad_connect util_dac_unpack/dma_rd ila_tdd/probe4

4
projects/fmcomms2/rfsom/system_constr.xdc
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@ -34,6 +34,8 @@ set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVDS} [get_ports tx_data_o
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVDS} [get_ports tx_data_out_n[4]] ; ## IO_L17N_T2_AD5N_35
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS} [get_ports tx_data_out_p[5]] ; ## IO_L18P_T2_AD13P_35
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS} [get_ports tx_data_out_n[5]] ; ## IO_L18N_T2_AD13N_35
set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports enable] ; ## IO_L11P_T1_SRCC_35
set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports txnrx] ; ## IO_L11N_T1_SRCC_35
set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] ; ## IO_L19P_T3_35
set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] ; ## IO_L19N_T3_VREF_35
@ -49,8 +51,6 @@ set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[
set_property -dict {PACKAGE_PIN A2 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]] ; ## IO_L24N_T3_34
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] ; ## IO_L10P_T1_AD11P_35
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports gpio_sync] ; ## IO_L10N_T1_AD11N_35
set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports gpio_enable] ; ## IO_L11P_T1_SRCC_35
set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports gpio_txnrx] ; ## IO_L11N_T1_SRCC_35
set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] ; ## IO_0_VRN_35
set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports gpio_clksel] ; ## IO_0_VRN_34
set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS18} [get_ports gpio_rfpwr_enable] ; ## IO_25_VRP_34

22
projects/fmcomms2/rfsom/system_top.v
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@ -107,11 +107,11 @@ module system_top (
tx_frame_out_n,
tx_data_out_p,
tx_data_out_n,
enable,
txnrx,
gpio_rfpwr_enable,
gpio_clksel,
gpio_txnrx,
gpio_enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
@ -190,11 +190,11 @@ module system_top (
output tx_frame_out_n;
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
output enable;
output txnrx;
inout gpio_rfpwr_enable;
inout gpio_clksel;
inout gpio_txnrx;
inout gpio_enable;
inout gpio_resetb;
inout gpio_sync;
inout gpio_en_agc;
@ -219,14 +219,12 @@ module system_top (
// instantiations
ad_iobuf #(.DATA_WIDTH(19)) i_iobuf (
.dt (gpio_t[50:32]),
.di (gpio_o[50:32]),
.do (gpio_i[50:32]),
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
.dt ({gpio_t[50:49], gpio_t[46:32]}),
.di ({gpio_o[50:49], gpio_o[46:32]}),
.do ({gpio_i[50:49], gpio_i[46:32]}),
.dio({ gpio_rfpwr_enable,
gpio_clksel,
gpio_txnrx,
gpio_enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
@ -255,6 +253,7 @@ module system_top (
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.enable (enable),
.eth1_125mclk (),
.eth1_25mclk (),
.eth1_2m5clk (),
@ -336,7 +335,8 @@ module system_top (
.tx_data_out_n (tx_data_out_n),
.tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p));
.tx_frame_out_p (tx_frame_out_p),
.txnrx (txnrx));
endmodule

8
projects/fmcomms2/zc706/system_constr.xdc
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@ -34,6 +34,8 @@ set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25} [get_ports tx_data_o
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N
set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P
set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N
@ -50,10 +52,6 @@ set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVCMOS25} [get_ports gpio_ctl
set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports ad9361_enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports ad9361_txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {IOB TRUE} [get_ports {ad9361_enable ad9361_txnrx}]
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N
@ -67,6 +65,8 @@ set_property -dict {PACKAGE_PIN AK21 IOSTANDARD LVCMOS25} [get_ports sp
set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS25} [get_ports spi_udc_sclk] ; ## PMOD1_3_LS
set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS25} [get_ports spi_udc_data] ; ## PMOD1_2_LS
set_property -dict {IOB TRUE} [get_ports {enable txnrx}]
# clocks
create_clock -name rx_clk -period 4.00 [get_ports rx_clk_in_p]

17
projects/fmcomms2/zc706/system_top.v
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@ -89,6 +89,8 @@ module system_top (
tx_frame_out_n,
tx_data_out_p,
tx_data_out_n,
enable,
txnrx,
gpio_resetb,
gpio_sync,
@ -96,9 +98,6 @@ module system_top (
gpio_ctl,
gpio_status,
ad9361_enable,
ad9361_txnrx,
spi_csn,
spi_clk,
spi_mosi,
@ -157,6 +156,8 @@ module system_top (
output tx_frame_out_n;
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
output enable;
output txnrx;
inout gpio_resetb;
inout gpio_sync;
@ -174,9 +175,6 @@ module system_top (
output spi_udc_sclk;
output spi_udc_data;
output ad9361_enable;
output ad9361_txnrx;
// internal signals
wire [63:0] gpio_i;
@ -204,9 +202,6 @@ module system_top (
wire [31:0] dac_gpio_input;
wire [31:0] dac_gpio_output;
wire ad9361_enable_s;
wire ad9361_txnrx_s;
// instantiations
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf (
@ -241,6 +236,7 @@ module system_top (
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.enable (enable),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
@ -300,8 +296,7 @@ module system_top (
.tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p),
.axi_ad9361_enable(ad9361_enable),
.axi_ad9361_txnrx(ad9361_txnrx));
.txnrx (txnrx));
endmodule