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avl_dacfifo: Fix avl_address generation 

+ Define address limit at 2GByte
  + Address is WORD aligned, increment accordingly
main
Istvan Csomortani 2017-12-15 12:17:47 +00:00
parent 60d2fb939d
commit 3e3955ce91
2 changed files with 5 additions and 9 deletions
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8
library/altera/avl_dacfifo/avl_dacfifo_rd.v
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@ -41,7 +41,7 @@ module avl_dacfifo_rd #(
parameter DAC_DATA_WIDTH = 64,
parameter AVL_BURST_LENGTH = 127,
parameter AVL_DDR_BASE_ADDRESS = 0,
parameter AVL_DDR_ADDRESS_LIMIT = 1048576,
parameter AVL_DDR_ADDRESS_LIMIT = 33554432,
parameter DAC_MEM_ADDRESS_WIDTH = 8)(
input dac_clk,
@ -84,8 +84,6 @@ module avl_dacfifo_rd #(
(MEM_RATIO > 4) ? 3 :
(MEM_RATIO > 2) ? 2 :
(MEM_RATIO > 1) ? 1 : 1;
localparam AVL_BYTE_DATA_WIDTH = AVL_DATA_WIDTH/8;
localparam AVL_ARINCR = AVL_BURST_LENGTH * AVL_BYTE_DATA_WIDTH;
// FSM state definition
@ -207,7 +205,7 @@ module avl_dacfifo_rd #(
XFER_STAGING : begin
if (avl_xfer_req_in == 1'b1) begin
if (avl_mem_request_data == 1'b1) begin
if (avl_address + AVL_ARINCR <= avl_last_address) begin
if (avl_address + AVL_BURST_LENGTH <= avl_last_address) begin
avl_read_state <= XFER_FULL_BURST;
avl_burstcount <= AVL_BURST_LENGTH;
end else begin
@ -259,7 +257,7 @@ module avl_dacfifo_rd #(
avl_address <= AVL_DDR_BASE_ADDRESS;
end else begin
if (avl_end_of_burst_s == 1'b1) begin
avl_address <= (avl_address < avl_last_address) ? avl_address + (avl_burstcount * AVL_BYTE_DATA_WIDTH) : AVL_DDR_BASE_ADDRESS;
avl_address <= (avl_address < avl_last_address) ? avl_address + avl_burstcount : AVL_DDR_BASE_ADDRESS;
end
end
end

6
library/altera/avl_dacfifo/avl_dacfifo_wr.v
View File

@ -41,7 +41,7 @@ module avl_dacfifo_wr #(
parameter DMA_DATA_WIDTH = 64,
parameter AVL_BURST_LENGTH = 128,
parameter AVL_DDR_BASE_ADDRESS = 0,
parameter AVL_DDR_ADDRESS_LIMIT = 1048576,
parameter AVL_DDR_ADDRESS_LIMIT = 33554432,
parameter DMA_MEM_ADDRESS_WIDTH = 10)(
input dma_clk,
@ -82,8 +82,6 @@ module avl_dacfifo_wr #(
(MEM_RATIO > 1) ? 1 : 1;
localparam DMA_BUF_THRESHOLD_HI = {(DMA_MEM_ADDRESS_WIDTH){1'b1}} - AVL_BURST_LENGTH;
localparam DMA_BYTE_DATA_WIDTH = DMA_DATA_WIDTH/8;
localparam AVL_BYTE_DATA_WIDTH = AVL_DATA_WIDTH/8;
// FSM state definition
@ -427,7 +425,7 @@ module avl_dacfifo_wr #(
avl_address <= AVL_DDR_BASE_ADDRESS;
end else begin
if (avl_endof_burst == 1'b1) begin
avl_address <= (avl_address < AVL_DDR_ADDRESS_LIMIT) ? avl_address + (AVL_BURST_LENGTH * AVL_BYTE_DATA_WIDTH) : AVL_DDR_BASE_ADDRESS;
avl_address <= (avl_address < AVL_DDR_ADDRESS_LIMIT) ? avl_address + AVL_BURST_LENGTH : AVL_DDR_BASE_ADDRESS;
end
end
end