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util_adxcvr: expose cpll/qpll as it is

main
Rejeesh Kutty 2016-11-22 11:32:37 -05:00
parent 3cbe735bd8
commit 3dbed492b3
3 changed files with 37 additions and 99 deletions
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128
library/xilinx/util_adxcvr/util_adxcvr.v
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@ -55,7 +55,6 @@ module util_adxcvr #(
parameter integer CPLL_FBDIV = 2, parameter integer CPLL_FBDIV = 2,
parameter integer CPLL_FBDIV_4_5 = 5, parameter integer CPLL_FBDIV_4_5 = 5,
parameter integer CPLL_TX_OR_RX_N = 0,
// tx-configuration // tx-configuration
@ -76,7 +75,9 @@ module util_adxcvr #(
input up_clk, input up_clk,
input qpll_ref_clk_0, input qpll_ref_clk_0,
input up_qpll_rst_0,
input cpll_ref_clk_0, input cpll_ref_clk_0,
input up_cpll_rst_0,
input rx_0_p, input rx_0_p,
input rx_0_n, input rx_0_n,
@ -109,7 +110,6 @@ module util_adxcvr #(
input [15:0] up_es_wdata_0, input [15:0] up_es_wdata_0,
output [15:0] up_es_rdata_0, output [15:0] up_es_rdata_0,
output up_es_ready_0, output up_es_ready_0,
input up_rx_pll_rst_0,
output up_rx_pll_locked_0, output up_rx_pll_locked_0,
input up_rx_rst_0, input up_rx_rst_0,
input up_rx_user_ready_0, input up_rx_user_ready_0,
@ -125,7 +125,6 @@ module util_adxcvr #(
input [15:0] up_rx_wdata_0, input [15:0] up_rx_wdata_0,
output [15:0] up_rx_rdata_0, output [15:0] up_rx_rdata_0,
output up_rx_ready_0, output up_rx_ready_0,
input up_tx_pll_rst_0,
output up_tx_pll_locked_0, output up_tx_pll_locked_0,
input up_tx_rst_0, input up_tx_rst_0,
input up_tx_user_ready_0, input up_tx_user_ready_0,
@ -143,6 +142,7 @@ module util_adxcvr #(
output up_tx_ready_0, output up_tx_ready_0,
input cpll_ref_clk_1, input cpll_ref_clk_1,
input up_cpll_rst_1,
input rx_1_p, input rx_1_p,
input rx_1_n, input rx_1_n,
@ -168,7 +168,6 @@ module util_adxcvr #(
input [15:0] up_es_wdata_1, input [15:0] up_es_wdata_1,
output [15:0] up_es_rdata_1, output [15:0] up_es_rdata_1,
output up_es_ready_1, output up_es_ready_1,
input up_rx_pll_rst_1,
output up_rx_pll_locked_1, output up_rx_pll_locked_1,
input up_rx_rst_1, input up_rx_rst_1,
input up_rx_user_ready_1, input up_rx_user_ready_1,
@ -184,7 +183,6 @@ module util_adxcvr #(
input [15:0] up_rx_wdata_1, input [15:0] up_rx_wdata_1,
output [15:0] up_rx_rdata_1, output [15:0] up_rx_rdata_1,
output up_rx_ready_1, output up_rx_ready_1,
input up_tx_pll_rst_1,
output up_tx_pll_locked_1, output up_tx_pll_locked_1,
input up_tx_rst_1, input up_tx_rst_1,
input up_tx_user_ready_1, input up_tx_user_ready_1,
@ -202,6 +200,7 @@ module util_adxcvr #(
output up_tx_ready_1, output up_tx_ready_1,
input cpll_ref_clk_2, input cpll_ref_clk_2,
input up_cpll_rst_2,
input rx_2_p, input rx_2_p,
input rx_2_n, input rx_2_n,
@ -227,7 +226,6 @@ module util_adxcvr #(
input [15:0] up_es_wdata_2, input [15:0] up_es_wdata_2,
output [15:0] up_es_rdata_2, output [15:0] up_es_rdata_2,
output up_es_ready_2, output up_es_ready_2,
input up_rx_pll_rst_2,
output up_rx_pll_locked_2, output up_rx_pll_locked_2,
input up_rx_rst_2, input up_rx_rst_2,
input up_rx_user_ready_2, input up_rx_user_ready_2,
@ -243,7 +241,6 @@ module util_adxcvr #(
input [15:0] up_rx_wdata_2, input [15:0] up_rx_wdata_2,
output [15:0] up_rx_rdata_2, output [15:0] up_rx_rdata_2,
output up_rx_ready_2, output up_rx_ready_2,
input up_tx_pll_rst_2,
output up_tx_pll_locked_2, output up_tx_pll_locked_2,
input up_tx_rst_2, input up_tx_rst_2,
input up_tx_user_ready_2, input up_tx_user_ready_2,
@ -261,6 +258,7 @@ module util_adxcvr #(
output up_tx_ready_2, output up_tx_ready_2,
input cpll_ref_clk_3, input cpll_ref_clk_3,
input up_cpll_rst_3,
input rx_3_p, input rx_3_p,
input rx_3_n, input rx_3_n,
@ -286,7 +284,6 @@ module util_adxcvr #(
input [15:0] up_es_wdata_3, input [15:0] up_es_wdata_3,
output [15:0] up_es_rdata_3, output [15:0] up_es_rdata_3,
output up_es_ready_3, output up_es_ready_3,
input up_rx_pll_rst_3,
output up_rx_pll_locked_3, output up_rx_pll_locked_3,
input up_rx_rst_3, input up_rx_rst_3,
input up_rx_user_ready_3, input up_rx_user_ready_3,
@ -302,7 +299,6 @@ module util_adxcvr #(
input [15:0] up_rx_wdata_3, input [15:0] up_rx_wdata_3,
output [15:0] up_rx_rdata_3, output [15:0] up_rx_rdata_3,
output up_rx_ready_3, output up_rx_ready_3,
input up_tx_pll_rst_3,
output up_tx_pll_locked_3, output up_tx_pll_locked_3,
input up_tx_rst_3, input up_tx_rst_3,
input up_tx_user_ready_3, input up_tx_user_ready_3,
@ -320,7 +316,9 @@ module util_adxcvr #(
output up_tx_ready_3, output up_tx_ready_3,
input qpll_ref_clk_4, input qpll_ref_clk_4,
input up_qpll_rst_4,
input cpll_ref_clk_4, input cpll_ref_clk_4,
input up_cpll_rst_4,
input rx_4_p, input rx_4_p,
input rx_4_n, input rx_4_n,
@ -353,7 +351,6 @@ module util_adxcvr #(
input [15:0] up_es_wdata_4, input [15:0] up_es_wdata_4,
output [15:0] up_es_rdata_4, output [15:0] up_es_rdata_4,
output up_es_ready_4, output up_es_ready_4,
input up_rx_pll_rst_4,
output up_rx_pll_locked_4, output up_rx_pll_locked_4,
input up_rx_rst_4, input up_rx_rst_4,
input up_rx_user_ready_4, input up_rx_user_ready_4,
@ -369,7 +366,6 @@ module util_adxcvr #(
input [15:0] up_rx_wdata_4, input [15:0] up_rx_wdata_4,
output [15:0] up_rx_rdata_4, output [15:0] up_rx_rdata_4,
output up_rx_ready_4, output up_rx_ready_4,
input up_tx_pll_rst_4,
output up_tx_pll_locked_4, output up_tx_pll_locked_4,
input up_tx_rst_4, input up_tx_rst_4,
input up_tx_user_ready_4, input up_tx_user_ready_4,
@ -387,6 +383,7 @@ module util_adxcvr #(
output up_tx_ready_4, output up_tx_ready_4,
input cpll_ref_clk_5, input cpll_ref_clk_5,
input up_cpll_rst_5,
input rx_5_p, input rx_5_p,
input rx_5_n, input rx_5_n,
@ -412,7 +409,6 @@ module util_adxcvr #(
input [15:0] up_es_wdata_5, input [15:0] up_es_wdata_5,
output [15:0] up_es_rdata_5, output [15:0] up_es_rdata_5,
output up_es_ready_5, output up_es_ready_5,
input up_rx_pll_rst_5,
output up_rx_pll_locked_5, output up_rx_pll_locked_5,
input up_rx_rst_5, input up_rx_rst_5,
input up_rx_user_ready_5, input up_rx_user_ready_5,
@ -428,7 +424,6 @@ module util_adxcvr #(
input [15:0] up_rx_wdata_5, input [15:0] up_rx_wdata_5,
output [15:0] up_rx_rdata_5, output [15:0] up_rx_rdata_5,
output up_rx_ready_5, output up_rx_ready_5,
input up_tx_pll_rst_5,
output up_tx_pll_locked_5, output up_tx_pll_locked_5,
input up_tx_rst_5, input up_tx_rst_5,
input up_tx_user_ready_5, input up_tx_user_ready_5,
@ -446,6 +441,7 @@ module util_adxcvr #(
output up_tx_ready_5, output up_tx_ready_5,
input cpll_ref_clk_6, input cpll_ref_clk_6,
input up_cpll_rst_6,
input rx_6_p, input rx_6_p,
input rx_6_n, input rx_6_n,
@ -471,7 +467,6 @@ module util_adxcvr #(
input [15:0] up_es_wdata_6, input [15:0] up_es_wdata_6,
output [15:0] up_es_rdata_6, output [15:0] up_es_rdata_6,
output up_es_ready_6, output up_es_ready_6,
input up_rx_pll_rst_6,
output up_rx_pll_locked_6, output up_rx_pll_locked_6,
input up_rx_rst_6, input up_rx_rst_6,
input up_rx_user_ready_6, input up_rx_user_ready_6,
@ -487,7 +482,6 @@ module util_adxcvr #(
input [15:0] up_rx_wdata_6, input [15:0] up_rx_wdata_6,
output [15:0] up_rx_rdata_6, output [15:0] up_rx_rdata_6,
output up_rx_ready_6, output up_rx_ready_6,
input up_tx_pll_rst_6,
output up_tx_pll_locked_6, output up_tx_pll_locked_6,
input up_tx_rst_6, input up_tx_rst_6,
input up_tx_user_ready_6, input up_tx_user_ready_6,
@ -505,6 +499,7 @@ module util_adxcvr #(
output up_tx_ready_6, output up_tx_ready_6,
input cpll_ref_clk_7, input cpll_ref_clk_7,
input up_cpll_rst_7,
input rx_7_p, input rx_7_p,
input rx_7_n, input rx_7_n,
@ -530,7 +525,6 @@ module util_adxcvr #(
input [15:0] up_es_wdata_7, input [15:0] up_es_wdata_7,
output [15:0] up_es_rdata_7, output [15:0] up_es_rdata_7,
output up_es_ready_7, output up_es_ready_7,
input up_rx_pll_rst_7,
output up_rx_pll_locked_7, output up_rx_pll_locked_7,
input up_rx_rst_7, input up_rx_rst_7,
input up_rx_user_ready_7, input up_rx_user_ready_7,
@ -546,7 +540,6 @@ module util_adxcvr #(
input [15:0] up_rx_wdata_7, input [15:0] up_rx_wdata_7,
output [15:0] up_rx_rdata_7, output [15:0] up_rx_rdata_7,
output up_rx_ready_7, output up_rx_ready_7,
input up_tx_pll_rst_7,
output up_tx_pll_locked_7, output up_tx_pll_locked_7,
input up_tx_rst_7, input up_tx_rst_7,
input up_tx_user_ready_7, input up_tx_user_ready_7,
@ -564,7 +557,9 @@ module util_adxcvr #(
output up_tx_ready_7, output up_tx_ready_7,
input qpll_ref_clk_8, input qpll_ref_clk_8,
input up_qpll_rst_8,
input cpll_ref_clk_8, input cpll_ref_clk_8,
input up_cpll_rst_8,
input rx_8_p, input rx_8_p,
input rx_8_n, input rx_8_n,
@ -597,7 +592,6 @@ module util_adxcvr #(
input [15:0] up_es_wdata_8, input [15:0] up_es_wdata_8,
output [15:0] up_es_rdata_8, output [15:0] up_es_rdata_8,
output up_es_ready_8, output up_es_ready_8,
input up_rx_pll_rst_8,
output up_rx_pll_locked_8, output up_rx_pll_locked_8,
input up_rx_rst_8, input up_rx_rst_8,
input up_rx_user_ready_8, input up_rx_user_ready_8,
@ -613,7 +607,6 @@ module util_adxcvr #(
input [15:0] up_rx_wdata_8, input [15:0] up_rx_wdata_8,
output [15:0] up_rx_rdata_8, output [15:0] up_rx_rdata_8,
output up_rx_ready_8, output up_rx_ready_8,
input up_tx_pll_rst_8,
output up_tx_pll_locked_8, output up_tx_pll_locked_8,
input up_tx_rst_8, input up_tx_rst_8,
input up_tx_user_ready_8, input up_tx_user_ready_8,
@ -631,6 +624,7 @@ module util_adxcvr #(
output up_tx_ready_8, output up_tx_ready_8,
input cpll_ref_clk_9, input cpll_ref_clk_9,
input up_cpll_rst_9,
input rx_9_p, input rx_9_p,
input rx_9_n, input rx_9_n,
@ -656,7 +650,6 @@ module util_adxcvr #(
input [15:0] up_es_wdata_9, input [15:0] up_es_wdata_9,
output [15:0] up_es_rdata_9, output [15:0] up_es_rdata_9,
output up_es_ready_9, output up_es_ready_9,
input up_rx_pll_rst_9,
output up_rx_pll_locked_9, output up_rx_pll_locked_9,
input up_rx_rst_9, input up_rx_rst_9,
input up_rx_user_ready_9, input up_rx_user_ready_9,
@ -672,7 +665,6 @@ module util_adxcvr #(
input [15:0] up_rx_wdata_9, input [15:0] up_rx_wdata_9,
output [15:0] up_rx_rdata_9, output [15:0] up_rx_rdata_9,
output up_rx_ready_9, output up_rx_ready_9,
input up_tx_pll_rst_9,
output up_tx_pll_locked_9, output up_tx_pll_locked_9,
input up_tx_rst_9, input up_tx_rst_9,
input up_tx_user_ready_9, input up_tx_user_ready_9,
@ -690,6 +682,7 @@ module util_adxcvr #(
output up_tx_ready_9, output up_tx_ready_9,
input cpll_ref_clk_10, input cpll_ref_clk_10,
input up_cpll_rst_10,
input rx_10_p, input rx_10_p,
input rx_10_n, input rx_10_n,
@ -715,7 +708,6 @@ module util_adxcvr #(
input [15:0] up_es_wdata_10, input [15:0] up_es_wdata_10,
output [15:0] up_es_rdata_10, output [15:0] up_es_rdata_10,
output up_es_ready_10, output up_es_ready_10,
input up_rx_pll_rst_10,
output up_rx_pll_locked_10, output up_rx_pll_locked_10,
input up_rx_rst_10, input up_rx_rst_10,
input up_rx_user_ready_10, input up_rx_user_ready_10,
@ -731,7 +723,6 @@ module util_adxcvr #(
input [15:0] up_rx_wdata_10, input [15:0] up_rx_wdata_10,
output [15:0] up_rx_rdata_10, output [15:0] up_rx_rdata_10,
output up_rx_ready_10, output up_rx_ready_10,
input up_tx_pll_rst_10,
output up_tx_pll_locked_10, output up_tx_pll_locked_10,
input up_tx_rst_10, input up_tx_rst_10,
input up_tx_user_ready_10, input up_tx_user_ready_10,
@ -749,6 +740,7 @@ module util_adxcvr #(
output up_tx_ready_10, output up_tx_ready_10,
input cpll_ref_clk_11, input cpll_ref_clk_11,
input up_cpll_rst_11,
input rx_11_p, input rx_11_p,
input rx_11_n, input rx_11_n,
@ -774,7 +766,6 @@ module util_adxcvr #(
input [15:0] up_es_wdata_11, input [15:0] up_es_wdata_11,
output [15:0] up_es_rdata_11, output [15:0] up_es_rdata_11,
output up_es_ready_11, output up_es_ready_11,
input up_rx_pll_rst_11,
output up_rx_pll_locked_11, output up_rx_pll_locked_11,
input up_rx_rst_11, input up_rx_rst_11,
input up_rx_user_ready_11, input up_rx_user_ready_11,
@ -790,7 +781,6 @@ module util_adxcvr #(
input [15:0] up_rx_wdata_11, input [15:0] up_rx_wdata_11,
output [15:0] up_rx_rdata_11, output [15:0] up_rx_rdata_11,
output up_rx_ready_11, output up_rx_ready_11,
input up_tx_pll_rst_11,
output up_tx_pll_locked_11, output up_tx_pll_locked_11,
input up_tx_rst_11, input up_tx_rst_11,
input up_tx_user_ready_11, input up_tx_user_ready_11,
@ -808,7 +798,9 @@ module util_adxcvr #(
output up_tx_ready_11, output up_tx_ready_11,
input qpll_ref_clk_12, input qpll_ref_clk_12,
input up_qpll_rst_12,
input cpll_ref_clk_12, input cpll_ref_clk_12,
input up_cpll_rst_12,
input rx_12_p, input rx_12_p,
input rx_12_n, input rx_12_n,
@ -841,7 +833,6 @@ module util_adxcvr #(
input [15:0] up_es_wdata_12, input [15:0] up_es_wdata_12,
output [15:0] up_es_rdata_12, output [15:0] up_es_rdata_12,
output up_es_ready_12, output up_es_ready_12,
input up_rx_pll_rst_12,
output up_rx_pll_locked_12, output up_rx_pll_locked_12,
input up_rx_rst_12, input up_rx_rst_12,
input up_rx_user_ready_12, input up_rx_user_ready_12,
@ -857,7 +848,6 @@ module util_adxcvr #(
input [15:0] up_rx_wdata_12, input [15:0] up_rx_wdata_12,
output [15:0] up_rx_rdata_12, output [15:0] up_rx_rdata_12,
output up_rx_ready_12, output up_rx_ready_12,
input up_tx_pll_rst_12,
output up_tx_pll_locked_12, output up_tx_pll_locked_12,
input up_tx_rst_12, input up_tx_rst_12,
input up_tx_user_ready_12, input up_tx_user_ready_12,
@ -875,6 +865,7 @@ module util_adxcvr #(
output up_tx_ready_12, output up_tx_ready_12,
input cpll_ref_clk_13, input cpll_ref_clk_13,
input up_cpll_rst_13,
input rx_13_p, input rx_13_p,
input rx_13_n, input rx_13_n,
@ -900,7 +891,6 @@ module util_adxcvr #(
input [15:0] up_es_wdata_13, input [15:0] up_es_wdata_13,
output [15:0] up_es_rdata_13, output [15:0] up_es_rdata_13,
output up_es_ready_13, output up_es_ready_13,
input up_rx_pll_rst_13,
output up_rx_pll_locked_13, output up_rx_pll_locked_13,
input up_rx_rst_13, input up_rx_rst_13,
input up_rx_user_ready_13, input up_rx_user_ready_13,
@ -916,7 +906,6 @@ module util_adxcvr #(
input [15:0] up_rx_wdata_13, input [15:0] up_rx_wdata_13,
output [15:0] up_rx_rdata_13, output [15:0] up_rx_rdata_13,
output up_rx_ready_13, output up_rx_ready_13,
input up_tx_pll_rst_13,
output up_tx_pll_locked_13, output up_tx_pll_locked_13,
input up_tx_rst_13, input up_tx_rst_13,
input up_tx_user_ready_13, input up_tx_user_ready_13,
@ -934,6 +923,7 @@ module util_adxcvr #(
output up_tx_ready_13, output up_tx_ready_13,
input cpll_ref_clk_14, input cpll_ref_clk_14,
input up_cpll_rst_14,
input rx_14_p, input rx_14_p,
input rx_14_n, input rx_14_n,
@ -959,7 +949,6 @@ module util_adxcvr #(
input [15:0] up_es_wdata_14, input [15:0] up_es_wdata_14,
output [15:0] up_es_rdata_14, output [15:0] up_es_rdata_14,
output up_es_ready_14, output up_es_ready_14,
input up_rx_pll_rst_14,
output up_rx_pll_locked_14, output up_rx_pll_locked_14,
input up_rx_rst_14, input up_rx_rst_14,
input up_rx_user_ready_14, input up_rx_user_ready_14,
@ -975,7 +964,6 @@ module util_adxcvr #(
input [15:0] up_rx_wdata_14, input [15:0] up_rx_wdata_14,
output [15:0] up_rx_rdata_14, output [15:0] up_rx_rdata_14,
output up_rx_ready_14, output up_rx_ready_14,
input up_tx_pll_rst_14,
output up_tx_pll_locked_14, output up_tx_pll_locked_14,
input up_tx_rst_14, input up_tx_rst_14,
input up_tx_user_ready_14, input up_tx_user_ready_14,
@ -993,6 +981,7 @@ module util_adxcvr #(
output up_tx_ready_14, output up_tx_ready_14,
input cpll_ref_clk_15, input cpll_ref_clk_15,
input up_cpll_rst_15,
input rx_15_p, input rx_15_p,
input rx_15_n, input rx_15_n,
@ -1018,7 +1007,6 @@ module util_adxcvr #(
input [15:0] up_es_wdata_15, input [15:0] up_es_wdata_15,
output [15:0] up_es_rdata_15, output [15:0] up_es_rdata_15,
output up_es_ready_15, output up_es_ready_15,
input up_rx_pll_rst_15,
output up_rx_pll_locked_15, output up_rx_pll_locked_15,
input up_rx_rst_15, input up_rx_rst_15,
input up_rx_user_ready_15, input up_rx_user_ready_15,
@ -1034,7 +1022,6 @@ module util_adxcvr #(
input [15:0] up_rx_wdata_15, input [15:0] up_rx_wdata_15,
output [15:0] up_rx_rdata_15, output [15:0] up_rx_rdata_15,
output up_rx_ready_15, output up_rx_ready_15,
input up_tx_pll_rst_15,
output up_tx_pll_locked_15, output up_tx_pll_locked_15,
input up_tx_rst_15, input up_tx_rst_15,
input up_tx_user_ready_15, input up_tx_user_ready_15,
@ -1061,26 +1048,15 @@ module util_adxcvr #(
wire qpll2ch_clk_0; wire qpll2ch_clk_0;
wire qpll2ch_ref_clk_0; wire qpll2ch_ref_clk_0;
wire qpll2ch_locked_0; wire qpll2ch_locked_0;
wire up_qpll_rst_0;
wire qpll2ch_clk_4; wire qpll2ch_clk_4;
wire qpll2ch_ref_clk_4; wire qpll2ch_ref_clk_4;
wire qpll2ch_locked_4; wire qpll2ch_locked_4;
wire up_qpll_rst_4;
wire qpll2ch_clk_8; wire qpll2ch_clk_8;
wire qpll2ch_ref_clk_8; wire qpll2ch_ref_clk_8;
wire qpll2ch_locked_8; wire qpll2ch_locked_8;
wire up_qpll_rst_8;
wire qpll2ch_clk_12; wire qpll2ch_clk_12;
wire qpll2ch_ref_clk_12; wire qpll2ch_ref_clk_12;
wire qpll2ch_locked_12; wire qpll2ch_locked_12;
wire up_qpll_rst_12;
// quad controls
assign up_qpll_rst_0 = (CPLL_TX_OR_RX_N == 0) ? up_tx_pll_rst_0 : up_rx_pll_rst_0;
assign up_qpll_rst_4 = (CPLL_TX_OR_RX_N == 0) ? up_tx_pll_rst_4 : up_rx_pll_rst_4;
assign up_qpll_rst_8 = (CPLL_TX_OR_RX_N == 0) ? up_tx_pll_rst_8 : up_rx_pll_rst_8;
assign up_qpll_rst_12 = (CPLL_TX_OR_RX_N == 0) ? up_tx_pll_rst_12 : up_rx_pll_rst_12;
// instantiations // instantiations
@ -1124,7 +1100,6 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE), .XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
.TX_OUT_DIV (TX_OUT_DIV), .TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLK25_DIV (TX_CLK25_DIV),
.RX_OUT_DIV (RX_OUT_DIV), .RX_OUT_DIV (RX_OUT_DIV),
@ -1137,6 +1112,7 @@ module util_adxcvr #(
.qpll2ch_ref_clk (qpll2ch_ref_clk_0), .qpll2ch_ref_clk (qpll2ch_ref_clk_0),
.qpll2ch_locked (qpll2ch_locked_0), .qpll2ch_locked (qpll2ch_locked_0),
.cpll_ref_clk (cpll_ref_clk_0), .cpll_ref_clk (cpll_ref_clk_0),
.up_cpll_rst (up_cpll_rst_0),
.rx_p (rx_0_p), .rx_p (rx_0_p),
.rx_n (rx_0_n), .rx_n (rx_0_n),
.rx_out_clk (rx_out_clk_0), .rx_out_clk (rx_out_clk_0),
@ -1161,7 +1137,6 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_0), .up_es_wdata (up_es_wdata_0),
.up_es_rdata (up_es_rdata_0), .up_es_rdata (up_es_rdata_0),
.up_es_ready (up_es_ready_0), .up_es_ready (up_es_ready_0),
.up_rx_pll_rst (up_rx_pll_rst_0),
.up_rx_pll_locked (up_rx_pll_locked_0), .up_rx_pll_locked (up_rx_pll_locked_0),
.up_rx_rst (up_rx_rst_0), .up_rx_rst (up_rx_rst_0),
.up_rx_user_ready (up_rx_user_ready_0), .up_rx_user_ready (up_rx_user_ready_0),
@ -1177,7 +1152,6 @@ module util_adxcvr #(
.up_rx_wdata (up_rx_wdata_0), .up_rx_wdata (up_rx_wdata_0),
.up_rx_rdata (up_rx_rdata_0), .up_rx_rdata (up_rx_rdata_0),
.up_rx_ready (up_rx_ready_0), .up_rx_ready (up_rx_ready_0),
.up_tx_pll_rst (up_tx_pll_rst_0),
.up_tx_pll_locked (up_tx_pll_locked_0), .up_tx_pll_locked (up_tx_pll_locked_0),
.up_tx_rst (up_tx_rst_0), .up_tx_rst (up_tx_rst_0),
.up_tx_user_ready (up_tx_user_ready_0), .up_tx_user_ready (up_tx_user_ready_0),
@ -1223,7 +1197,6 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE), .XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
.TX_OUT_DIV (TX_OUT_DIV), .TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLK25_DIV (TX_CLK25_DIV),
.RX_OUT_DIV (RX_OUT_DIV), .RX_OUT_DIV (RX_OUT_DIV),
@ -1236,6 +1209,7 @@ module util_adxcvr #(
.qpll2ch_ref_clk (qpll2ch_ref_clk_0), .qpll2ch_ref_clk (qpll2ch_ref_clk_0),
.qpll2ch_locked (qpll2ch_locked_0), .qpll2ch_locked (qpll2ch_locked_0),
.cpll_ref_clk (cpll_ref_clk_1), .cpll_ref_clk (cpll_ref_clk_1),
.up_cpll_rst (up_cpll_rst_1),
.rx_p (rx_1_p), .rx_p (rx_1_p),
.rx_n (rx_1_n), .rx_n (rx_1_n),
.rx_out_clk (rx_out_clk_1), .rx_out_clk (rx_out_clk_1),
@ -1260,7 +1234,6 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_1), .up_es_wdata (up_es_wdata_1),
.up_es_rdata (up_es_rdata_1), .up_es_rdata (up_es_rdata_1),
.up_es_ready (up_es_ready_1), .up_es_ready (up_es_ready_1),
.up_rx_pll_rst (up_rx_pll_rst_1),
.up_rx_pll_locked (up_rx_pll_locked_1), .up_rx_pll_locked (up_rx_pll_locked_1),
.up_rx_rst (up_rx_rst_1), .up_rx_rst (up_rx_rst_1),
.up_rx_user_ready (up_rx_user_ready_1), .up_rx_user_ready (up_rx_user_ready_1),
@ -1276,7 +1249,6 @@ module util_adxcvr #(
.up_rx_wdata (up_rx_wdata_1), .up_rx_wdata (up_rx_wdata_1),
.up_rx_rdata (up_rx_rdata_1), .up_rx_rdata (up_rx_rdata_1),
.up_rx_ready (up_rx_ready_1), .up_rx_ready (up_rx_ready_1),
.up_tx_pll_rst (up_tx_pll_rst_1),
.up_tx_pll_locked (up_tx_pll_locked_1), .up_tx_pll_locked (up_tx_pll_locked_1),
.up_tx_rst (up_tx_rst_1), .up_tx_rst (up_tx_rst_1),
.up_tx_user_ready (up_tx_user_ready_1), .up_tx_user_ready (up_tx_user_ready_1),
@ -1322,7 +1294,6 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE), .XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
.TX_OUT_DIV (TX_OUT_DIV), .TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLK25_DIV (TX_CLK25_DIV),
.RX_OUT_DIV (RX_OUT_DIV), .RX_OUT_DIV (RX_OUT_DIV),
@ -1335,6 +1306,7 @@ module util_adxcvr #(
.qpll2ch_ref_clk (qpll2ch_ref_clk_0), .qpll2ch_ref_clk (qpll2ch_ref_clk_0),
.qpll2ch_locked (qpll2ch_locked_0), .qpll2ch_locked (qpll2ch_locked_0),
.cpll_ref_clk (cpll_ref_clk_2), .cpll_ref_clk (cpll_ref_clk_2),
.up_cpll_rst (up_cpll_rst_2),
.rx_p (rx_2_p), .rx_p (rx_2_p),
.rx_n (rx_2_n), .rx_n (rx_2_n),
.rx_out_clk (rx_out_clk_2), .rx_out_clk (rx_out_clk_2),
@ -1359,7 +1331,6 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_2), .up_es_wdata (up_es_wdata_2),
.up_es_rdata (up_es_rdata_2), .up_es_rdata (up_es_rdata_2),
.up_es_ready (up_es_ready_2), .up_es_ready (up_es_ready_2),
.up_rx_pll_rst (up_rx_pll_rst_2),
.up_rx_pll_locked (up_rx_pll_locked_2), .up_rx_pll_locked (up_rx_pll_locked_2),
.up_rx_rst (up_rx_rst_2), .up_rx_rst (up_rx_rst_2),
.up_rx_user_ready (up_rx_user_ready_2), .up_rx_user_ready (up_rx_user_ready_2),
@ -1375,7 +1346,6 @@ module util_adxcvr #(
.up_rx_wdata (up_rx_wdata_2), .up_rx_wdata (up_rx_wdata_2),
.up_rx_rdata (up_rx_rdata_2), .up_rx_rdata (up_rx_rdata_2),
.up_rx_ready (up_rx_ready_2), .up_rx_ready (up_rx_ready_2),
.up_tx_pll_rst (up_tx_pll_rst_2),
.up_tx_pll_locked (up_tx_pll_locked_2), .up_tx_pll_locked (up_tx_pll_locked_2),
.up_tx_rst (up_tx_rst_2), .up_tx_rst (up_tx_rst_2),
.up_tx_user_ready (up_tx_user_ready_2), .up_tx_user_ready (up_tx_user_ready_2),
@ -1421,7 +1391,6 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE), .XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
.TX_OUT_DIV (TX_OUT_DIV), .TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLK25_DIV (TX_CLK25_DIV),
.RX_OUT_DIV (RX_OUT_DIV), .RX_OUT_DIV (RX_OUT_DIV),
@ -1434,6 +1403,7 @@ module util_adxcvr #(
.qpll2ch_ref_clk (qpll2ch_ref_clk_0), .qpll2ch_ref_clk (qpll2ch_ref_clk_0),
.qpll2ch_locked (qpll2ch_locked_0), .qpll2ch_locked (qpll2ch_locked_0),
.cpll_ref_clk (cpll_ref_clk_3), .cpll_ref_clk (cpll_ref_clk_3),
.up_cpll_rst (up_cpll_rst_3),
.rx_p (rx_3_p), .rx_p (rx_3_p),
.rx_n (rx_3_n), .rx_n (rx_3_n),
.rx_out_clk (rx_out_clk_3), .rx_out_clk (rx_out_clk_3),
@ -1458,7 +1428,6 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_3), .up_es_wdata (up_es_wdata_3),
.up_es_rdata (up_es_rdata_3), .up_es_rdata (up_es_rdata_3),
.up_es_ready (up_es_ready_3), .up_es_ready (up_es_ready_3),
.up_rx_pll_rst (up_rx_pll_rst_3),
.up_rx_pll_locked (up_rx_pll_locked_3), .up_rx_pll_locked (up_rx_pll_locked_3),
.up_rx_rst (up_rx_rst_3), .up_rx_rst (up_rx_rst_3),
.up_rx_user_ready (up_rx_user_ready_3), .up_rx_user_ready (up_rx_user_ready_3),
@ -1474,7 +1443,6 @@ module util_adxcvr #(
.up_rx_wdata (up_rx_wdata_3), .up_rx_wdata (up_rx_wdata_3),
.up_rx_rdata (up_rx_rdata_3), .up_rx_rdata (up_rx_rdata_3),
.up_rx_ready (up_rx_ready_3), .up_rx_ready (up_rx_ready_3),
.up_tx_pll_rst (up_tx_pll_rst_3),
.up_tx_pll_locked (up_tx_pll_locked_3), .up_tx_pll_locked (up_tx_pll_locked_3),
.up_tx_rst (up_tx_rst_3), .up_tx_rst (up_tx_rst_3),
.up_tx_user_ready (up_tx_user_ready_3), .up_tx_user_ready (up_tx_user_ready_3),
@ -1552,7 +1520,6 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE), .XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
.TX_OUT_DIV (TX_OUT_DIV), .TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLK25_DIV (TX_CLK25_DIV),
.RX_OUT_DIV (RX_OUT_DIV), .RX_OUT_DIV (RX_OUT_DIV),
@ -1565,6 +1532,7 @@ module util_adxcvr #(
.qpll2ch_ref_clk (qpll2ch_ref_clk_4), .qpll2ch_ref_clk (qpll2ch_ref_clk_4),
.qpll2ch_locked (qpll2ch_locked_4), .qpll2ch_locked (qpll2ch_locked_4),
.cpll_ref_clk (cpll_ref_clk_4), .cpll_ref_clk (cpll_ref_clk_4),
.up_cpll_rst (up_cpll_rst_4),
.rx_p (rx_4_p), .rx_p (rx_4_p),
.rx_n (rx_4_n), .rx_n (rx_4_n),
.rx_out_clk (rx_out_clk_4), .rx_out_clk (rx_out_clk_4),
@ -1589,7 +1557,6 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_4), .up_es_wdata (up_es_wdata_4),
.up_es_rdata (up_es_rdata_4), .up_es_rdata (up_es_rdata_4),
.up_es_ready (up_es_ready_4), .up_es_ready (up_es_ready_4),
.up_rx_pll_rst (up_rx_pll_rst_4),
.up_rx_pll_locked (up_rx_pll_locked_4), .up_rx_pll_locked (up_rx_pll_locked_4),
.up_rx_rst (up_rx_rst_4), .up_rx_rst (up_rx_rst_4),
.up_rx_user_ready (up_rx_user_ready_4), .up_rx_user_ready (up_rx_user_ready_4),
@ -1605,7 +1572,6 @@ module util_adxcvr #(
.up_rx_wdata (up_rx_wdata_4), .up_rx_wdata (up_rx_wdata_4),
.up_rx_rdata (up_rx_rdata_4), .up_rx_rdata (up_rx_rdata_4),
.up_rx_ready (up_rx_ready_4), .up_rx_ready (up_rx_ready_4),
.up_tx_pll_rst (up_tx_pll_rst_4),
.up_tx_pll_locked (up_tx_pll_locked_4), .up_tx_pll_locked (up_tx_pll_locked_4),
.up_tx_rst (up_tx_rst_4), .up_tx_rst (up_tx_rst_4),
.up_tx_user_ready (up_tx_user_ready_4), .up_tx_user_ready (up_tx_user_ready_4),
@ -1651,7 +1617,6 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE), .XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
.TX_OUT_DIV (TX_OUT_DIV), .TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLK25_DIV (TX_CLK25_DIV),
.RX_OUT_DIV (RX_OUT_DIV), .RX_OUT_DIV (RX_OUT_DIV),
@ -1664,6 +1629,7 @@ module util_adxcvr #(
.qpll2ch_ref_clk (qpll2ch_ref_clk_4), .qpll2ch_ref_clk (qpll2ch_ref_clk_4),
.qpll2ch_locked (qpll2ch_locked_4), .qpll2ch_locked (qpll2ch_locked_4),
.cpll_ref_clk (cpll_ref_clk_5), .cpll_ref_clk (cpll_ref_clk_5),
.up_cpll_rst (up_cpll_rst_5),
.rx_p (rx_5_p), .rx_p (rx_5_p),
.rx_n (rx_5_n), .rx_n (rx_5_n),
.rx_out_clk (rx_out_clk_5), .rx_out_clk (rx_out_clk_5),
@ -1688,7 +1654,6 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_5), .up_es_wdata (up_es_wdata_5),
.up_es_rdata (up_es_rdata_5), .up_es_rdata (up_es_rdata_5),
.up_es_ready (up_es_ready_5), .up_es_ready (up_es_ready_5),
.up_rx_pll_rst (up_rx_pll_rst_5),
.up_rx_pll_locked (up_rx_pll_locked_5), .up_rx_pll_locked (up_rx_pll_locked_5),
.up_rx_rst (up_rx_rst_5), .up_rx_rst (up_rx_rst_5),
.up_rx_user_ready (up_rx_user_ready_5), .up_rx_user_ready (up_rx_user_ready_5),
@ -1704,7 +1669,6 @@ module util_adxcvr #(
.up_rx_wdata (up_rx_wdata_5), .up_rx_wdata (up_rx_wdata_5),
.up_rx_rdata (up_rx_rdata_5), .up_rx_rdata (up_rx_rdata_5),
.up_rx_ready (up_rx_ready_5), .up_rx_ready (up_rx_ready_5),
.up_tx_pll_rst (up_tx_pll_rst_5),
.up_tx_pll_locked (up_tx_pll_locked_5), .up_tx_pll_locked (up_tx_pll_locked_5),
.up_tx_rst (up_tx_rst_5), .up_tx_rst (up_tx_rst_5),
.up_tx_user_ready (up_tx_user_ready_5), .up_tx_user_ready (up_tx_user_ready_5),
@ -1750,7 +1714,6 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE), .XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
.TX_OUT_DIV (TX_OUT_DIV), .TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLK25_DIV (TX_CLK25_DIV),
.RX_OUT_DIV (RX_OUT_DIV), .RX_OUT_DIV (RX_OUT_DIV),
@ -1763,6 +1726,7 @@ module util_adxcvr #(
.qpll2ch_ref_clk (qpll2ch_ref_clk_4), .qpll2ch_ref_clk (qpll2ch_ref_clk_4),
.qpll2ch_locked (qpll2ch_locked_4), .qpll2ch_locked (qpll2ch_locked_4),
.cpll_ref_clk (cpll_ref_clk_6), .cpll_ref_clk (cpll_ref_clk_6),
.up_cpll_rst (up_cpll_rst_6),
.rx_p (rx_6_p), .rx_p (rx_6_p),
.rx_n (rx_6_n), .rx_n (rx_6_n),
.rx_out_clk (rx_out_clk_6), .rx_out_clk (rx_out_clk_6),
@ -1787,7 +1751,6 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_6), .up_es_wdata (up_es_wdata_6),
.up_es_rdata (up_es_rdata_6), .up_es_rdata (up_es_rdata_6),
.up_es_ready (up_es_ready_6), .up_es_ready (up_es_ready_6),
.up_rx_pll_rst (up_rx_pll_rst_6),
.up_rx_pll_locked (up_rx_pll_locked_6), .up_rx_pll_locked (up_rx_pll_locked_6),
.up_rx_rst (up_rx_rst_6), .up_rx_rst (up_rx_rst_6),
.up_rx_user_ready (up_rx_user_ready_6), .up_rx_user_ready (up_rx_user_ready_6),
@ -1803,7 +1766,6 @@ module util_adxcvr #(
.up_rx_wdata (up_rx_wdata_6), .up_rx_wdata (up_rx_wdata_6),
.up_rx_rdata (up_rx_rdata_6), .up_rx_rdata (up_rx_rdata_6),
.up_rx_ready (up_rx_ready_6), .up_rx_ready (up_rx_ready_6),
.up_tx_pll_rst (up_tx_pll_rst_6),
.up_tx_pll_locked (up_tx_pll_locked_6), .up_tx_pll_locked (up_tx_pll_locked_6),
.up_tx_rst (up_tx_rst_6), .up_tx_rst (up_tx_rst_6),
.up_tx_user_ready (up_tx_user_ready_6), .up_tx_user_ready (up_tx_user_ready_6),
@ -1849,7 +1811,6 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE), .XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
.TX_OUT_DIV (TX_OUT_DIV), .TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLK25_DIV (TX_CLK25_DIV),
.RX_OUT_DIV (RX_OUT_DIV), .RX_OUT_DIV (RX_OUT_DIV),
@ -1862,6 +1823,7 @@ module util_adxcvr #(
.qpll2ch_ref_clk (qpll2ch_ref_clk_4), .qpll2ch_ref_clk (qpll2ch_ref_clk_4),
.qpll2ch_locked (qpll2ch_locked_4), .qpll2ch_locked (qpll2ch_locked_4),
.cpll_ref_clk (cpll_ref_clk_7), .cpll_ref_clk (cpll_ref_clk_7),
.up_cpll_rst (up_cpll_rst_7),
.rx_p (rx_7_p), .rx_p (rx_7_p),
.rx_n (rx_7_n), .rx_n (rx_7_n),
.rx_out_clk (rx_out_clk_7), .rx_out_clk (rx_out_clk_7),
@ -1886,7 +1848,6 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_7), .up_es_wdata (up_es_wdata_7),
.up_es_rdata (up_es_rdata_7), .up_es_rdata (up_es_rdata_7),
.up_es_ready (up_es_ready_7), .up_es_ready (up_es_ready_7),
.up_rx_pll_rst (up_rx_pll_rst_7),
.up_rx_pll_locked (up_rx_pll_locked_7), .up_rx_pll_locked (up_rx_pll_locked_7),
.up_rx_rst (up_rx_rst_7), .up_rx_rst (up_rx_rst_7),
.up_rx_user_ready (up_rx_user_ready_7), .up_rx_user_ready (up_rx_user_ready_7),
@ -1902,7 +1863,6 @@ module util_adxcvr #(
.up_rx_wdata (up_rx_wdata_7), .up_rx_wdata (up_rx_wdata_7),
.up_rx_rdata (up_rx_rdata_7), .up_rx_rdata (up_rx_rdata_7),
.up_rx_ready (up_rx_ready_7), .up_rx_ready (up_rx_ready_7),
.up_tx_pll_rst (up_tx_pll_rst_7),
.up_tx_pll_locked (up_tx_pll_locked_7), .up_tx_pll_locked (up_tx_pll_locked_7),
.up_tx_rst (up_tx_rst_7), .up_tx_rst (up_tx_rst_7),
.up_tx_user_ready (up_tx_user_ready_7), .up_tx_user_ready (up_tx_user_ready_7),
@ -1980,7 +1940,6 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE), .XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
.TX_OUT_DIV (TX_OUT_DIV), .TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLK25_DIV (TX_CLK25_DIV),
.RX_OUT_DIV (RX_OUT_DIV), .RX_OUT_DIV (RX_OUT_DIV),
@ -1993,6 +1952,7 @@ module util_adxcvr #(
.qpll2ch_ref_clk (qpll2ch_ref_clk_8), .qpll2ch_ref_clk (qpll2ch_ref_clk_8),
.qpll2ch_locked (qpll2ch_locked_8), .qpll2ch_locked (qpll2ch_locked_8),
.cpll_ref_clk (cpll_ref_clk_8), .cpll_ref_clk (cpll_ref_clk_8),
.up_cpll_rst (up_cpll_rst_8),
.rx_p (rx_8_p), .rx_p (rx_8_p),
.rx_n (rx_8_n), .rx_n (rx_8_n),
.rx_out_clk (rx_out_clk_8), .rx_out_clk (rx_out_clk_8),
@ -2017,7 +1977,6 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_8), .up_es_wdata (up_es_wdata_8),
.up_es_rdata (up_es_rdata_8), .up_es_rdata (up_es_rdata_8),
.up_es_ready (up_es_ready_8), .up_es_ready (up_es_ready_8),
.up_rx_pll_rst (up_rx_pll_rst_8),
.up_rx_pll_locked (up_rx_pll_locked_8), .up_rx_pll_locked (up_rx_pll_locked_8),
.up_rx_rst (up_rx_rst_8), .up_rx_rst (up_rx_rst_8),
.up_rx_user_ready (up_rx_user_ready_8), .up_rx_user_ready (up_rx_user_ready_8),
@ -2033,7 +1992,6 @@ module util_adxcvr #(
.up_rx_wdata (up_rx_wdata_8), .up_rx_wdata (up_rx_wdata_8),
.up_rx_rdata (up_rx_rdata_8), .up_rx_rdata (up_rx_rdata_8),
.up_rx_ready (up_rx_ready_8), .up_rx_ready (up_rx_ready_8),
.up_tx_pll_rst (up_tx_pll_rst_8),
.up_tx_pll_locked (up_tx_pll_locked_8), .up_tx_pll_locked (up_tx_pll_locked_8),
.up_tx_rst (up_tx_rst_8), .up_tx_rst (up_tx_rst_8),
.up_tx_user_ready (up_tx_user_ready_8), .up_tx_user_ready (up_tx_user_ready_8),
@ -2079,7 +2037,6 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE), .XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
.TX_OUT_DIV (TX_OUT_DIV), .TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLK25_DIV (TX_CLK25_DIV),
.RX_OUT_DIV (RX_OUT_DIV), .RX_OUT_DIV (RX_OUT_DIV),
@ -2092,6 +2049,7 @@ module util_adxcvr #(
.qpll2ch_ref_clk (qpll2ch_ref_clk_8), .qpll2ch_ref_clk (qpll2ch_ref_clk_8),
.qpll2ch_locked (qpll2ch_locked_8), .qpll2ch_locked (qpll2ch_locked_8),
.cpll_ref_clk (cpll_ref_clk_9), .cpll_ref_clk (cpll_ref_clk_9),
.up_cpll_rst (up_cpll_rst_9),
.rx_p (rx_9_p), .rx_p (rx_9_p),
.rx_n (rx_9_n), .rx_n (rx_9_n),
.rx_out_clk (rx_out_clk_9), .rx_out_clk (rx_out_clk_9),
@ -2116,7 +2074,6 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_9), .up_es_wdata (up_es_wdata_9),
.up_es_rdata (up_es_rdata_9), .up_es_rdata (up_es_rdata_9),
.up_es_ready (up_es_ready_9), .up_es_ready (up_es_ready_9),
.up_rx_pll_rst (up_rx_pll_rst_9),
.up_rx_pll_locked (up_rx_pll_locked_9), .up_rx_pll_locked (up_rx_pll_locked_9),
.up_rx_rst (up_rx_rst_9), .up_rx_rst (up_rx_rst_9),
.up_rx_user_ready (up_rx_user_ready_9), .up_rx_user_ready (up_rx_user_ready_9),
@ -2132,7 +2089,6 @@ module util_adxcvr #(
.up_rx_wdata (up_rx_wdata_9), .up_rx_wdata (up_rx_wdata_9),
.up_rx_rdata (up_rx_rdata_9), .up_rx_rdata (up_rx_rdata_9),
.up_rx_ready (up_rx_ready_9), .up_rx_ready (up_rx_ready_9),
.up_tx_pll_rst (up_tx_pll_rst_9),
.up_tx_pll_locked (up_tx_pll_locked_9), .up_tx_pll_locked (up_tx_pll_locked_9),
.up_tx_rst (up_tx_rst_9), .up_tx_rst (up_tx_rst_9),
.up_tx_user_ready (up_tx_user_ready_9), .up_tx_user_ready (up_tx_user_ready_9),
@ -2178,7 +2134,6 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE), .XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
.TX_OUT_DIV (TX_OUT_DIV), .TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLK25_DIV (TX_CLK25_DIV),
.RX_OUT_DIV (RX_OUT_DIV), .RX_OUT_DIV (RX_OUT_DIV),
@ -2191,6 +2146,7 @@ module util_adxcvr #(
.qpll2ch_ref_clk (qpll2ch_ref_clk_8), .qpll2ch_ref_clk (qpll2ch_ref_clk_8),
.qpll2ch_locked (qpll2ch_locked_8), .qpll2ch_locked (qpll2ch_locked_8),
.cpll_ref_clk (cpll_ref_clk_10), .cpll_ref_clk (cpll_ref_clk_10),
.up_cpll_rst (up_cpll_rst_10),
.rx_p (rx_10_p), .rx_p (rx_10_p),
.rx_n (rx_10_n), .rx_n (rx_10_n),
.rx_out_clk (rx_out_clk_10), .rx_out_clk (rx_out_clk_10),
@ -2215,7 +2171,6 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_10), .up_es_wdata (up_es_wdata_10),
.up_es_rdata (up_es_rdata_10), .up_es_rdata (up_es_rdata_10),
.up_es_ready (up_es_ready_10), .up_es_ready (up_es_ready_10),
.up_rx_pll_rst (up_rx_pll_rst_10),
.up_rx_pll_locked (up_rx_pll_locked_10), .up_rx_pll_locked (up_rx_pll_locked_10),
.up_rx_rst (up_rx_rst_10), .up_rx_rst (up_rx_rst_10),
.up_rx_user_ready (up_rx_user_ready_10), .up_rx_user_ready (up_rx_user_ready_10),
@ -2231,7 +2186,6 @@ module util_adxcvr #(
.up_rx_wdata (up_rx_wdata_10), .up_rx_wdata (up_rx_wdata_10),
.up_rx_rdata (up_rx_rdata_10), .up_rx_rdata (up_rx_rdata_10),
.up_rx_ready (up_rx_ready_10), .up_rx_ready (up_rx_ready_10),
.up_tx_pll_rst (up_tx_pll_rst_10),
.up_tx_pll_locked (up_tx_pll_locked_10), .up_tx_pll_locked (up_tx_pll_locked_10),
.up_tx_rst (up_tx_rst_10), .up_tx_rst (up_tx_rst_10),
.up_tx_user_ready (up_tx_user_ready_10), .up_tx_user_ready (up_tx_user_ready_10),
@ -2277,7 +2231,6 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE), .XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
.TX_OUT_DIV (TX_OUT_DIV), .TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLK25_DIV (TX_CLK25_DIV),
.RX_OUT_DIV (RX_OUT_DIV), .RX_OUT_DIV (RX_OUT_DIV),
@ -2290,6 +2243,7 @@ module util_adxcvr #(
.qpll2ch_ref_clk (qpll2ch_ref_clk_8), .qpll2ch_ref_clk (qpll2ch_ref_clk_8),
.qpll2ch_locked (qpll2ch_locked_8), .qpll2ch_locked (qpll2ch_locked_8),
.cpll_ref_clk (cpll_ref_clk_11), .cpll_ref_clk (cpll_ref_clk_11),
.up_cpll_rst (up_cpll_rst_11),
.rx_p (rx_11_p), .rx_p (rx_11_p),
.rx_n (rx_11_n), .rx_n (rx_11_n),
.rx_out_clk (rx_out_clk_11), .rx_out_clk (rx_out_clk_11),
@ -2314,7 +2268,6 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_11), .up_es_wdata (up_es_wdata_11),
.up_es_rdata (up_es_rdata_11), .up_es_rdata (up_es_rdata_11),
.up_es_ready (up_es_ready_11), .up_es_ready (up_es_ready_11),
.up_rx_pll_rst (up_rx_pll_rst_11),
.up_rx_pll_locked (up_rx_pll_locked_11), .up_rx_pll_locked (up_rx_pll_locked_11),
.up_rx_rst (up_rx_rst_11), .up_rx_rst (up_rx_rst_11),
.up_rx_user_ready (up_rx_user_ready_11), .up_rx_user_ready (up_rx_user_ready_11),
@ -2330,7 +2283,6 @@ module util_adxcvr #(
.up_rx_wdata (up_rx_wdata_11), .up_rx_wdata (up_rx_wdata_11),
.up_rx_rdata (up_rx_rdata_11), .up_rx_rdata (up_rx_rdata_11),
.up_rx_ready (up_rx_ready_11), .up_rx_ready (up_rx_ready_11),
.up_tx_pll_rst (up_tx_pll_rst_11),
.up_tx_pll_locked (up_tx_pll_locked_11), .up_tx_pll_locked (up_tx_pll_locked_11),
.up_tx_rst (up_tx_rst_11), .up_tx_rst (up_tx_rst_11),
.up_tx_user_ready (up_tx_user_ready_11), .up_tx_user_ready (up_tx_user_ready_11),
@ -2408,7 +2360,6 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE), .XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
.TX_OUT_DIV (TX_OUT_DIV), .TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLK25_DIV (TX_CLK25_DIV),
.RX_OUT_DIV (RX_OUT_DIV), .RX_OUT_DIV (RX_OUT_DIV),
@ -2421,6 +2372,7 @@ module util_adxcvr #(
.qpll2ch_ref_clk (qpll2ch_ref_clk_12), .qpll2ch_ref_clk (qpll2ch_ref_clk_12),
.qpll2ch_locked (qpll2ch_locked_12), .qpll2ch_locked (qpll2ch_locked_12),
.cpll_ref_clk (cpll_ref_clk_12), .cpll_ref_clk (cpll_ref_clk_12),
.up_cpll_rst (up_cpll_rst_12),
.rx_p (rx_12_p), .rx_p (rx_12_p),
.rx_n (rx_12_n), .rx_n (rx_12_n),
.rx_out_clk (rx_out_clk_12), .rx_out_clk (rx_out_clk_12),
@ -2445,7 +2397,6 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_12), .up_es_wdata (up_es_wdata_12),
.up_es_rdata (up_es_rdata_12), .up_es_rdata (up_es_rdata_12),
.up_es_ready (up_es_ready_12), .up_es_ready (up_es_ready_12),
.up_rx_pll_rst (up_rx_pll_rst_12),
.up_rx_pll_locked (up_rx_pll_locked_12), .up_rx_pll_locked (up_rx_pll_locked_12),
.up_rx_rst (up_rx_rst_12), .up_rx_rst (up_rx_rst_12),
.up_rx_user_ready (up_rx_user_ready_12), .up_rx_user_ready (up_rx_user_ready_12),
@ -2461,7 +2412,6 @@ module util_adxcvr #(
.up_rx_wdata (up_rx_wdata_12), .up_rx_wdata (up_rx_wdata_12),
.up_rx_rdata (up_rx_rdata_12), .up_rx_rdata (up_rx_rdata_12),
.up_rx_ready (up_rx_ready_12), .up_rx_ready (up_rx_ready_12),
.up_tx_pll_rst (up_tx_pll_rst_12),
.up_tx_pll_locked (up_tx_pll_locked_12), .up_tx_pll_locked (up_tx_pll_locked_12),
.up_tx_rst (up_tx_rst_12), .up_tx_rst (up_tx_rst_12),
.up_tx_user_ready (up_tx_user_ready_12), .up_tx_user_ready (up_tx_user_ready_12),
@ -2507,7 +2457,6 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE), .XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
.TX_OUT_DIV (TX_OUT_DIV), .TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLK25_DIV (TX_CLK25_DIV),
.RX_OUT_DIV (RX_OUT_DIV), .RX_OUT_DIV (RX_OUT_DIV),
@ -2520,6 +2469,7 @@ module util_adxcvr #(
.qpll2ch_ref_clk (qpll2ch_ref_clk_12), .qpll2ch_ref_clk (qpll2ch_ref_clk_12),
.qpll2ch_locked (qpll2ch_locked_12), .qpll2ch_locked (qpll2ch_locked_12),
.cpll_ref_clk (cpll_ref_clk_13), .cpll_ref_clk (cpll_ref_clk_13),
.up_cpll_rst (up_cpll_rst_13),
.rx_p (rx_13_p), .rx_p (rx_13_p),
.rx_n (rx_13_n), .rx_n (rx_13_n),
.rx_out_clk (rx_out_clk_13), .rx_out_clk (rx_out_clk_13),
@ -2544,7 +2494,6 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_13), .up_es_wdata (up_es_wdata_13),
.up_es_rdata (up_es_rdata_13), .up_es_rdata (up_es_rdata_13),
.up_es_ready (up_es_ready_13), .up_es_ready (up_es_ready_13),
.up_rx_pll_rst (up_rx_pll_rst_13),
.up_rx_pll_locked (up_rx_pll_locked_13), .up_rx_pll_locked (up_rx_pll_locked_13),
.up_rx_rst (up_rx_rst_13), .up_rx_rst (up_rx_rst_13),
.up_rx_user_ready (up_rx_user_ready_13), .up_rx_user_ready (up_rx_user_ready_13),
@ -2560,7 +2509,6 @@ module util_adxcvr #(
.up_rx_wdata (up_rx_wdata_13), .up_rx_wdata (up_rx_wdata_13),
.up_rx_rdata (up_rx_rdata_13), .up_rx_rdata (up_rx_rdata_13),
.up_rx_ready (up_rx_ready_13), .up_rx_ready (up_rx_ready_13),
.up_tx_pll_rst (up_tx_pll_rst_13),
.up_tx_pll_locked (up_tx_pll_locked_13), .up_tx_pll_locked (up_tx_pll_locked_13),
.up_tx_rst (up_tx_rst_13), .up_tx_rst (up_tx_rst_13),
.up_tx_user_ready (up_tx_user_ready_13), .up_tx_user_ready (up_tx_user_ready_13),
@ -2606,7 +2554,6 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE), .XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
.TX_OUT_DIV (TX_OUT_DIV), .TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLK25_DIV (TX_CLK25_DIV),
.RX_OUT_DIV (RX_OUT_DIV), .RX_OUT_DIV (RX_OUT_DIV),
@ -2619,6 +2566,7 @@ module util_adxcvr #(
.qpll2ch_ref_clk (qpll2ch_ref_clk_12), .qpll2ch_ref_clk (qpll2ch_ref_clk_12),
.qpll2ch_locked (qpll2ch_locked_12), .qpll2ch_locked (qpll2ch_locked_12),
.cpll_ref_clk (cpll_ref_clk_14), .cpll_ref_clk (cpll_ref_clk_14),
.up_cpll_rst (up_cpll_rst_14),
.rx_p (rx_14_p), .rx_p (rx_14_p),
.rx_n (rx_14_n), .rx_n (rx_14_n),
.rx_out_clk (rx_out_clk_14), .rx_out_clk (rx_out_clk_14),
@ -2643,7 +2591,6 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_14), .up_es_wdata (up_es_wdata_14),
.up_es_rdata (up_es_rdata_14), .up_es_rdata (up_es_rdata_14),
.up_es_ready (up_es_ready_14), .up_es_ready (up_es_ready_14),
.up_rx_pll_rst (up_rx_pll_rst_14),
.up_rx_pll_locked (up_rx_pll_locked_14), .up_rx_pll_locked (up_rx_pll_locked_14),
.up_rx_rst (up_rx_rst_14), .up_rx_rst (up_rx_rst_14),
.up_rx_user_ready (up_rx_user_ready_14), .up_rx_user_ready (up_rx_user_ready_14),
@ -2659,7 +2606,6 @@ module util_adxcvr #(
.up_rx_wdata (up_rx_wdata_14), .up_rx_wdata (up_rx_wdata_14),
.up_rx_rdata (up_rx_rdata_14), .up_rx_rdata (up_rx_rdata_14),
.up_rx_ready (up_rx_ready_14), .up_rx_ready (up_rx_ready_14),
.up_tx_pll_rst (up_tx_pll_rst_14),
.up_tx_pll_locked (up_tx_pll_locked_14), .up_tx_pll_locked (up_tx_pll_locked_14),
.up_tx_rst (up_tx_rst_14), .up_tx_rst (up_tx_rst_14),
.up_tx_user_ready (up_tx_user_ready_14), .up_tx_user_ready (up_tx_user_ready_14),
@ -2705,7 +2651,6 @@ module util_adxcvr #(
.XCVR_TYPE (XCVR_TYPE), .XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.CPLL_TX_OR_RX_N (CPLL_TX_OR_RX_N),
.TX_OUT_DIV (TX_OUT_DIV), .TX_OUT_DIV (TX_OUT_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLK25_DIV (TX_CLK25_DIV),
.RX_OUT_DIV (RX_OUT_DIV), .RX_OUT_DIV (RX_OUT_DIV),
@ -2718,6 +2663,7 @@ module util_adxcvr #(
.qpll2ch_ref_clk (qpll2ch_ref_clk_12), .qpll2ch_ref_clk (qpll2ch_ref_clk_12),
.qpll2ch_locked (qpll2ch_locked_12), .qpll2ch_locked (qpll2ch_locked_12),
.cpll_ref_clk (cpll_ref_clk_15), .cpll_ref_clk (cpll_ref_clk_15),
.up_cpll_rst (up_cpll_rst_15),
.rx_p (rx_15_p), .rx_p (rx_15_p),
.rx_n (rx_15_n), .rx_n (rx_15_n),
.rx_out_clk (rx_out_clk_15), .rx_out_clk (rx_out_clk_15),
@ -2742,7 +2688,6 @@ module util_adxcvr #(
.up_es_wdata (up_es_wdata_15), .up_es_wdata (up_es_wdata_15),
.up_es_rdata (up_es_rdata_15), .up_es_rdata (up_es_rdata_15),
.up_es_ready (up_es_ready_15), .up_es_ready (up_es_ready_15),
.up_rx_pll_rst (up_rx_pll_rst_15),
.up_rx_pll_locked (up_rx_pll_locked_15), .up_rx_pll_locked (up_rx_pll_locked_15),
.up_rx_rst (up_rx_rst_15), .up_rx_rst (up_rx_rst_15),
.up_rx_user_ready (up_rx_user_ready_15), .up_rx_user_ready (up_rx_user_ready_15),
@ -2758,7 +2703,6 @@ module util_adxcvr #(
.up_rx_wdata (up_rx_wdata_15), .up_rx_wdata (up_rx_wdata_15),
.up_rx_rdata (up_rx_rdata_15), .up_rx_rdata (up_rx_rdata_15),
.up_rx_ready (up_rx_ready_15), .up_rx_ready (up_rx_ready_15),
.up_tx_pll_rst (up_tx_pll_rst_15),
.up_tx_pll_locked (up_tx_pll_locked_15), .up_tx_pll_locked (up_tx_pll_locked_15),
.up_tx_rst (up_tx_rst_15), .up_tx_rst (up_tx_rst_15),
.up_tx_user_ready (up_tx_user_ready_15), .up_tx_user_ready (up_tx_user_ready_15),

2
library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
View File

@ -40,7 +40,6 @@ for {set n 0} {$n < 16} {incr n} {
"ready up_es_ready_${n} "] "ready up_es_ready_${n} "]
adi_if_infer_bus ADI:user:if_xcvr_ch slave up_rx_${n} [list \ adi_if_infer_bus ADI:user:if_xcvr_ch slave up_rx_${n} [list \
"pll_rst up_rx_pll_rst_${n} "\
"pll_locked up_rx_pll_locked_${n} "\ "pll_locked up_rx_pll_locked_${n} "\
"rst up_rx_rst_${n} "\ "rst up_rx_rst_${n} "\
"user_ready up_rx_user_ready_${n} "\ "user_ready up_rx_user_ready_${n} "\
@ -58,7 +57,6 @@ for {set n 0} {$n < 16} {incr n} {
"ready up_rx_ready_${n} "] "ready up_rx_ready_${n} "]
adi_if_infer_bus ADI:user:if_xcvr_ch slave up_tx_${n} [list \ adi_if_infer_bus ADI:user:if_xcvr_ch slave up_tx_${n} [list \
"pll_rst up_tx_pll_rst_${n} "\
"pll_locked up_tx_pll_locked_${n} "\ "pll_locked up_tx_pll_locked_${n} "\
"rst up_tx_rst_${n} "\ "rst up_tx_rst_${n} "\
"user_ready up_tx_user_ready_${n} "\ "user_ready up_tx_user_ready_${n} "\

6
library/xilinx/util_adxcvr/util_adxcvr_xch.v
View File

@ -46,7 +46,6 @@ module util_adxcvr_xch #(
parameter integer CPLL_FBDIV = 2, parameter integer CPLL_FBDIV = 2,
parameter integer CPLL_FBDIV_4_5 = 5, parameter integer CPLL_FBDIV_4_5 = 5,
parameter integer CPLL_TX_OR_RX_N = 0,
parameter integer TX_OUT_DIV = 1, parameter integer TX_OUT_DIV = 1,
parameter integer TX_CLK25_DIV = 20, parameter integer TX_CLK25_DIV = 20,
@ -63,6 +62,7 @@ module util_adxcvr_xch #(
input qpll2ch_ref_clk, input qpll2ch_ref_clk,
input qpll2ch_locked, input qpll2ch_locked,
input cpll_ref_clk, input cpll_ref_clk,
input up_cpll_rst,
// receive // receive
@ -98,7 +98,6 @@ module util_adxcvr_xch #(
input [15:0] up_es_wdata, input [15:0] up_es_wdata,
output [15:0] up_es_rdata, output [15:0] up_es_rdata,
output up_es_ready, output up_es_ready,
input up_rx_pll_rst,
output up_rx_pll_locked, output up_rx_pll_locked,
input up_rx_rst, input up_rx_rst,
input up_rx_user_ready, input up_rx_user_ready,
@ -114,7 +113,6 @@ module util_adxcvr_xch #(
input [15:0] up_rx_wdata, input [15:0] up_rx_wdata,
output [15:0] up_rx_rdata, output [15:0] up_rx_rdata,
output up_rx_ready, output up_rx_ready,
input up_tx_pll_rst,
output up_tx_pll_locked, output up_tx_pll_locked,
input up_tx_rst, input up_tx_rst,
input up_tx_user_ready, input up_tx_user_ready,
@ -155,7 +153,6 @@ module util_adxcvr_xch #(
// internal signals // internal signals
wire up_cpll_rst;
wire up_es_enb_s; wire up_es_enb_s;
wire up_rx_enb_s; wire up_rx_enb_s;
wire up_tx_enb_s; wire up_tx_enb_s;
@ -177,7 +174,6 @@ module util_adxcvr_xch #(
// pll // pll
assign up_cpll_rst = (CPLL_TX_OR_RX_N == 1) ? up_tx_pll_rst : up_rx_pll_rst;
assign up_rx_pll_locked = (up_rx_sys_clk_sel == 2'd3) ? qpll2ch_locked : cpll_locked_s; assign up_rx_pll_locked = (up_rx_sys_clk_sel == 2'd3) ? qpll2ch_locked : cpll_locked_s;
assign up_tx_pll_locked = (up_tx_sys_clk_sel == 2'd3) ? qpll2ch_locked : cpll_locked_s; assign up_tx_pll_locked = (up_tx_sys_clk_sel == 2'd3) ? qpll2ch_locked : cpll_locked_s;