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util_dac_unpack: Fix unpack order with 1 channel 

Due to the delay between the dac_valid and the fifo_valid signal we need to
have two counters. One counter which counts the number of incoming
dac_valid signals and generates the dma_rd signal and one counter for the
offset which gets set to 0 when fifo_valid is set.

This fixes issues with the unpack order when only one channel is active.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2014-09-30 18:48:04 +02:00 committed by Istvan Csomortani
parent dd70320b00
commit 3d5ef9a8ed
1 changed files with 17 additions and 10 deletions
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27
library/util_dac_unpack/util_dac_unpack.v
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@ -134,7 +134,8 @@ module util_dac_unpack (
reg [DATA_WIDTH*CHANNELS-1:0] dac_data = 'h00;
reg [DMA_WIDTH-1:0] buffer = 'h00;
reg dma_rd = 1'b0;
reg [$clog2(CHANNELS)-1:0] counter = 'h00;
reg [$clog2(CHANNELS)-1:0] rd_counter = 'h00;
reg [$clog2(CHANNELS)-1:0] req_counter = 'h00;
reg [CHANNELS-1:0] dac_enable_d1 = 'h00;
assign dac_enable[0] = dac_enable_00;
@ -187,18 +188,22 @@ module util_dac_unpack (
always @(posedge clk) begin
if (fifo_valid == 1'b1) begin
buffer <= dma_data;
buffer <= dma_data;
rd_counter <= 'h0;
end else if (dac_chan_valid == 1'b1) begin
rd_counter <= rd_counter + enable_reduce(CHANNELS);
end
end
always @(posedge clk) begin
dma_rd <= 1'b0;
if (dac_enable != dac_enable_d1) begin
counter <= 'h00;
req_counter <= 'h00;
end else if (dac_chan_valid == 1'b1) begin
counter <= counter + enable_reduce(CHANNELS);
if (counter == 'h00)
req_counter <= req_counter + enable_reduce(CHANNELS);
if (req_counter == 'h00) begin
dma_rd <= 1'b1;
end
end
dac_enable_d1 <= dac_enable;
end
@ -213,12 +218,14 @@ module util_dac_unpack (
generate
genvar j;
for (j = 0; j < CHANNELS; j = j + 1) begin : gen_dac_data
assign offset[j] = counter + enable_reduce(j);
assign offset[j] = rd_counter + enable_reduce(j);
always @(posedge clk) begin
if (dac_enable[j])
dac_data[DATA_WIDTH+j*DATA_WIDTH-1:j*DATA_WIDTH] <= data_array[offset[j]];
else
dac_data[DATA_WIDTH+j*DATA_WIDTH-1:j*DATA_WIDTH] <= 'h0000;
if (dac_chan_valid) begin
if (dac_enable[j])
dac_data[DATA_WIDTH+j*DATA_WIDTH-1:j*DATA_WIDTH] <= data_array[offset[j]];
else
dac_data[DATA_WIDTH+j*DATA_WIDTH-1:j*DATA_WIDTH] <= 'h0000;
end
end
end
endgenerate