util_cpack: Added reset interface
parent
f7d28e0944
commit
3d1ffe7bd2
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@ -38,7 +38,6 @@ set_parameter_property CH_CNT HDL_PARAMETER true
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# defaults
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ad_alt_intf clock adc_clk input 1
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ad_alt_intf signal adc_rst input 1
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ad_alt_intf signal adc_valid output 1
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ad_alt_intf signal adc_sync output 1
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ad_alt_intf signal adc_data output CH_CNT*CH_DW
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@ -46,6 +45,10 @@ ad_alt_intf signal adc_valid_0 input 1
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ad_alt_intf signal adc_enable_0 input 1
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ad_alt_intf signal adc_data_0 input CH_DW
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add_interface adc_reset reset end
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set_interface_property adc_reset associatedClock if_adc_clk
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add_interface_port adc_reset adc_rst reset Input 1
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proc p_util_cpack {} {
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if {[get_parameter_value CH_CNT] > 1} {
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