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pzsdr2: ccusb_lvdsr, updated project for the latest schematic

main
Adrian Costina 2016-11-22 16:54:13 +02:00
parent aff45eae5f
commit 3d0049d274
5 changed files with 93 additions and 78 deletions
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17
projects/pzsdr2/ccusb_lvds/Makefile
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@ -7,18 +7,15 @@
M_DEPS += system_top.v
M_DEPS += system_project.tcl
M_DEPS += system_constr.xdc
M_DEPS += system_bd.tcl
M_DEPS += ../common/pzsdr2_constr_lvds.xdc
M_DEPS += ../common/pzsdr2_constr.xdc
M_DEPS += ../common/pzsdr2_bd.tcl
M_DEPS += ../common/ccusb_constr.xdc
M_DEPS += ../common/ccusb_bd.tcl
M_DEPS += ../../scripts/adi_project.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../fmcomms2/common/fmcomms2_bd.tcl
M_DEPS += ../../common/xilinx/sys_wfifo.tcl
M_DEPS += ../../common/pzsdr/pzsdr_system_ps7.tcl
M_DEPS += ../../common/pzsdr/pzsdr_system_constr.xdc
M_DEPS += ../../common/pzsdr/pzsdr_system_bd.tcl
M_DEPS += ../../common/pzsdr/pzsdr_lvds_system_constr.xdc
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
@ -47,7 +44,7 @@ M_FLIST += *.ip_user_files
.PHONY: all lib clean clean-all
all: lib ccusb_lvds_pzsdr.sdk/system_top.hdf
all: lib pzsdr2_ccusb_lvds.sdk/system_top.hdf
clean:
@ -64,9 +61,9 @@ clean-all:clean
make -C ../../../library/util_wfifo clean
ccusb_lvds_pzsdr.sdk/system_top.hdf: $(M_DEPS)
pzsdr2_ccusb_lvds.sdk/system_top.hdf: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) system_project.tcl >> ccusb_lvds_pzsdr_vivado.log 2>&1
$(M_VIVADO) system_project.tcl >> pzsdr2_ccusb_lvds_vivado.log 2>&1
lib:

4
projects/pzsdr2/ccusb_lvds/system_bd.tcl
View File

@ -1,4 +1,6 @@
source $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_bd.tcl
source ../common/pzsdr2_bd.tcl
source ../common/ccusb_bd.tcl
cfg_ad9361_interface LVDS

17
projects/pzsdr2/ccusb_lvds/system_project.tcl
View File

@ -3,17 +3,18 @@ source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create ccusb_lvds_pzsdr
adi_project_files ccusb_lvds_pzsdr [list \
set p_device "xc7z035ifbg676-2L"
adi_project_create pzsdr2_ccusb_lvds
adi_project_files pzsdr2_ccusb_lvds [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc" \
"$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
"../common/pzsdr2_constr.xdc" \
"../common/pzsdr2_constr_lvds.xdc" \
"../common/ccusb_constr.xdc" ]
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
set_property PROCESSING_ORDER LATE [get_files system_constr.xdc]
set_property PROCESSING_ORDER EARLY [get_files ../common/pzsdr2_constr.xdc]
set_property PROCESSING_ORDER LATE [get_files ../common/ccusb_constr.xdc]
adi_project_run ccusb_lvds_pzsdr
adi_project_run pzsdr2_ccusb_lvds

19
projects/pzsdr2/ccusb_lvds/system_top.v
View File

@ -92,18 +92,21 @@ module system_top (
input usb_fx3_uart_tx,
output usb_fx3_uart_rx,
input [ 3:0] fifo_rdy,
input [ 7:0] fifo_rdy,
inout [31:0] data,
output [1:0] addr,
output [ 4:0] addr,
output pclk,
output slcs_n,
output slrd_n,
output sloe_n,
output slwr_n,
output pktend_n,
output epswitch_n,
output [ 1:0] pmode,
output reset_n,
output [ 2:0] pmode,
output spi_csn,
output spi_clk,
@ -118,7 +121,11 @@ module system_top (
// assignments
assign pmode = 2'b11;
assign pmode = 3'b111;
assign addr[4:2] = 3'b000;
assign epswitch_n = 1'b1;
assign reset_n = 1'b1;
// instantiations
@ -213,10 +220,10 @@ module system_top (
.usb_fx3_uart_rx(usb_fx3_uart_rx),
.dma_rdy(),
.dma_wmk(),
.fifo_rdy(fifo_rdy),
.fifo_rdy(fifo_rdy[3:0]),
.pclk(pclk),
.data(data),
.addr(addr),
.addr(addr[1:0]),
.slcs_n(slcs_n),
.slrd_n(slrd_n),
.sloe_n(sloe_n),

114
projects/pzsdr2/ccusb_lvds/system_constr.xdc → projects/pzsdr2/common/ccusb_constr.xdc
View File

@ -1,63 +1,71 @@
# Default constraints have LVCMOS25, overwite it
set_property -dict {IOSTANDARD LVCMOS18} [get_ports iic_scl] ; ## IO_L5P_T0_13
set_property -dict {IOSTANDARD LVCMOS18} [get_ports iic_sda] ; ## IO_L5N_T0_13
set_property -dict {IOSTANDARD LVCMOS18} [get_ports iic_scl] ;
set_property -dict {IOSTANDARD LVCMOS18} [get_ports iic_sda] ;
# USB_FX3
set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports data[0]] ; ## IO_L01_34_JX4_P
set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports data[1]] ; ## IO_L01_34_JX4_N
set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports data[2]] ; ## IO_L03_34_JX4_P
set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVCMOS18} [get_ports data[3]] ; ## IO_L03_34_JX4_N
set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports data[4]] ; ## IO_L05_34_JX4_P
set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports data[5]] ; ## IO_L05_34_JX4_N
set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports data[6]] ; ## IO_L07_34_JX4_P
set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS18} [get_ports data[7]] ; ## IO_L07_34_JX4_N
set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18} [get_ports data[8]] ; ## IO_L09_34_JX4_P
set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVCMOS18} [get_ports data[9]] ; ## IO_L09_34_JX4_N
set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports data[10]] ; ## IO_L11_SRCC_34_JX4_P
set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports data[11]] ; ## IO_L11_SRCC_34_JX4_N
set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports data[12]] ; ## IO_L13_MRCC_34_JX4_P
set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports data[13]] ; ## IO_L13_MRCC_34_JX4_N
set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports data[14]] ; ## IO_L15_34_JX4_P
set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports data[15]] ; ## IO_L15_34_JX4_N
set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports data[16]] ; ## IO_L06_34_JX4_P
set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports data[17]] ; ## IO_L06_34_JX4_N
set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports data[18]] ; ## IO_L08_34_JX4_P
set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS18} [get_ports data[19]] ; ## IO_L08_34_JX4_N
set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports data[20]] ; ## IO_L10_34_JX4_P
set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports data[21]] ; ## IO_L10_34_JX4_N
set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports data[22]] ; ## IO_L12_MRCC_34_JX4_P
set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS18} [get_ports data[23]] ; ## IO_L12_MRCC_34_JX4_N
set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports data[24]] ; ## IO_L14_SRCC_34_JX4_P
set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports data[25]] ; ## IO_L14_SRCC_34_JX4_N
set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports data[26]] ; ## IO_L16_34_JX4_P
set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports data[27]] ; ## IO_L16_34_JX4_N
set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports data[28]] ; ## IO_L18_34_JX4_P
set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports data[29]] ; ## IO_L18_34_JX4_N
set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports data[30]] ; ## IO_L20_34_JX4_P
set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports data[31]] ; ## IO_L20_34_JX4_N
set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports data[30]] ;
set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports data[31]] ;
set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports data[24]] ;
set_property -dict {PACKAGE_PIN G9 IOSTANDARD LVCMOS18} [get_ports data[27]] ;
set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports data[26]] ;
set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports data[21]] ;
set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports data[18]] ;
set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS18} [get_ports data[19]] ;
set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18} [get_ports data[23]] ;
set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVCMOS18} [get_ports data[20]] ;
set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports data[2]] ;
set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports data[14]] ;
set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports data[13]] ;
set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports data[9]] ;
set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports data[12]] ;
set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports data[8]] ;
set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports data[7]] ;
set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports data[3]] ;
set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports data[0]] ;
set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports data[4]] ;
set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports data[5]] ;
set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS18} [get_ports data[28]] ;
set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports data[29]] ;
set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports data[25]] ;
set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports data[22]] ;
set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports data[16]] ;
set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports data[17]] ;
set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports data[15]] ;
set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports data[11]] ;
set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports data[10]] ;
set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports data[6]] ;
set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports data[1]] ;
set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports pclk] ; ## IO_L17_34_JX4_P
set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports pclk] ;
set_property -dict {PACKAGE_PIN G6 IOSTANDARD LVCMOS18} [get_ports addr[0]] ; ## IO_L02_34_JX4_P
set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS18} [get_ports addr[1]] ; ## IO_L17_13_JX2_P
#set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVCMOS18} [get_ports addr[2]] ; ## G34 FMC_LPC_LA31_N
#set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVCMOS18} [get_ports addr[3]] ; ## G33 FMC_LPC_LA31_P
#set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS18} [get_ports addr[4]] ; ## G31 FMC_LPC_LA29_N
set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports addr[0]] ;
set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports addr[1]] ;
set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS18} [get_ports addr[2]] ;
set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVCMOS18} [get_ports addr[3]] ;
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS18} [get_ports addr[4]] ;
set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports slcs_n] ; ## IO_L17_34_JX4_N
set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports slwr_n] ; ## IO_L19_34_JX4_P
set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports sloe_n] ; ## IO_L19_34_JX4_N
set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports slrd_n] ; ## IO_L21_34_JX4_P
set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVCMOS18} [get_ports pktend_n] ; ## IO_L13_MRCC_13_JX2_P
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS18} [get_ports slcs_n] ;
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS18} [get_ports slwr_n] ;
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS18} [get_ports sloe_n] ;
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS18} [get_ports slrd_n] ;
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS18} [get_ports pktend_n] ;
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS18} [get_ports usb_fx3_uart_tx] ; ## IO_L14_SRCC_13_JX2_N
set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS18} [get_ports usb_fx3_uart_rx] ; ## IO_L16_13_JX2_P
set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports usb_fx3_uart_tx] ;
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS18} [get_ports usb_fx3_uart_rx] ;
set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[0]] ; ## IO_L21_34_JX4_N
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[1]] ; ## IO_L11_SRCC_13_JX2_P
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[2]] ; ## IO_L11_SRCC_13_JX2_N
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[3]] ; ## IO_L13_MRCC_13_JX2_N
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[0]] ;
set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[1]] ;
set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[2]] ;
set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[3]] ;
set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[4]] ;
set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[5]] ;
set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[6]] ;
set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports fifo_rdy[7]] ;
set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports pmode[0]] ; ## IO_L02_34_JX4_N
set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports pmode[1]] ; ## IO_L04_34_JX4_P
set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports pmode[0]] ;
set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS18} [get_ports pmode[1]] ;
set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports pmode[2]] ;
set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS18} [get_ports reset_n] ;
set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS18} [get_ports epswitch_n] ;