cn0506_mii: Add support on zc706
AndreiGrozav
AndreiGrozav
parent
e98951d282
commit
3cb2392711
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := cn0506_zc706
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M_DEPS += ../common/cn0506_bd.tcl
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M_DEPS += ../../common/zc706/zc706_system_constr.xdc
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M_DEPS += ../../common/zc706/zc706_system_bd.tcl
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M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
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LIB_DEPS += axi_clkgen
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_hdmi_tx
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LIB_DEPS += axi_spdif_tx
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LIB_DEPS += axi_sysid
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LIB_DEPS += sysid_rom
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include ../../scripts/project-xilinx.mk
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- Connect to FMC LPC
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- VADJ = 2.5V
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- MII mode, Connected to PS7's Ethernet 0(PHY 0) and Ethernet 1(PHY 0)
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@ -0,0 +1,15 @@
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_ENET0_IO EMIO
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ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_IO EMIO
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ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_PERIPHERAL_ENABLE 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_GRP_MDIO_ENABLE 1
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source ../common/cn0506_bd.tcl
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make_bd_intf_pins_external [get_bd_intf_pins sys_ps7/MDIO_ETHERNET_1]
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make_bd_intf_pins_external [get_bd_intf_pins sys_ps7/GMII_ETHERNET_1]
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make_bd_intf_pins_external [get_bd_intf_pins sys_ps7/MDIO_ETHERNET_0]
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make_bd_intf_pins_external [get_bd_intf_pins sys_ps7/GMII_ETHERNET_0]
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set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports mii_rx_clk_a] ; ## G06 FMC_LPC_LA00_CC_P
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set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports mii_rx_er_a] ; ## D08 FMC_LPC_LA01_CC_P
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set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS25} [get_ports mii_rx_dv_a] ; ## H14 FMC_LPC_LA07_N
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set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports {mii_rxd_a[0]}] ; ## H07 FMC_LPC_LA02_P
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set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports {mii_rxd_a[1]}] ; ## H08 FMC_LPC_LA02_N
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set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS25} [get_ports {mii_rxd_a[2]}] ; ## G09 FMC_LPC_LA03_P
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set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports {mii_rxd_a[3]}] ; ## G10 FMC_LPC_LA03_N
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set_property -dict {PACKAGE_PIN Ak15 IOSTANDARD LVCMOS25} [get_ports mii_tx_clk_a] ; ## H11 FMC_LPC_LA04_N
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set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports mii_tx_en_a] ; ## H13 FMC_LPC_LA07_P
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set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {mii_txd_a[0]}] ; ## D14 FMC_LPC_LA09_P
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set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {mii_txd_a[1]}] ; ## D15 FMC_LPC_LA09_N
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set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {mii_txd_a[2]}] ; ## C10 FMC_LPC_LA06_P
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set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {mii_txd_a[3]}] ; ## C11 FMC_LPC_LA06_N
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set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVCMOS25 PULLUP true} [get_ports mdio_fmc_a] ; ## H16 FMC_LPC_LA11_P
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set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVCMOS25} [get_ports mdc_fmc_a] ; ## H17 FMC_LPC_LA11_N
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set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS25} [get_ports reset_a] ; ## H19 FMC_LPC_LA15_P
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set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVCMOS25} [get_ports link_st_a] ; ## H10 FMC_LPC_LA04_P
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set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports mii_crs_a] ; ## G13 FMC_LPC_LA08_N
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set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS25} [get_ports led_0_a] ; ## G12 FMC_LPC_LA08_P
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set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS25} [get_ports led_ar_c_c2m] ; ## G15 FMC_HPC1_LA12_P
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set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVCMOS25} [get_ports led_ar_a_c2m] ; ## G16 FMC_HPC1_LA12_N
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set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVCMOS25} [get_ports led_al_c_c2m] ; ## D17 FMC_LPC_LA13_P
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set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVCMOS25} [get_ports led_al_a_c2m] ; ## D18 FMC_LPC_LA13_N
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set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVCMOS25} [get_ports mii_rx_clk_b] ; ## C22 FMC_LPC_LA18_CC_P
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set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVCMOS25} [get_ports mii_rx_er_b] ; ## D20 FMC_LPC_LA17_CC_P
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set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS25} [get_ports mii_rx_dv_b] ; ## H29 FMC_LPC_LA24_N
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set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVCMOS25} [get_ports {mii_rxd_b[0]}] ; ## H22 FMC_LPC_LA19_P
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set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVCMOS25} [get_ports {mii_rxd_b[1]}] ; ## H23 FMC_LPC_LA19_N
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set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS25} [get_ports {mii_rxd_b[2]}] ; ## G21 FMC_LPC_LA20_P
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set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS25} [get_ports {mii_rxd_b[3]}] ; ## G22 FMC_LPC_LA20_N
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set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVCMOS25} [get_ports mii_tx_clk_b] ; ## G28 FMC_LPC_LA25_N
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set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports mii_tx_en_b] ; ## H28 FMC_LPC_LA24_P
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set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {mii_txd_b[0]}] ; ## H25 FMC_LPC_LA21_P
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set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {mii_txd_b[1]}] ; ## H26 FMC_LPC_LA21_N
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set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {mii_txd_b[2]}] ; ## G24 FMC_LPC_LA22_P
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set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {mii_txd_b[3]}] ; ## G25 FMC_LPC_LA22_N
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set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25 PULLUP true} [get_ports mdio_fmc_b] ; ## H31 FMC_LPC_LA28_P
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set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS25} [get_ports mdc_fmc_b] ; ## H32 FMC_LPC_LA28_N
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set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS25} [get_ports reset_b] ; ## H20 FMC_LPC_LA15_N
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set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports link_st_b] ; ## G27 FMC_LPC_LA25_P
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set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVCMOS25} [get_ports mii_crs_b] ; ## D24 FMC_LPC_LA23_N
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set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVCMOS25} [get_ports led_0_b] ; ## D23 FMC_LPC_LA23_P
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set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25} [get_ports led_bl_c_c2m] ; ## D26 FMC_LPC_LA26_P
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set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports led_bl_a_c2m] ; ## D27 FMC_LPC_LA26_N
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set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports led_br_c_c2m] ; ## G18 FMC_LPC_LA16_P
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set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports led_br_a_c2m] ; ## G19 FMC_LPC_LA16_N
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create_clock -name rx_clk_1 -period 40.0 [get_ports mii_rx_clk_a]
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create_clock -name rx_clk_2 -period 40.0 [get_ports mii_rx_clk_b]
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create_clock -name tx_clk_1 -period 40.0 [get_ports mii_tx_clk_a]
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create_clock -name tx_clk_2 -period 40.0 [get_ports mii_tx_clk_b]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets mii_tx_clk_a*]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets mii_tx_clk_b*]
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project cn0506_zc706
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adi_project_files cn0506_zc706 [list \
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"system_top.v" \
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"system_constr.xdc"\
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"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" \
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"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"]
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adi_project_run cn0506_zc706
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 3:0] ddr_dm,
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inout [31:0] ddr_dq,
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inout [ 3:0] ddr_dqs_n,
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inout [ 3:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [53:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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inout [14:0] gpio_bd,
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output hdmi_out_clk,
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output hdmi_vsync,
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output hdmi_hsync,
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output hdmi_data_e,
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output [23:0] hdmi_data,
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output spdif,
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input sys_rst,
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input sys_clk_p,
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input sys_clk_n,
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inout iic_scl,
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inout iic_sda,
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// mii interface
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output reset_a,
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output mdc_fmc_a,
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inout mdio_fmc_a,
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input [ 3:0] mii_rxd_a,
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input mii_rx_er_a,
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input mii_rx_dv_a,
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input mii_rx_clk_a,
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output [ 3:0] mii_txd_a,
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output mii_tx_en_a,
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input mii_tx_clk_a,
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input link_st_a,
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input mii_crs_a,
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input led_0_a,
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output reset_b,
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output mdc_fmc_b,
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inout mdio_fmc_b,
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input [ 3:0] mii_rxd_b,
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input mii_rx_er_b,
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input mii_rx_dv_b,
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input mii_rx_clk_b,
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output [ 3:0] mii_txd_b,
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output mii_tx_en_b,
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input mii_tx_clk_b,
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input link_st_b,
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input mii_crs_b,
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input led_0_b,
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// LEDs
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output led_ar_c_c2m,
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output led_ar_a_c2m,
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output led_al_c_c2m,
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output led_al_a_c2m,
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output led_br_c_c2m,
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output led_br_a_c2m,
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output led_bl_c_c2m,
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output led_bl_a_c2m
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);
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// internal signals
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wire reset;
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wire [ 1:0] speed_mode_a_s;
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wire [ 1:0] speed_mode_b_s;
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wire [ 3:0] mii_txd_extra_a;
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wire [ 3:0] mii_txd_extra_b;
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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assign reset_a = reset;
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assign reset_b = reset;
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// port a - right led (activity/status) yellow only
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assign led_ar_c_c2m = led_0_a;
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assign led_ar_a_c2m = 1'b0;
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// port a - left led (speed mode) hard-coded to 100M=yellow no feedback from mac
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assign led_al_c_c2m = 1'b1;
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assign led_al_a_c2m = 1'b0;
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// port b - right led (activity/status) yellow only
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assign led_br_c_c2m = led_0_b;
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assign led_br_a_c2m = 1'b0;
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// port b - left led (speed mode) hard-coded to 100M=yellow no feedback from mac
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assign led_bl_c_c2m = 1'b1;
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assign led_bl_a_c2m = 1'b0;
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assign gpio_i[63:36] = gpio_o[63:36];
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assign gpio_i[35] = link_st_a;
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assign gpio_i[34] = link_st_b;
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assign gpio_i[33:15] = gpio_o[33:15];
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ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
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.dio_t (gpio_t[14:0]),
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.dio_i (gpio_o[14:0]),
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.dio_o (gpio_i[14:0]),
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.dio_p (gpio_bd));
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// instantiations
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.spdif (spdif),
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.spi0_clk_i (1'b0),
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.spi0_clk_o (),
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.spi0_csn_0_o (),
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.spi0_csn_1_o (),
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.spi0_csn_2_o (),
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.spi0_csn_i (1'b1),
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.spi0_sdi_i (1'b0),
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.spi0_sdo_i (1'b0),
|
||||
.spi0_sdo_o (),
|
||||
.spi1_clk_i (1'b0),
|
||||
.spi1_clk_o (),
|
||||
.spi1_csn_0_o (),
|
||||
.spi1_csn_1_o (),
|
||||
.spi1_csn_2_o (),
|
||||
.spi1_csn_i (1'b1),
|
||||
.spi1_sdi_i (1'b0),
|
||||
.spi1_sdo_i (1'b0),
|
||||
.spi1_sdo_o(),
|
||||
|
||||
.reset (reset),
|
||||
|
||||
.GMII_ETHERNET_0_0_col(led_0_a),
|
||||
.GMII_ETHERNET_0_0_crs(mii_crs_a),
|
||||
.GMII_ETHERNET_0_0_rx_clk(mii_rx_clk_a),
|
||||
.GMII_ETHERNET_0_0_rx_dv(mii_rx_dv_a),
|
||||
.GMII_ETHERNET_0_0_rx_er(mii_rx_er_a),
|
||||
.GMII_ETHERNET_0_0_rxd({4'h0,mii_rxd_a}),
|
||||
.GMII_ETHERNET_0_0_tx_clk(mii_tx_clk_a),
|
||||
.GMII_ETHERNET_0_0_tx_en(mii_tx_en_a),
|
||||
.GMII_ETHERNET_0_0_tx_er(),
|
||||
.GMII_ETHERNET_0_0_txd({mii_txd_extra_a,mii_txd_a}),
|
||||
.MDIO_ETHERNET_0_0_mdc(mdc_fmc_a),
|
||||
.MDIO_ETHERNET_0_0_mdio_io(mdio_fmc_a),
|
||||
|
||||
.GMII_ETHERNET_1_0_col(led_0_b),
|
||||
.GMII_ETHERNET_1_0_crs(mii_crs_b),
|
||||
.GMII_ETHERNET_1_0_rx_clk(mii_rx_clk_b),
|
||||
.GMII_ETHERNET_1_0_rx_dv(mii_rx_dv_b),
|
||||
.GMII_ETHERNET_1_0_rx_er(mii_rx_er_b),
|
||||
.GMII_ETHERNET_1_0_rxd({4'h0,mii_rxd_b}),
|
||||
.GMII_ETHERNET_1_0_tx_clk(mii_tx_clk_b),
|
||||
.GMII_ETHERNET_1_0_tx_en(mii_tx_en_b),
|
||||
.GMII_ETHERNET_1_0_tx_er(),
|
||||
.GMII_ETHERNET_1_0_txd({mii_txd_extra_b,mii_txd_b}),
|
||||
.MDIO_ETHERNET_1_0_mdc(mdc_fmc_b),
|
||||
.MDIO_ETHERNET_1_0_mdio_io(mdio_fmc_b)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue