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axi_hdmi_tx_es: Drop strange port initializers 

Those were added by mistake. It does not seem to be legal Verilog, but for
some reason Vivado accepts it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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Lars-Peter Clausen 2015-06-30 21:11:12 +02:00
parent 26b0ff9853
commit 3c6d19d33d
1 changed files with 4 additions and 4 deletions
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8
library/axi_hdmi_tx/axi_hdmi_tx_es.v
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@ -56,10 +56,10 @@ module axi_hdmi_tx_es (
// hdmi interface // hdmi interface
input hdmi_clk; input hdmi_clk;
input hdmi_hs_de = 'd0; input hdmi_hs_de;
input hdmi_vs_de = 'd0; input hdmi_vs_de;
input [(DATA_WIDTH-1):0] hdmi_data_de = 'd0; input [(DATA_WIDTH-1):0] hdmi_data_de;
output [(DATA_WIDTH-1):0] hdmi_data = 'd0; output [(DATA_WIDTH-1):0] hdmi_data;
// internal registers // internal registers