From 3c6d19d33dada4ec53f3f1e4f0c31198da50f1e3 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 30 Jun 2015 21:11:12 +0200 Subject: [PATCH] axi_hdmi_tx_es: Drop strange port initializers Those were added by mistake. It does not seem to be legal Verilog, but for some reason Vivado accepts it. Signed-off-by: Lars-Peter Clausen --- library/axi_hdmi_tx/axi_hdmi_tx_es.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_es.v b/library/axi_hdmi_tx/axi_hdmi_tx_es.v index 664f88613..5ecef3aec 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_es.v +++ b/library/axi_hdmi_tx/axi_hdmi_tx_es.v @@ -56,10 +56,10 @@ module axi_hdmi_tx_es ( // hdmi interface input hdmi_clk; - input hdmi_hs_de = 'd0; - input hdmi_vs_de = 'd0; - input [(DATA_WIDTH-1):0] hdmi_data_de = 'd0; - output [(DATA_WIDTH-1):0] hdmi_data = 'd0; + input hdmi_hs_de; + input hdmi_vs_de; + input [(DATA_WIDTH-1):0] hdmi_data_de; + output [(DATA_WIDTH-1):0] hdmi_data; // internal registers