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daq1/a10gx: Remove project

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Istvan Csomortani 2017-05-26 17:05:28 +03:00
parent 414943db4b
commit 3c47d00a96
5 changed files with 0 additions and 477 deletions
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152
projects/daq1/a10gx/Makefile
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
ifeq ($(NIOS2_MMU),)
NIOS2_MMU := 1
endif
export ALT_NIOS_MMU_ENABLED := $(NIOS2_MMU)
M_DEPS += system_top.v
M_DEPS += system_qsys.tcl
M_DEPS += system_project.tcl
M_DEPS += system_constr.sdc
M_DEPS += ../common/daq1_spi.v
M_DEPS += ../common/daq1_qsys.tcl
M_DEPS += ../../scripts/adi_tquest.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../common/altera/sys_gen.tcl
M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
M_DEPS += ../../../library/altera/common/ad_mul.v
M_DEPS += ../../../library/altera/common/up_clock_mon_constr.sdc
M_DEPS += ../../../library/altera/common/up_rst_constr.sdc
M_DEPS += ../../../library/altera/common/up_xfer_cntrl_constr.sdc
M_DEPS += ../../../library/altera/common/up_xfer_status_constr.sdc
M_DEPS += ../../../library/axi_ad9122/axi_ad9122.v
M_DEPS += ../../../library/axi_ad9122/axi_ad9122_channel.v
M_DEPS += ../../../library/axi_ad9122/axi_ad9122_constr.sdc
M_DEPS += ../../../library/axi_ad9122/axi_ad9122_core.v
M_DEPS += ../../../library/axi_ad9122/axi_ad9122_hw.tcl
M_DEPS += ../../../library/axi_ad9122/axi_ad9122_if.v
M_DEPS += ../../../library/axi_ad9684/axi_ad9684.v
M_DEPS += ../../../library/axi_ad9684/axi_ad9684_channel.v
M_DEPS += ../../../library/axi_ad9684/axi_ad9684_constr.sdc
M_DEPS += ../../../library/axi_ad9684/axi_ad9684_hw.tcl
M_DEPS += ../../../library/axi_ad9684/axi_ad9684_if.v
M_DEPS += ../../../library/axi_ad9684/axi_ad9684_pnmon.v
M_DEPS += ../../../library/axi_dmac/2d_transfer.v
M_DEPS += ../../../library/axi_dmac/address_generator.v
M_DEPS += ../../../library/axi_dmac/axi_dmac.v
M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc
M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
M_DEPS += ../../../library/axi_dmac/data_mover.v
M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
M_DEPS += ../../../library/axi_dmac/inc_id.h
M_DEPS += ../../../library/axi_dmac/request_arb.v
M_DEPS += ../../../library/axi_dmac/request_generator.v
M_DEPS += ../../../library/axi_dmac/resp.h
M_DEPS += ../../../library/axi_dmac/response_generator.v
M_DEPS += ../../../library/axi_dmac/response_handler.v
M_DEPS += ../../../library/axi_dmac/splitter.v
M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
M_DEPS += ../../../library/common/ad_axis_inf_rx.v
M_DEPS += ../../../library/common/ad_datafmt.v
M_DEPS += ../../../library/common/ad_dds.v
M_DEPS += ../../../library/common/ad_dds_1.v
M_DEPS += ../../../library/common/ad_dds_sine.v
M_DEPS += ../../../library/common/ad_pnmon.v
M_DEPS += ../../../library/common/ad_rst.v
M_DEPS += ../../../library/common/sync_bits.v
M_DEPS += ../../../library/common/sync_gray.v
M_DEPS += ../../../library/common/up_adc_channel.v
M_DEPS += ../../../library/common/up_adc_common.v
M_DEPS += ../../../library/common/up_axi.v
M_DEPS += ../../../library/common/up_clock_mon.v
M_DEPS += ../../../library/common/up_dac_channel.v
M_DEPS += ../../../library/common/up_dac_common.v
M_DEPS += ../../../library/common/up_delay_cntrl.v
M_DEPS += ../../../library/common/up_xfer_cntrl.v
M_DEPS += ../../../library/common/up_xfer_status.v
M_DEPS += ../../../library/scripts/adi_env.tcl
M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc
M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
M_DEPS += ../../../library/util_axis_fifo/address_gray.v
M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
M_DEPS += ../../../library/util_axis_fifo/address_sync.v
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
M_DEPS += ../../../library/util_cpack/util_cpack.v
M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
M_DEPS += ../../../library/util_upack/util_upack.v
M_DEPS += ../../../library/util_upack/util_upack_dmx.v
M_DEPS += ../../../library/util_upack/util_upack_dsf.v
M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
M_ALTERA := quartus_sh --64bit -t
M_FLIST += *.log
M_FLIST += *_INFO.txt
M_FLIST += *_dump.txt
M_FLIST += db
M_FLIST += *.asm.rpt
M_FLIST += *.done
M_FLIST += *.eda.rpt
M_FLIST += *.fit.*
M_FLIST += *.map.*
M_FLIST += *.sta.*
M_FLIST += *.qsf
M_FLIST += *.qpf
M_FLIST += *.qws
M_FLIST += *.sof
M_FLIST += *.cdf
M_FLIST += *.sld
M_FLIST += *.qdf
M_FLIST += hc_output
M_FLIST += system_bd
M_FLIST += hps_isw_handoff
M_FLIST += hps_sdram_*.csv
M_FLIST += *ddr3_*.csv
M_FLIST += incremental_db
M_FLIST += reconfig_mif
M_FLIST += *.sopcinfo
M_FLIST += *.jdi
M_FLIST += *.pin
M_FLIST += *_summary.csv
M_FLIST += *.dpf
.PHONY: all clean clean-all
all: daq1_a10gx.sof
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
daq1_a10gx.sof: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_ALTERA) system_project.tcl >> daq1_a10gx_quartus.log 2>&1
####################################################################################
####################################################################################

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projects/daq1/a10gx/system_constr.sdc
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
create_clock -period "2.000 ns" -name rx_clk_500mhz [get_ports {adc_clk_in}]
create_clock -period "2.000 ns" -name tx_clk_500mhz [get_ports {dac_clk_in}]
derive_pll_clocks
derive_clock_uncertainty

137
projects/daq1/a10gx/system_project.tcl
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load_package flow
source ../../scripts/adi_env.tcl
project_new daq1_a10gx -overwrite
source "../../common/a10gx/a10gx_system_assign.tcl"
set_global_assignment -name VERILOG_FILE ../common/daq1_spi.v
set_global_assignment -name VERILOG_FILE system_top.v
set_global_assignment -name QSYS_FILE system_bd.qsys
set_global_assignment -name SDC_FILE system_constr.sdc
set_global_assignment -name TOP_LEVEL_ENTITY system_top
# physical interface
set_location_assignment PIN_BA12 -to dac_clk_in ; ## G02 FMC_LPC_CLK1_M2C_P (PIN_BA12, 3C, TERM_ON_BOARD)
set_location_assignment PIN_BA13 -to "dac_clk_in(n)" ; ## G03 FMC_LPC_CLK1_M2C_N (PIN_BA13, 3C, TERM_ON_BOARD)
set_location_assignment PIN_AY15 -to dac_clk_out ; ## G27 FMC_LPC_LA25_P (PIN_AY15, 3B)
set_location_assignment PIN_AY14 -to "dac_clk_out(n)" ; ## G28 FMC_LPC_LA25_N (PIN_AY14, 3B)
set_location_assignment PIN_AV20 -to dac_frame_out ; ## H37 FMC_LPC_LA32_P (PIN_AV20, 3B)
set_location_assignment PIN_AU20 -to "dac_frame_out(n)" ; ## H38 FMC_LPC_LA32_N (PIN_AU20, 3B)
set_location_assignment PIN_AR9 -to dac_data_out[0] ; ## H19 FMC_LPC_LA15_P (PIN_AR9 , 3C)
set_location_assignment PIN_AT9 -to "dac_data_out[0](n)" ; ## H20 FMC_LPC_LA15_N (PIN_AT9 , 3C)
set_location_assignment PIN_AU8 -to dac_data_out[1] ; ## G21 FMC_LPC_LA20_P (PIN_AU8 , 3C)
set_location_assignment PIN_AT8 -to "dac_data_out[1](n)" ; ## G22 FMC_LPC_LA20_N (PIN_AT8 , 3C)
set_location_assignment PIN_AU11 -to dac_data_out[2] ; ## H22 FMC_LPC_LA19_P (PIN_AU11, 3C)
set_location_assignment PIN_AU12 -to "dac_data_out[2](n)" ; ## H23 FMC_LPC_LA19_N (PIN_AU12, 3C)
set_location_assignment PIN_AV19 -to dac_data_out[3] ; ## D20 FMC_LPC_LA17_CC_P (PIN_AV19, 3B)
set_location_assignment PIN_AW19 -to "dac_data_out[3](n)" ; ## D21 FMC_LPC_LA17_CC_N (PIN_AW19, 3B)
set_location_assignment PIN_AU18 -to dac_data_out[4] ; ## D23 FMC_LPC_LA23_P (PIN_AU18, 3B)
set_location_assignment PIN_AT18 -to "dac_data_out[4](n)" ; ## D24 FMC_LPC_LA23_N (PIN_AT18, 3B)
set_location_assignment PIN_AW12 -to dac_data_out[5] ; ## G24 FMC_LPC_LA22_P (PIN_AW12, 3C)
set_location_assignment PIN_AY12 -to "dac_data_out[5](n)" ; ## G25 FMC_LPC_LA22_N (PIN_AY12, 3C)
set_location_assignment PIN_AU21 -to dac_data_out[6] ; ## C22 FMC_LPC_LA18_CC_P (PIN_AU21, 3B)
set_location_assignment PIN_AV21 -to "dac_data_out[6](n)" ; ## C23 FMC_LPC_LA18_CC_N (PIN_AV21, 3B)
set_location_assignment PIN_AY10 -to dac_data_out[7] ; ## H25 FMC_LPC_LA21_P (PIN_AY10, 3C)
set_location_assignment PIN_AY11 -to "dac_data_out[7](n)" ; ## H26 FMC_LPC_LA21_N (PIN_AY11, 3C)
set_location_assignment PIN_AT19 -to dac_data_out[8] ; ## D26 FMC_LPC_LA26_P (PIN_AT19, 3B)
set_location_assignment PIN_AT20 -to "dac_data_out[8](n)" ; ## D27 FMC_LPC_LA26_N (PIN_AT20, 3B)
set_location_assignment PIN_BB15 -to dac_data_out[9] ; ## H28 FMC_LPC_LA24_P (PIN_BB15, 3C)
set_location_assignment PIN_BC15 -to "dac_data_out[9](n)" ; ## H29 FMC_LPC_LA24_N (PIN_BC15, 3C)
set_location_assignment PIN_AW13 -to dac_data_out[10] ; ## D14 FMC_LPC_LA09_P (PIN_AW13, 3C)-- ## C26 FMC_LPC_LA27_P (PIN_AP21, 3B)
set_location_assignment PIN_AV13 -to "dac_data_out[10](n)" ; ## D15 FMC_LPC_LA09_N (PIN_AV13, 3C)-- ## C27 FMC_LPC_LA27_N (PIN_AR21, 3B)
set_location_assignment PIN_BA15 -to dac_data_out[11] ; ## G30 FMC_LPC_LA29_P (PIN_BA15, 3C)
set_location_assignment PIN_BA14 -to "dac_data_out[11](n)" ; ## G31 FMC_LPC_LA29_N (PIN_BA14, 3C)
set_location_assignment PIN_AV11 -to dac_data_out[12] ; ## D11 FMC_LPC_LA05_P (PIN_AV11, 3C)-- ## H31 FMC_LPC_LA28_P (PIN_AY16, 3B)
set_location_assignment PIN_AW11 -to "dac_data_out[12](n)" ; ## D12 FMC_LPC_LA05_N (PIN_AW11, 3C)-- ## H32 FMC_LPC_LA28_N (PIN_AW16, 3B)
set_location_assignment PIN_BB17 -to dac_data_out[13] ; ## G33 FMC_LPC_LA31_P (PIN_BB17, 3C)
set_location_assignment PIN_BB18 -to "dac_data_out[13](n)" ; ## G34 FMC_LPC_LA31_N (PIN_BB18, 3C)
set_location_assignment PIN_BC18 -to dac_data_out[14] ; ## H34 FMC_LPC_LA30_P (PIN_BC18, 3C)
set_location_assignment PIN_BD18 -to "dac_data_out[14](n)" ; ## H35 FMC_LPC_LA30_N (PIN_BD18, 3C)
set_location_assignment PIN_AT10 -to dac_data_out[15] ; ## D08 FMC_LPC_LA01_CC_P (PIN_AT10, 3C, TERM_ON_BOARD)-- ## G36 FMC_LPC_LA33_P (PIN_AY17, 3B)
set_location_assignment PIN_AR11 -to "dac_data_out[15](n)" ; ## D09 FMC_LPC_LA01_CC_N (PIN_AR11, 3C, TERM_ON_BOARD)-- ## G37 FMC_LPC_LA33_N (PIN_AW17, 3B)
set_location_assignment PIN_AV15 -to adc_clk_in ; ## G06 FMC_LPC_LA00_CC_P (PIN_AV15, 3B, TERM_ON_BOARD)
set_location_assignment PIN_AU15 -to "adc_clk_in(n)" ; ## G07 FMC_LPC_LA00_CC_N (PIN_AU15, 3B, TERM_ON_BOARD)
set_location_assignment PIN_AR15 -to adc_data_in[0] ; ## C14 FMC_LPC_LA10_P (PIN_AR15, 3B)
set_location_assignment PIN_AT15 -to "adc_data_in[0](n)" ; ## C15 FMC_LPC_LA10_N (PIN_AT15, 3B)
set_location_assignment PIN_AW18 -to adc_data_in[1] ; ## C18 FMC_LPC_LA14_P (PIN_AW18, 3B)
set_location_assignment PIN_AV18 -to "adc_data_in[1](n)" ; ## C19 FMC_LPC_LA14_N (PIN_AV18, 3B)
set_location_assignment PIN_AR17 -to adc_data_in[2] ; ## D17 FMC_LPC_LA13_P (PIN_AR17, 3B)
set_location_assignment PIN_AP17 -to "adc_data_in[2](n)" ; ## D18 FMC_LPC_LA13_N (PIN_AP17, 3B)
set_location_assignment PIN_AT14 -to adc_data_in[3] ; ## H16 FMC_LPC_LA11_P (PIN_AT14, 3B)
set_location_assignment PIN_AR14 -to "adc_data_in[3](n)" ; ## H17 FMC_LPC_LA11_N (PIN_AR14, 3B)
set_location_assignment PIN_AR16 -to adc_data_in[4] ; ## G15 FMC_LPC_LA12_P (PIN_AR16, 3B)
set_location_assignment PIN_AP16 -to "adc_data_in[4](n)" ; ## G16 FMC_LPC_LA12_N (PIN_AP16, 3B)
set_location_assignment PIN_AP21 -to adc_data_in[5] ; ## C26 FMC_LPC_LA27_P (PIN_AP21, 3B)-- ## D14 FMC_LPC_LA09_P (PIN_AW13, 3C)
set_location_assignment PIN_AR21 -to "adc_data_in[5](n)" ; ## C27 FMC_LPC_LA27_N (PIN_AR21, 3B)-- ## D15 FMC_LPC_LA09_N (PIN_AV13, 3C)
set_location_assignment PIN_AT17 -to adc_data_in[6] ; ## H13 FMC_LPC_LA07_P (PIN_AT17, 3B)
set_location_assignment PIN_AU17 -to "adc_data_in[6](n)" ; ## H14 FMC_LPC_LA07_N (PIN_AU17, 3B)
set_location_assignment PIN_AP18 -to adc_data_in[7] ; ## G12 FMC_LPC_LA08_P (PIN_AP18, 3B)
set_location_assignment PIN_AN19 -to "adc_data_in[7](n)" ; ## G13 FMC_LPC_LA08_N (PIN_AN19, 3B)
set_location_assignment PIN_AY16 -to adc_data_in[8] ; ## H31 FMC_LPC_LA28_P (PIN_AY16, 3B)-- ## D11 FMC_LPC_LA05_P (PIN_AV11, 3C)
set_location_assignment PIN_AW16 -to "adc_data_in[8](n)" ; ## H32 FMC_LPC_LA28_N (PIN_AW16, 3B)-- ## D12 FMC_LPC_LA05_N (PIN_AW11, 3C)
set_location_assignment PIN_AN20 -to adc_data_in[9] ; ## H10 FMC_LPC_LA04_P (PIN_AN20, 3B)
set_location_assignment PIN_AP19 -to "adc_data_in[9](n)" ; ## H11 FMC_LPC_LA04_N (PIN_AP19, 3B)
set_location_assignment PIN_AR20 -to adc_data_in[10] ; ## G09 FMC_LPC_LA03_P (PIN_AR20, 3B)
set_location_assignment PIN_AR19 -to "adc_data_in[10](n)" ; ## G10 FMC_LPC_LA03_N (PIN_AR19, 3B)
set_location_assignment PIN_AV14 -to adc_data_in[11] ; ## C10 FMC_LPC_LA06_P (PIN_AV14, 3B)
set_location_assignment PIN_AW14 -to "adc_data_in[11](n)" ; ## C11 FMC_LPC_LA06_N (PIN_AW14, 3B)
set_location_assignment PIN_AR22 -to adc_data_in[12] ; ## H07 FMC_LPC_LA02_P (PIN_AR22, 3B)
set_location_assignment PIN_AT22 -to "adc_data_in[12](n)" ; ## H08 FMC_LPC_LA02_N (PIN_AT22, 3B)
set_location_assignment PIN_AY17 -to adc_data_in[13] ; ## G36 FMC_LPC_LA33_P (PIN_AY17, 3B)-- ## D08 FMC_LPC_LA01_CC_P (PIN_AT10, 3C, TERM_ON_BOARD)
set_location_assignment PIN_AW17 -to "adc_data_in[13](n)" ; ## G37 FMC_LPC_LA33_N (PIN_AW17, 3B)-- ## D09 FMC_LPC_LA01_CC_N (PIN_AR11, 3C, TERM_ON_BOARD)
set_instance_assignment -name IO_STANDARD LVDS -to dac_clk_in
set_instance_assignment -name IO_STANDARD LVDS -to dac_clk_out
set_instance_assignment -name IO_STANDARD LVDS -to dac_frame_out
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[0]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[1]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[2]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[3]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[4]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[5]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[6]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[7]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[8]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[9]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[10]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[11]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[12]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[13]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[14]
set_instance_assignment -name IO_STANDARD LVDS -to dac_data_out[15]
set_instance_assignment -name IO_STANDARD LVDS -to adc_clk_in
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[0]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[1]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[2]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[3]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[4]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[5]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[6]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[7]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[8]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[9]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[10]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[11]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[12]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[13]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[14]
set_instance_assignment -name IO_STANDARD LVDS -to adc_data_in[15]
# SPI interface
set_location_assignment PIN_AY19 -to spi_csn ; ## H05 FMC_LPC_CLK0_M2C_N
set_location_assignment PIN_AY20 -to spi_clk ; ## H04 FMC_LPC_CLK0_M2C_P
set_location_assignment PIN_AT13 -to spi_sdio ; ## G18 FMC_LPC_LA16_P
set_location_assignment PIN_AU13 -to spi_int ; ## G19 FMC_LPC_LA16_N
set_instance_assignment -name IO_STANDARD "1.8V" -to spi_csn
set_instance_assignment -name IO_STANDARD "1.8V" -to spi_clk
set_instance_assignment -name IO_STANDARD "1.8V" -to spi_sdio
set_instance_assignment -name IO_STANDARD "1.8V" -to spi_int
execute_flow -compile

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projects/daq1/a10gx/system_qsys.tcl
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source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
source ../common/daq1_qsys.tcl

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projects/daq1/a10gx/system_top.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// Each core or library found in this collection may have its own licensing terms.
// The user should keep this in in mind while exploring these cores.
//
// Redistribution and use in source and binary forms,
// with or without modification of this file, are permitted under the terms of either
// (at the option of the user):
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory, or at:
// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
//
// OR
//
// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
// clock and resets
input sys_clk,
input sys_resetn,
// ddr3
output ddr3_clk_p,
output ddr3_clk_n,
output [ 14:0] ddr3_a,
output [ 2:0] ddr3_ba,
output ddr3_cke,
output ddr3_cs_n,
output ddr3_odt,
output ddr3_reset_n,
output ddr3_we_n,
output ddr3_ras_n,
output ddr3_cas_n,
inout [ 7:0] ddr3_dqs_p,
inout [ 7:0] ddr3_dqs_n,
inout [ 63:0] ddr3_dq,
output [ 7:0] ddr3_dm,
input ddr3_rzq,
input ddr3_ref_clk,
// ethernet
input eth_ref_clk,
input eth_rxd,
output eth_txd,
output eth_mdc,
inout eth_mdio,
output eth_resetn,
input eth_intn,
// board gpio
input [ 10:0] gpio_bd_i,
output [ 15:0] gpio_bd_o,
// daq1 interface
input dac_clk_in,
output dac_clk_out,
output dac_frame_out,
output [15:0] dac_data_out,
input adc_clk_in,
input [13:0] adc_data_in,
output spi_clk,
output spi_csn,
inout spi_sdio,
input spi_int);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire spi_mosi;
wire spi_miso;
// board specific connections
assign eth_resetn = ~eth_reset;
assign eth_mdio_i = eth_mdio;
assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o;
assign ddr3_a[14:12] = 3'd0;
assign gpio_i[31:27] = gpio_o[31:27];
assign gpio_i[26:16] = gpio_bd_i;
assign gpio_i[15: 0] = gpio_o[15:0];
assign gpio_bd_o = gpio_o[15:0];
// instantiations
daq1_spi i_spi (
.spi_csn (spi_csn),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_sdio (spi_sdio));
system_bd i_system_bd (
.sys_clk_clk (sys_clk),
.sys_rst_reset_n (sys_resetn),
.sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
.sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
.sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]),
.sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
.sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
.sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
.sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
.sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
.sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
.sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
.sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
.sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
.sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
.sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
.sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
.sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
.sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
.sys_ethernet_mdio_mdc (eth_mdc),
.sys_ethernet_mdio_mdio_in (eth_mdio_i),
.sys_ethernet_mdio_mdio_out (eth_mdio_o),
.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
.sys_ethernet_ref_clk_clk (eth_ref_clk),
.sys_ethernet_reset_reset (eth_reset),
.sys_ethernet_sgmii_rxp_0 (eth_rxd),
.sys_ethernet_sgmii_txp_0 (eth_txd),
.sys_gpio_bd_in_port (gpio_i[31:0]),
.sys_gpio_bd_out_port (gpio_o[31:0]),
.sys_gpio_in_export (gpio_i[63:32]),
.sys_gpio_out_export (gpio_o[63:32]),
.sys_spi_MISO (spi_miso),
.sys_spi_MOSI (spi_mosi),
.sys_spi_SCLK (spi_clk),
.sys_spi_SS_n (spi_csn),
.spi_int_irq(spi_int),
.axi_ad9684_device_if_adc_clk_in_n (1'd0),
.axi_ad9684_device_if_adc_clk_in_p (adc_clk_in),
.axi_ad9684_device_if_adc_data_in_n (14'd0),
.axi_ad9684_device_if_adc_data_in_p (adc_data_in),
.axi_ad9122_device_if_dac_clk_in_n (1'd0),
.axi_ad9122_device_if_dac_clk_in_p (dac_clk_in),
.axi_ad9122_device_if_dac_clk_out_n (),
.axi_ad9122_device_if_dac_clk_out_p (dac_clk_out),
.axi_ad9122_device_if_dac_data_out_n (),
.axi_ad9122_device_if_dac_data_out_p (dac_data_out),
.axi_ad9122_device_if_dac_frame_out_n (),
.axi_ad9122_device_if_dac_frame_out_p (dac_frame_out)
);
endmodule
// ***************************************************************************
// ***************************************************************************