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spi_engine_offload: Add a CDC module for trigger reception 

There are devices which have a asynchronous data ready signal. (asynchronous
with the spi clock) The CDC stages can be enabled by setting up
the ASYNC_TRIG parameter.
main
Istvan Csomortani 2017-04-28 12:11:09 +03:00
parent 07956cfe66
commit 3ba57582bb
1 changed files with 13 additions and 1 deletions
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14
library/spi_engine/spi_engine_offload/spi_engine_offload.v
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@ -2,6 +2,7 @@
module spi_engine_offload #( module spi_engine_offload #(
parameter ASYNC_SPI_CLK = 0, parameter ASYNC_SPI_CLK = 0,
parameter ASYNC_TRIG = 0,
parameter CMD_MEM_ADDRESS_WIDTH = 4, parameter CMD_MEM_ADDRESS_WIDTH = 4,
parameter SDO_MEM_ADDRESS_WIDTH = 4, parameter SDO_MEM_ADDRESS_WIDTH = 4,
parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32 parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32
@ -125,12 +126,23 @@ end endgenerate
assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1; assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1;
wire trigger_s;
sync_bits #(
.NUM_OF_BITS(1),
.ASYNC_CLK(ASYNC_TRIG)
) i_sync_trigger (
.in(trigger),
.out_clk(spi_clk),
.out_resetn(1'b1),
.out(trigger_s)
);
always @(posedge spi_clk) begin always @(posedge spi_clk) begin
if (spi_resetn == 1'b0) begin if (spi_resetn == 1'b0) begin
spi_active <= 1'b0; spi_active <= 1'b0;
end else begin end else begin
if (spi_active == 1'b0) begin if (spi_active == 1'b0) begin
if (trigger == 1'b1 && spi_enable == 1'b1) if (trigger_s == 1'b1 && spi_enable == 1'b1)
spi_active <= 1'b1; spi_active <= 1'b1;
end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin
spi_active <= 1'b0; spi_active <= 1'b0;