diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution.v b/library/spi_engine/spi_engine_execution/spi_engine_execution.v
index e6a2ce130..734421023 100644
--- a/library/spi_engine/spi_engine_execution/spi_engine_execution.v
+++ b/library/spi_engine/spi_engine_execution/spi_engine_execution.v
@@ -157,6 +157,8 @@ reg [(DATA_WIDTH-1):0] data_sdi_shift_5 = 'h0;
 reg [(DATA_WIDTH-1):0] data_sdi_shift_6 = 'h0;
 reg [(DATA_WIDTH-1):0] data_sdi_shift_7 = 'h0;
 
+reg [4:0] trigger_rx_d = 5'b0;
+
 wire [1:0] inst = cmd[13:12];
 wire [1:0] inst_d1 = cmd_d1[13:12];
 
@@ -168,6 +170,19 @@ wire exec_chipselect_cmd = exec_cmd && inst == CMD_CHIPSELECT;
 wire exec_misc_cmd = exec_cmd && inst == CMD_MISC;
 wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC;
 
+wire trigger_tx;
+wire trigger_rx;
+
+wire sleep_counter_compare;
+wire cs_sleep_counter_compare;
+wire cs_sleep_counter_compare2;
+
+wire io_ready1;
+wire io_ready2;
+wire trigger_rx_s;
+
+wire last_sdi_bit;
+
 assign cmd_ready = idle;
 
 always @(posedge clk) begin
@@ -229,12 +244,12 @@ always @(posedge clk) begin
   end
 end
 
-wire trigger_tx = trigger == 1'b1 && ntx_rx == 1'b0;
-wire trigger_rx = trigger == 1'b1 && ntx_rx == 1'b1;
+assign trigger_tx = trigger == 1'b1 && ntx_rx == 1'b0;
+assign trigger_rx = trigger == 1'b1 && ntx_rx == 1'b1;
 
-wire sleep_counter_compare = sleep_counter == cmd_d1[7:0] && clk_div_last == 1'b1;
-wire cs_sleep_counter_compare = cs_sleep_counter == cmd_d1[9:8] && clk_div_last == 1'b1;
-wire cs_sleep_counter_compare2 = cs_sleep_counter2 == {cmd_d1[9:8],1'b1} && clk_div_last == 1'b1;
+assign sleep_counter_compare = sleep_counter == cmd_d1[7:0] && clk_div_last == 1'b1;
+assign cs_sleep_counter_compare = cs_sleep_counter == cmd_d1[9:8] && clk_div_last == 1'b1;
+assign cs_sleep_counter_compare2 = cs_sleep_counter2 == {cmd_d1[9:8],1'b1} && clk_div_last == 1'b1;
 
 always @(posedge clk) begin
   if (idle == 1'b1) begin
@@ -321,9 +336,9 @@ always @(posedge clk) begin
     sdi_data_valid <= 1'b0;
 end
 
-wire io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) &&
+assign io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) &&
         (sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
-wire io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) &&
+assign io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) &&
         (sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
 
 always @(posedge clk) begin
@@ -390,16 +405,15 @@ assign sdo_int_s = data_sdo_shift[DATA_WIDTH-1];
 // be set to 0, to reduce the core clock's speed, this delay will mean that SDI will
 // be latched at one of the next consecutive SCLK edge.
 
-reg [4:0] trigger_rx_d = 5'b0;
 always @(posedge clk) begin
   trigger_rx_d[0] <= trigger_rx;
   trigger_rx_d[4:1] <= trigger_rx_d[3:0];
 end
 
-wire trigger_rx_s = (SDI_DELAY == 2'b00) ? trigger_rx_d[1] :
-                    (SDI_DELAY == 2'b01) ? trigger_rx_d[2] :
-                    (SDI_DELAY == 2'b10) ? trigger_rx_d[3] :
-                    (SDI_DELAY == 2'b11) ? trigger_rx_d[4] : trigger_rx_d[1];
+assign trigger_rx_s = (SDI_DELAY == 2'b00) ? trigger_rx_d[1] :
+                      (SDI_DELAY == 2'b01) ? trigger_rx_d[2] :
+                      (SDI_DELAY == 2'b10) ? trigger_rx_d[3] :
+                      (SDI_DELAY == 2'b11) ? trigger_rx_d[4] : trigger_rx_d[1];
 
 always @(posedge clk) begin
   if (inst_d1 == CMD_CHIPSELECT) begin
@@ -444,7 +458,7 @@ assign sdi_data = (NUM_OF_SDI == 1) ? data_sdi_shift :
                                        data_sdi_shift_3, data_sdi_shift_2,
                                        data_sdi_shift_1, data_sdi_shift} : data_sdi_shift;
 
-wire last_sdi_bit = (sdi_counter == word_length-1);
+assign last_sdi_bit = (sdi_counter == word_length-1);
 always @(posedge clk) begin
   if (resetn == 1'b0) begin
     sdi_counter <= 8'b0;