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util_adxcvr- rx/tx clocks

main
Rejeesh Kutty 2016-10-05 13:53:02 -04:00
parent 7ec93ce8e0
commit 39fdf11ef3
1 changed files with 44 additions and 22 deletions
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66
library/xilinx/util_adxcvr/util_adxcvr_xch.v
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@ -301,28 +301,6 @@ module util_adxcvr_xch #(
end
endgenerate
generate
if (XCVR_TYPE == 1) begin
BUFG_GT i_rx_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (rx_out_clk_s),
.O (rx_out_clk));
BUFG_GT i_tx_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (tx_out_clk_s),
.O (tx_out_clk));
end
endgenerate
generate
if (XCVR_TYPE == 0) begin
assign rx_sys_clk_sel_s = up_rx_sys_clk_sel;
@ -768,6 +746,28 @@ module util_adxcvr_xch #(
end
endgenerate
generate
if (XCVR_TYPE == 1) begin
BUFG_GT i_rx_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (rx_out_clk_s),
.O (rx_out_clk));
BUFG_GT i_tx_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (tx_out_clk_s),
.O (tx_out_clk));
end
endgenerate
generate
if (XCVR_TYPE == 1) begin
assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;
@ -1500,6 +1500,28 @@ module util_adxcvr_xch #(
end
endgenerate
generate
if (XCVR_TYPE == 2) begin
BUFG_GT i_rx_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (rx_out_clk_s),
.O (rx_out_clk));
BUFG_GT i_tx_bufg (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (1'b0),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (tx_out_clk_s),
.O (tx_out_clk));
end
endgenerate
generate
if (XCVR_TYPE == 2) begin
assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel == 2'd3) ? 2'b10 : 2'b00;