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adrv9371x: Use the output of IBUFDS_GTE2 as reference for the clock gens 

In some cases (GTX2) the transceiver may gate the out_clk when it is in
reset. This will stop the clock generators from getting a clock prior
removing the reset of the XCVR.  The XCVR has a requirement of running
user clock while removing the reset. The correct sequence must be :

Enable device clocks (user clock)
Remove the reset from the XCVR
main
Laszlo Nagy 2022-02-10 13:13:57 +00:00 committed by Laszlo Nagy
parent 86d754ae85
commit 39e073e6bf
1 changed files with 5 additions and 3 deletions
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8
projects/adrv9371x/common/adrv9371x_bd.tcl
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@ -45,6 +45,8 @@ source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl
# ad9371
create_bd_port -dir I ref_clk
create_bd_port -dir I dac_fifo_bypass
create_bd_port -dir I adc_fir_filter_active
create_bd_port -dir I dac_fir_filter_active
@ -220,14 +222,14 @@ ad_connect $sys_cpu_clk util_ad9371_xcvr/up_clk
# Tx
ad_connect ad9371_tx_device_clk axi_ad9371_tx_clkgen/clk_0
ad_xcvrcon util_ad9371_xcvr axi_ad9371_tx_xcvr axi_ad9371_tx_jesd {1 2 3 0} ad9371_tx_device_clk {} $MAX_TX_NUM_OF_LANES
ad_connect util_ad9371_xcvr/tx_out_clk_0 axi_ad9371_tx_clkgen/clk
ad_connect ref_clk axi_ad9371_tx_clkgen/clk
ad_xcvrpll $tx_ref_clk util_ad9371_xcvr/qpll_ref_clk_0
ad_xcvrpll axi_ad9371_tx_xcvr/up_pll_rst util_ad9371_xcvr/up_qpll_rst_0
# Rx
ad_connect ad9371_rx_device_clk axi_ad9371_rx_clkgen/clk_0
ad_xcvrcon util_ad9371_xcvr axi_ad9371_rx_xcvr axi_ad9371_rx_jesd {} ad9371_rx_device_clk {} $MAX_RX_NUM_OF_LANES
ad_connect util_ad9371_xcvr/rx_out_clk_0 axi_ad9371_rx_clkgen/clk
ad_connect ref_clk axi_ad9371_rx_clkgen/clk
for {set i 0} {$i < $MAX_RX_NUM_OF_LANES} {incr i} {
set ch [expr $i]
ad_xcvrpll $rx_ref_clk util_ad9371_xcvr/cpll_ref_clk_$ch
@ -237,7 +239,7 @@ for {set i 0} {$i < $MAX_RX_NUM_OF_LANES} {incr i} {
# Rx - OBS
ad_connect ad9371_rx_os_device_clk axi_ad9371_rx_os_clkgen/clk_0
ad_xcvrcon util_ad9371_xcvr axi_ad9371_rx_os_xcvr axi_ad9371_rx_os_jesd {} ad9371_rx_os_device_clk {} $MAX_RX_OS_NUM_OF_LANES
ad_connect util_ad9371_xcvr/rx_out_clk_$MAX_RX_NUM_OF_LANES axi_ad9371_rx_os_clkgen/clk
ad_connect ref_clk axi_ad9371_rx_os_clkgen/clk
for {set i 0} {$i < $MAX_RX_OS_NUM_OF_LANES} {incr i} {
# channel indexing starts from the last RX
set ch [expr $MAX_RX_NUM_OF_LANES + $i]