zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

util_adxcvr: Add additional parameters allowing for GTH4 RX 15Gbps rates

main
Adrian Costina 2019-06-21 10:17:03 +01:00
parent eab1e86544
commit 39d19ef401
2 changed files with 211 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

187
library/xilinx/util_adxcvr/util_adxcvr.v
View File

@ -70,6 +70,10 @@ module util_adxcvr #(
parameter [15:0] CPLL_CFG1 = 16'b0000000000100011,
parameter [15:0] CPLL_CFG2 = 16'b0000000000000010,
parameter [15:0] CPLL_CFG3 = 16'b0000000000000000,
parameter [15:0] GTH4_CH_HSPMUX = 16'b0010010000100100,
parameter integer GTH4_PREIQ_FREQ_BST = 0,
parameter [15:0] GTH4_RXPI_CFG0 = 16'b0000000000000010,
parameter [15:0] GTH4_RXPI_CFG1 = 16'b0000000000010101,
parameter [15:0] GTY4_CH_HSPMUX = 16'b0010000000100000,
parameter integer GTY4_PREIQ_FREQ_BST = 0,
parameter [2:0] GTY4_RTX_BUF_CML_CTRL = 3'b011,
@ -93,6 +97,13 @@ module util_adxcvr #(
parameter [15:0] RX_DFE_LPM_CFG = 16'h0104,
parameter [31:0] RX_PMA_CFG = 32'h001e7080,
parameter [72:0] RX_CDR_CFG = 72'h0b000023ff10400020,
parameter [15:0] RXCDR_CFG0 = 16'b0000000000000010,
parameter [ 9:0] RXCDR_CFG2_GEN2 = 10'b1001100101,
parameter [15:0] RXCDR_CFG2_GEN4 = 16'b0000000010110100,
parameter [15:0] RXCDR_CFG3 = 16'b0000000000010010,
parameter [ 5:0] RXCDR_CFG3_GEN2 = 6'b011010,
parameter [15:0] RXCDR_CFG3_GEN3 = 16'b0000000000010010,
parameter [15:0] RXCDR_CFG3_GEN4 = 16'b0000000000100100,
parameter integer RX_LANE_INVERT = 0) (
input up_rstn,
@ -1202,6 +1213,17 @@ module util_adxcvr #(
.RX_PMA_CFG (RX_PMA_CFG),
.RX_CDR_CFG (RX_CDR_CFG),
.RX_POLARITY ((RX_LANE_INVERT >> 0) & 1),
.RXCDR_CFG0 (RXCDR_CFG0),
.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2),
.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4),
.RXCDR_CFG3 (RXCDR_CFG3),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
@ -1315,6 +1337,17 @@ module util_adxcvr #(
.RX_PMA_CFG (RX_PMA_CFG),
.RX_CDR_CFG (RX_CDR_CFG),
.RX_POLARITY ((RX_LANE_INVERT >> 1) & 1),
.RXCDR_CFG0 (RXCDR_CFG0),
.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2),
.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4),
.RXCDR_CFG3 (RXCDR_CFG3),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
@ -1428,6 +1461,17 @@ module util_adxcvr #(
.RX_PMA_CFG (RX_PMA_CFG),
.RX_CDR_CFG (RX_CDR_CFG),
.RX_POLARITY ((RX_LANE_INVERT >> 2) & 1),
.RXCDR_CFG0 (RXCDR_CFG0),
.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2),
.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4),
.RXCDR_CFG3 (RXCDR_CFG3),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
@ -1541,6 +1585,17 @@ module util_adxcvr #(
.RX_PMA_CFG (RX_PMA_CFG),
.RX_CDR_CFG (RX_CDR_CFG),
.RX_POLARITY ((RX_LANE_INVERT >> 3) & 1),
.RXCDR_CFG0 (RXCDR_CFG0),
.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2),
.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4),
.RXCDR_CFG3 (RXCDR_CFG3),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
@ -1704,6 +1759,17 @@ module util_adxcvr #(
.RX_PMA_CFG (RX_PMA_CFG),
.RX_CDR_CFG (RX_CDR_CFG),
.RX_POLARITY ((RX_LANE_INVERT >> 4) & 1),
.RXCDR_CFG0 (RXCDR_CFG0),
.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2),
.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4),
.RXCDR_CFG3 (RXCDR_CFG3),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
@ -1817,6 +1883,17 @@ module util_adxcvr #(
.RX_PMA_CFG (RX_PMA_CFG),
.RX_CDR_CFG (RX_CDR_CFG),
.RX_POLARITY ((RX_LANE_INVERT >> 5) & 1),
.RXCDR_CFG0 (RXCDR_CFG0),
.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2),
.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4),
.RXCDR_CFG3 (RXCDR_CFG3),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
@ -1930,6 +2007,17 @@ module util_adxcvr #(
.RX_PMA_CFG (RX_PMA_CFG),
.RX_CDR_CFG (RX_CDR_CFG),
.RX_POLARITY ((RX_LANE_INVERT >> 6) & 1),
.RXCDR_CFG0 (RXCDR_CFG0),
.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2),
.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4),
.RXCDR_CFG3 (RXCDR_CFG3),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
@ -2043,6 +2131,17 @@ module util_adxcvr #(
.RX_PMA_CFG (RX_PMA_CFG),
.RX_CDR_CFG (RX_CDR_CFG),
.RX_POLARITY ((RX_LANE_INVERT >> 7) & 1),
.RXCDR_CFG0 (RXCDR_CFG0),
.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2),
.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4),
.RXCDR_CFG3 (RXCDR_CFG3),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
@ -2206,6 +2305,17 @@ module util_adxcvr #(
.RX_PMA_CFG (RX_PMA_CFG),
.RX_CDR_CFG (RX_CDR_CFG),
.RX_POLARITY ((RX_LANE_INVERT >> 8) & 1),
.RXCDR_CFG0 (RXCDR_CFG0),
.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2),
.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4),
.RXCDR_CFG3 (RXCDR_CFG3),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
@ -2319,6 +2429,17 @@ module util_adxcvr #(
.RX_PMA_CFG (RX_PMA_CFG),
.RX_CDR_CFG (RX_CDR_CFG),
.RX_POLARITY ((RX_LANE_INVERT >> 9) & 1),
.RXCDR_CFG0 (RXCDR_CFG0),
.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2),
.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4),
.RXCDR_CFG3 (RXCDR_CFG3),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
@ -2432,6 +2553,17 @@ module util_adxcvr #(
.RX_PMA_CFG (RX_PMA_CFG),
.RX_CDR_CFG (RX_CDR_CFG),
.RX_POLARITY ((RX_LANE_INVERT >> 10) & 1),
.RXCDR_CFG0 (RXCDR_CFG0),
.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2),
.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4),
.RXCDR_CFG3 (RXCDR_CFG3),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
@ -2545,6 +2677,17 @@ module util_adxcvr #(
.RX_PMA_CFG (RX_PMA_CFG),
.RX_CDR_CFG (RX_CDR_CFG),
.RX_POLARITY ((RX_LANE_INVERT >> 11) & 1),
.RXCDR_CFG0 (RXCDR_CFG0),
.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2),
.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4),
.RXCDR_CFG3 (RXCDR_CFG3),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
@ -2708,6 +2851,17 @@ module util_adxcvr #(
.RX_PMA_CFG (RX_PMA_CFG),
.RX_CDR_CFG (RX_CDR_CFG),
.RX_POLARITY ((RX_LANE_INVERT >> 12) & 1),
.RXCDR_CFG0 (RXCDR_CFG0),
.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2),
.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4),
.RXCDR_CFG3 (RXCDR_CFG3),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
@ -2821,6 +2975,17 @@ module util_adxcvr #(
.RX_PMA_CFG (RX_PMA_CFG),
.RX_CDR_CFG (RX_CDR_CFG),
.RX_POLARITY ((RX_LANE_INVERT >> 13) & 1),
.RXCDR_CFG0 (RXCDR_CFG0),
.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2),
.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4),
.RXCDR_CFG3 (RXCDR_CFG3),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
@ -2934,6 +3099,17 @@ module util_adxcvr #(
.RX_PMA_CFG (RX_PMA_CFG),
.RX_CDR_CFG (RX_CDR_CFG),
.RX_POLARITY ((RX_LANE_INVERT >> 14) & 1),
.RXCDR_CFG0 (RXCDR_CFG0),
.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2),
.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4),
.RXCDR_CFG3 (RXCDR_CFG3),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),
@ -3047,6 +3223,17 @@ module util_adxcvr #(
.RX_PMA_CFG (RX_PMA_CFG),
.RX_CDR_CFG (RX_CDR_CFG),
.RX_POLARITY ((RX_LANE_INVERT >> 15) & 1),
.RXCDR_CFG0 (RXCDR_CFG0),
.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2),
.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4),
.RXCDR_CFG3 (RXCDR_CFG3),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.GTH4_CH_HSPMUX (GTH4_CH_HSPMUX),
.GTH4_PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.GTH4_RXPI_CFG0 (GTH4_RXPI_CFG0),
.GTH4_RXPI_CFG1 (GTH4_RXPI_CFG1),
.GTY4_CH_HSPMUX (GTY4_CH_HSPMUX),
.GTY4_PREIQ_FREQ_BST (GTY4_PREIQ_FREQ_BST),
.GTY4_RTX_BUF_CML_CTRL (GTY4_RTX_BUF_CML_CTRL),

34
library/xilinx/util_adxcvr/util_adxcvr_xch.v
View File

@ -48,6 +48,11 @@ module util_adxcvr_xch #(
parameter [15:0] CPLL_CFG2 = 16'b0000000000000010,
parameter [15:0] CPLL_CFG3 = 16'b0000000000000000,
parameter [15:0] GTH4_CH_HSPMUX = 16'b0010010000100100,
parameter integer GTH4_PREIQ_FREQ_BST = 0,
parameter [15:0] GTH4_RXPI_CFG0 = 16'b0000000000000010,
parameter [15:0] GTH4_RXPI_CFG1 = 16'b0000000000010101,
parameter [15:0] GTY4_CH_HSPMUX = 16'b0010000000100000,
parameter integer GTY4_PREIQ_FREQ_BST = 0,
parameter [2:0] GTY4_RTX_BUF_CML_CTRL = 3'b011,
@ -65,6 +70,13 @@ module util_adxcvr_xch #(
parameter [15:0] RX_DFE_LPM_CFG = 16'h0104,
parameter [31:0] RX_PMA_CFG = 32'h001e7080,
parameter [72:0] RX_CDR_CFG = 72'h0b000023ff10400020,
parameter [15:0] RXCDR_CFG0 = 16'b0000000000000010,
parameter [ 9:0] RXCDR_CFG2_GEN2 = 10'b1001100101,
parameter [15:0] RXCDR_CFG2_GEN4 = 16'b0000000010110100,
parameter [15:0] RXCDR_CFG3 = 16'b0000000000010010,
parameter [ 5:0] RXCDR_CFG3_GEN2 = 6'b011010,
parameter [15:0] RXCDR_CFG3_GEN3 = 16'b0000000000010010,
parameter [15:0] RXCDR_CFG3_GEN4 = 16'b0000000000100100,
parameter integer RX_POLARITY = 0) (
// pll interface
@ -1588,7 +1600,7 @@ module util_adxcvr_xch #(
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_USE ("FALSE"),
.CHAN_BOND_SEQ_LEN (1),
.CH_HSPMUX (16'b0010010000100100),
.CH_HSPMUX (GTH4_CH_HSPMUX),
.CKCAL1_CFG_0 (16'b1100000011000000),
.CKCAL1_CFG_1 (16'b0101000011000000),
.CKCAL1_CFG_2 (16'b0000000000001010),
@ -1716,7 +1728,7 @@ module util_adxcvr_xch #(
.PD_TRANS_TIME_FROM_P2 (12'b000000111100),
.PD_TRANS_TIME_NONE_P2 (8'b00011001),
.PD_TRANS_TIME_TO_P2 (8'b01100100),
.PREIQ_FREQ_BST (0),
.PREIQ_FREQ_BST (GTH4_PREIQ_FREQ_BST),
.PROCESS_PAR (3'b010),
.RATE_SW_USE_DRP (1'b1),
.RCLK_SIPO_DLY_ENB (1'b0),
@ -1738,16 +1750,18 @@ module util_adxcvr_xch #(
.RXBUF_THRESH_UNDFLW (3),
.RXCDRFREQRESET_TIME (5'b00001),
.RXCDRPHRESET_TIME (5'b00001),
.RXCDR_CFG0 (16'b0000000000000010),
.RXCDR_CFG0 (RXCDR_CFG0),
.RXCDR_CFG0_GEN3 (16'b0000000000000011),
.RXCDR_CFG1 (16'b0000000000000000),
.RXCDR_CFG1_GEN3 (16'b0000000000000000),
.RXCDR_CFG2 (16'b0000001001100101),
.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2),
.RXCDR_CFG2_GEN3 (16'b0000001001100101),
.RXCDR_CFG2_GEN4 (16'b0000000010110100),
.RXCDR_CFG3 (16'b0000000000010010),
.RXCDR_CFG3_GEN3 (16'b0000000000010010),
.RXCDR_CFG3_GEN4 (16'b0000000000100100),
.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4),
.RXCDR_CFG3 (RXCDR_CFG3),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4),
.RXCDR_CFG4 (16'b0101110011110110),
.RXCDR_CFG4_GEN3 (16'b0101110011110110),
.RXCDR_CFG5 (16'b1011010001101011),
@ -1813,7 +1827,7 @@ module util_adxcvr_xch #(
.RXDFE_KH_CFG3 (16'b0100000100011100),
.RXDFE_OS_CFG0 (16'b0000000000000000),
.RXDFE_OS_CFG1 (16'b1000000000000010),
.RXDFE_PWR_SAVING (1'b1),
.RXDFE_PWR_SAVING (1'b0),
.RXDFE_UT_CFG0 (16'b0000000000000000),
.RXDFE_UT_CFG1 (16'b0000000000000011),
.RXDFE_UT_CFG2 (16'b0000000000000000),
@ -1842,8 +1856,8 @@ module util_adxcvr_xch #(
.RXPHSLIP_CFG (16'b1001100100110011),
.RXPH_MONITOR_SEL (5'b00000),
.RXPI_AUTO_BW_SEL_BYPASS (1'b0),
.RXPI_CFG0 (16'b0000000000000010),
.RXPI_CFG1 (16'b0000000000010101),
.RXPI_CFG0 (GTH4_RXPI_CFG0),
.RXPI_CFG1 (GTH4_RXPI_CFG1),
.RXPI_LPM (1'b0),
.RXPI_SEL_LC (2'b00),
.RXPI_STARTCODE (2'b00),