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adrv9371x/zc706: Add PL_DDR FIFO to the design

main
Istvan Csomortani 2016-05-17 10:05:52 +03:00
parent 3b6a36e3e2
commit 3859cba186
4 changed files with 96 additions and 17 deletions
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30
projects/adrv9371x/common/adrv9371x_bd.tcl
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@ -37,7 +37,6 @@ set axi_ad9371_tx_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.
set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9371_tx_dma
@ -46,8 +45,6 @@ set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9371_tx_dma
p_sys_dacfifo [current_bd_instance .] axi_ad9371_tx_fifo 128 17
set util_ad9371_tx_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9371_tx_upack]
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_ad9371_tx_upack
set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9371_tx_upack
@ -253,19 +250,21 @@ ad_connect axi_ad9371_core/dac_data_i1 util_ad9371_tx_upack/dac_data_2
ad_connect axi_ad9371_core/dac_valid_q1 util_ad9371_tx_upack/dac_valid_3
ad_connect axi_ad9371_core/dac_enable_q1 util_ad9371_tx_upack/dac_enable_3
ad_connect axi_ad9371_core/dac_data_q1 util_ad9371_tx_upack/dac_data_3
ad_connect util_ad9371_tx_upack/dma_xfer_in axi_ad9371_tx_fifo/dac_xfer_out
ad_connect axi_tx_clkgen/clk_0 axi_ad9371_tx_fifo/dac_clk
ad_connect util_ad9371_tx_upack/dac_valid axi_ad9371_tx_fifo/dac_valid
ad_connect util_ad9371_tx_upack/dac_data axi_ad9371_tx_fifo/dac_data
ad_connect axi_tx_clkgen/clk_0 axi_ad9371_tx_fifo/dma_clk
ad_connect util_ad9371_gt/tx_rst axi_ad9371_tx_fifo/dma_rst
ad_connect axi_tx_clkgen/clk_0 axi_ad9371_tx_dma/m_axis_aclk
ad_connect sys_dma_resetn axi_ad9371_tx_dma/m_src_axi_aresetn
ad_connect axi_ad9371_tx_fifo/dma_xfer_req axi_ad9371_tx_dma/m_axis_xfer_req
ad_connect axi_ad9371_tx_fifo/dma_ready axi_ad9371_tx_dma/m_axis_ready
ad_connect axi_ad9371_tx_fifo/dma_data axi_ad9371_tx_dma/m_axis_data
ad_connect axi_ad9371_tx_fifo/dma_valid axi_ad9371_tx_dma/m_axis_valid
ad_connect axi_ad9371_tx_fifo/dma_xfer_last axi_ad9371_tx_dma/m_axis_last
ad_connect util_ad9371_gt/tx_rst axi_ad9371_dacfifo/dac_rst
ad_connect util_ad9371_tx_upack/dma_xfer_in axi_ad9371_dacfifo/dac_xfer_out
ad_connect axi_tx_clkgen/clk_0 axi_ad9371_dacfifo/dac_clk
ad_connect util_ad9371_tx_upack/dac_valid axi_ad9371_dacfifo/dac_valid
ad_connect util_ad9371_tx_upack/dac_data axi_ad9371_dacfifo/dac_data
ad_connect axi_tx_clkgen/clk_0 axi_ad9371_dacfifo/dma_clk
ad_connect axi_ad9371_dacfifo/dma_xfer_req axi_ad9371_tx_dma/m_axis_xfer_req
ad_connect axi_ad9371_dacfifo/dma_rready axi_ad9371_tx_dma/m_axis_ready
ad_connect axi_ad9371_dacfifo/dma_rdata axi_ad9371_tx_dma/m_axis_data
ad_connect axi_ad9371_dacfifo/dma_rvalid axi_ad9371_tx_dma/m_axis_valid
ad_connect axi_ad9371_dacfifo/dma_xfer_last axi_ad9371_tx_dma/m_axis_last
# connections (adc)
@ -333,7 +332,8 @@ ad_connect util_ad9371_rx_os_cpack/adc_valid axi_ad9371_rx_os_dma/fifo_wr_en
ad_connect util_ad9371_rx_os_cpack/adc_sync axi_ad9371_rx_os_dma/fifo_wr_sync
ad_connect util_ad9371_rx_os_cpack/adc_data axi_ad9371_rx_os_dma/fifo_wr_din
ad_connect axi_ad9371_rx_os_dma/fifo_wr_overflow axi_ad9371_core/adc_os_dovf
ad_connect axi_ad9371_tx_fifo/dac_fifo_bypass dac_fifo_bypass
#ad_connect axi_ad9371_tx_fifo/dac_fifo_bypass dac_fifo_bypass
# interconnect (cpu)

19
projects/adrv9371x/zc706/system_bd.tcl
View File

@ -1,5 +1,24 @@
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
p_plddr3_dacfifo [current_bd_instance .] axi_ad9371_dacfifo 128 128
create_bd_port -dir I -type rst sys_rst
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
ad_connect sys_rst axi_ad9371_dacfifo/sys_rst
ad_connect sys_clk axi_ad9371_dacfifo/sys_clk
ad_connect ddr3 axi_ad9371_dacfifo/ddr3
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
[get_bd_addr_spaces axi_ad9371_dacfifo/axi_dacfifo/axi] \
[get_bd_addr_segs axi_ad9371_dacfifo/axi_ddr_cntrl/memmap/memaddr] \
SEG_axi_ddr_cntrl_memaddr
source ../common/adrv9371x_bd.tcl

1
projects/adrv9371x/zc706/system_project.tcl
View File

@ -10,6 +10,7 @@ adi_project_files adrv9371x_zc706 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc]

63
projects/adrv9371x/zc706/system_top.v
View File

@ -126,7 +126,27 @@ module system_top (
ad9371_gpio_13,
ad9371_gpio_17,
ad9371_gpio_16,
ad9371_gpio_18);
ad9371_gpio_18,
sys_rst,
sys_clk_p,
sys_clk_n,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
ddr3_ras_n,
ddr3_reset_n,
ddr3_we_n);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
@ -217,6 +237,27 @@ module system_top (
inout ad9371_gpio_16;
inout ad9371_gpio_18;
input sys_rst;
input sys_clk_p;
input sys_clk_n;
output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output ddr3_ras_n;
output ddr3_reset_n;
output ddr3_we_n;
// internal signals
wire [63:0] gpio_i;
@ -381,7 +422,25 @@ module system_top (
.tx_ref_clk (ref_clk1),
.tx_sync (tx_sync),
.tx_sysref (sysref),
.dac_fifo_bypass(ad9371_dac_fifo_bypass_s));
.dac_fifo_bypass(ad9371_dac_fifo_bypass_s),
.sys_rst(sys_rst),
.sys_clk_clk_p (sys_clk_p),
.sys_clk_clk_n (sys_clk_n),
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n));
endmodule