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axi_logic_analyzer: Switched from BUFGMUX to BUFGMUX_CTRL for glitch free clock switching

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Adrian Costina 2017-02-27 14:19:54 +02:00
parent 545e458997
commit 37a1c98c12
2 changed files with 2 additions and 1 deletions
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2
library/axi_logic_analyzer/axi_logic_analyzer.v
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@ -142,7 +142,7 @@ module axi_logic_analyzer (
end end
endgenerate endgenerate
BUFGMUX BUFGMUX_inst ( BUFGMUX_CTRL BUFGMUX_CTRL_inst (
.O (clk_out), .O (clk_out),
.I0 (data_i[0]), .I0 (data_i[0]),
.I1 (trigger_i[0]), .I1 (trigger_i[0]),

1
library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc
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@ -28,3 +28,4 @@ set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg* &&
set_false_path -to [get_cells -hier -filter {name =~ *trigger_m1_reg* && IS_SEQUENTIAL}] set_false_path -to [get_cells -hier -filter {name =~ *trigger_m1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg* && IS_SEQUENTIAL}] set_false_path -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_pins BUFGMUX_CTRL_inst/S*]