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cftl: Delete unused projects and libraries

main
Istvan Csomortani 2017-09-28 15:41:31 +03:00 committed by István Csomortáni
parent bee392253b
commit 377848ef52
24 changed files with 0 additions and 1444 deletions
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4
library/Makefile
View File

@ -81,8 +81,6 @@ clean:
$(MAKE) -C util_gmii_to_rgmii clean
$(MAKE) -C util_i2c_mixer clean
$(MAKE) -C util_mfifo clean
$(MAKE) -C util_pmod_adc clean
$(MAKE) -C util_pmod_fmeter clean
$(MAKE) -C util_pulse_gen clean
$(MAKE) -C util_rfifo clean
$(MAKE) -C util_sigma_delta_spi clean
@ -174,8 +172,6 @@ lib:
$(MAKE) -C util_gmii_to_rgmii
$(MAKE) -C util_i2c_mixer
$(MAKE) -C util_mfifo
$(MAKE) -C util_pmod_adc
$(MAKE) -C util_pmod_fmeter
$(MAKE) -C util_pulse_gen
$(MAKE) -C util_rfifo
$(MAKE) -C util_sigma_delta_spi

47
library/util_pmod_adc/Makefile
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@ -1,47 +0,0 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += util_pmod_adc.v
M_DEPS += util_pmod_adc_constr.xdc
M_DEPS += util_pmod_adc_ip.tcl
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
.PHONY: all clean clean-all
all: util_pmod_adc.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
util_pmod_adc.xpr: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) util_pmod_adc_ip.tcl >> util_pmod_adc_ip.log 2>&1
####################################################################################
####################################################################################

284
library/util_pmod_adc/util_pmod_adc.v
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@ -1,284 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// This core supports the following CFTL pmods:
// - EVAL-CN0350-PMDZ
// - EVAL-CN0335-PMDZ
// - EVAL-CN0336-PMDZ
// - EVAL-CN0337-PMDZ
//
// It controls a simple three wire SPI interface with an additional control
// line for conversion start, and a counter which trigger the SPI read after
// the end of ADC conversion.
// NOTE: - The maximum frequency of serial read clock (adc_spi_clk) is 50Mhz.
// - The maximum conversion rate is 1MSPS (AD7091r)
// - The frequency of the serial read clock need to be adjusted to the desired
// conversion rate, exp. for AD7091r :
//
// ADC Rate >= ADC Conversion Time + SPI Word Length * ADC Serial Clock Period + Tquiet
// where ADC Conversion Time >= 650ns
// SPI Word Length = 12
// Tquiet >= 58ns
`timescale 1ns/1ns
module util_pmod_adc #(
parameter FPGA_CLOCK_MHZ = 100,
parameter ADC_CONVST_NS = 100,
parameter ADC_CONVERT_NS = 650,
parameter ADC_TQUIET_NS = 60,
parameter SPI_WORD_LENGTH = 12,
parameter ADC_RESET_LENGTH = 3,
parameter ADC_CLK_DIVIDE = 16) (
// clock and reset signals
input clk,
input resetn,
// dma interface
output reg [15:0] adc_data,
output reg adc_valid,
output reg [24:0] adc_dbg,
// adc interface (clk, data, cs and conversion start)
input adc_sdo,
output adc_sclk,
output reg adc_cs_n,
output reg adc_convst_n);
localparam ADC_POWERUP = 0;
localparam ADC_SW_RESET = 1;
localparam ADC_IDLE = 2;
localparam ADC_START_CNV = 3;
localparam ADC_WAIT_CNV_DONE = 4;
localparam ADC_READ_CNV_RESULT = 5;
localparam ADC_DATA_VALID = 6;
localparam ADC_TQUIET = 7;
localparam [15:0] FPGA_CLOCK_PERIOD_NS = 1000 / FPGA_CLOCK_MHZ;
localparam [15:0] ADC_CONVST_CNT = ADC_CONVST_NS / FPGA_CLOCK_PERIOD_NS;
localparam [15:0] ADC_CONVERT_CNT = ADC_CONVERT_NS / FPGA_CLOCK_PERIOD_NS;
localparam [15:0] ADC_TQUITE_CNT = ADC_TQUIET_NS / FPGA_CLOCK_PERIOD_NS;
// Internal registers
reg [ 2:0] adc_state = 3'b0; // current state for the ADC control state machine
reg [ 2:0] adc_next_state = 3'b0; // next state for the ADC control state machine
reg [15:0] adc_tconvst_cnt = 16'b0;
reg [15:0] adc_tconvert_cnt = 16'b0;
reg [15:0] adc_tquiet_cnt = 16'b0;
reg [15:0] sclk_clk_cnt = 16'b0;
reg [15:0] sclk_clk_cnt_m1 = 16'b0;
reg [7:0] adc_clk_cnt = 8'h0;
reg adc_clk_en = 1'b0;
reg adc_sw_reset = 1'b0;
reg data_rd_ready = 1'b0;
reg adc_spi_clk = 1'b0;
// Assign/Always Blocks
assign adc_sclk = adc_spi_clk & adc_clk_en;
// spi clock generation
always @(posedge clk) begin
adc_clk_cnt <= adc_clk_cnt + 1;
if (adc_clk_cnt == ((ADC_CLK_DIVIDE/2)-1)) begin
adc_clk_cnt <= 0;
adc_spi_clk <= ~adc_spi_clk;
end
end
// update the ADC timing counters
always @(posedge clk)
begin
if(resetn == 1'b0) begin
adc_tconvst_cnt <= ADC_CONVST_CNT;
adc_tconvert_cnt <= ADC_CONVERT_CNT;
adc_tquiet_cnt <= ADC_TQUITE_CNT;
end else begin
if(adc_state == ADC_START_CNV) begin
adc_tconvst_cnt <= adc_tconvst_cnt - 1;
end else begin
adc_tconvst_cnt <= ADC_CONVST_CNT;
end
if((adc_state == ADC_START_CNV) || (adc_state == ADC_WAIT_CNV_DONE)) begin
adc_tconvert_cnt <= adc_tconvert_cnt - 1;
end else begin
adc_tconvert_cnt <= ADC_CONVERT_CNT;
end
if(adc_state == ADC_TQUIET) begin
adc_tquiet_cnt <= adc_tquiet_cnt - 1;
end else begin
adc_tquiet_cnt <= ADC_TQUITE_CNT;
end
end
end
// determine when the ADC clock is valid
always @(negedge adc_spi_clk) begin
adc_clk_en <= ((adc_state == ADC_READ_CNV_RESULT) && (sclk_clk_cnt != 0)) ? 1'b1 : 1'b0;
end
// read data from the ADC
always @(negedge adc_spi_clk) begin
sclk_clk_cnt_m1 <= sclk_clk_cnt;
if((adc_clk_en == 1'b1) && (sclk_clk_cnt != 0)) begin
adc_data <= {3'b0, adc_data[11:0], adc_sdo};
if ((adc_sw_reset == 1'b1) && (sclk_clk_cnt == SPI_WORD_LENGTH - ADC_RESET_LENGTH + 1)) begin
sclk_clk_cnt <= 16'b0;
end else begin
sclk_clk_cnt <= sclk_clk_cnt - 1;
end
end
else if(adc_state != ADC_READ_CNV_RESULT) begin
adc_data <= 16'h0;
sclk_clk_cnt <= SPI_WORD_LENGTH - 1;
end
end
// update the ADC current state and the control signals
always @(posedge clk) begin
if(resetn == 1'b0) begin
adc_state <= ADC_SW_RESET;
adc_dbg <= 1'b0;
end
else begin
adc_state <= adc_next_state;
adc_dbg <= {adc_state, adc_clk_en, sclk_clk_cnt};
case (adc_state)
ADC_POWERUP: begin
adc_convst_n <= 1'b1;
adc_cs_n <= 1'b1;
adc_valid <= 1'b0;
adc_sw_reset <= 1'b0;
end
ADC_SW_RESET: begin
adc_convst_n <= 1'b1;
adc_cs_n <= 1'b1;
adc_valid <= 1'b0;
adc_sw_reset <= 1'b1;
end
ADC_IDLE: begin
adc_convst_n <= 1'b1;
adc_cs_n <= 1'b1;
adc_valid <= 1'b0;
adc_sw_reset <= 1'b0;
end
ADC_START_CNV: begin
adc_convst_n <= 1'b0;
adc_cs_n <= 1'b1;
adc_valid <= 1'b0;
end
ADC_WAIT_CNV_DONE: begin
adc_convst_n <= 1'b1;
adc_cs_n <= 1'b1;
adc_valid <= 1'b0;
end
ADC_READ_CNV_RESULT: begin
adc_convst_n <= 1'b1;
adc_cs_n <= 1'b0;
adc_valid <= 1'b0;
end
ADC_DATA_VALID: begin
adc_convst_n <= 1'b1;
adc_cs_n <= 1'b0;
adc_valid <= 1'b1;
end
ADC_TQUIET: begin
adc_convst_n <= 1'b1;
adc_cs_n <= 1'b1;
adc_valid <= 1'b0;
end
endcase
end
end
// update the ADC next state
always @(adc_state, adc_tconvst_cnt, adc_tconvert_cnt, sclk_clk_cnt_m1, adc_tquiet_cnt, adc_sw_reset) begin
adc_next_state <= adc_state;
case (adc_state)
ADC_POWERUP: begin
if(adc_sw_reset == 1'b1) begin
adc_next_state <= ADC_SW_RESET;
end
end
ADC_SW_RESET: begin
adc_next_state <= ADC_START_CNV;
end
ADC_IDLE: begin
adc_next_state <= ADC_START_CNV;
end
ADC_START_CNV: begin
if(adc_tconvst_cnt == 0) begin
adc_next_state <= ADC_WAIT_CNV_DONE;
end
end
ADC_WAIT_CNV_DONE: begin
if(adc_tconvert_cnt == 0) begin
adc_next_state <= ADC_READ_CNV_RESULT;
end
end
ADC_READ_CNV_RESULT: begin
if(sclk_clk_cnt_m1 == 0) begin
adc_next_state <= ADC_DATA_VALID;
end
end
ADC_DATA_VALID: begin
adc_next_state <= ADC_TQUIET;
end
ADC_TQUIET: begin
if(adc_tquiet_cnt == 0) begin
adc_next_state <= ADC_IDLE;
end
end
default: begin
adc_next_state <= ADC_IDLE;
end
endcase
end
endmodule

1
library/util_pmod_adc/util_pmod_adc_constr.xdc
View File

@ -1 +0,0 @@
create_generated_clock -name adc_spi_clk -source [get_ports clk] -divide_by 16 [get_pins -hier *adc_spi_clk_reg/Q]

15
library/util_pmod_adc/util_pmod_adc_ip.tcl
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@ -1,15 +0,0 @@
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_pmod_adc
adi_ip_files util_pmod_adc [list \
"util_pmod_adc.v" \
"util_pmod_adc_constr.xdc"
]
adi_ip_properties_lite util_pmod_adc
ipx::save_core [ipx::current_core]

51
library/util_pmod_fmeter/Makefile
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@ -1,51 +0,0 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_pmod.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += util_pmod_fmeter.v
M_DEPS += util_pmod_fmeter_core.v
M_DEPS += util_pmod_fmeter_ip.tcl
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
.PHONY: all clean clean-all
all: util_pmod_fmeter.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
util_pmod_fmeter.xpr: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) util_pmod_fmeter_ip.tcl >> util_pmod_fmeter_ip.log 2>&1
####################################################################################
####################################################################################

146
library/util_pmod_fmeter/util_pmod_fmeter.v
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@ -1,146 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
module util_pmod_fmeter #(
parameter ID = 0) (
input ref_clk,
input square_signal,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
// internal signals
wire up_clk;
wire up_rstn;
wire reset;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s;
wire up_rack_s;
wire up_wack_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire [31:0] signal_freq_s;
//defaults
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_valid = 1'b1;
// frequency measurment module
util_pmod_fmeter_core i_util_pmod_fmeter_core (
.ref_clk(ref_clk),
.reset(reset),
.square_signal(square_signal),
.signal_freq(signal_freq_s));
// register map
up_pmod i_up_pmod(
.pmod_clk(ref_clk),
.pmod_rst(reset),
.pmod_signal_freq(signal_freq_s),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq(up_wreq_s),
.up_waddr(up_waddr_s),
.up_wdata(up_wdata_s),
.up_wack(up_wack_s),
.up_rreq(up_rreq_s),
.up_raddr(up_raddr_s),
.up_rdata(up_rdata_s),
.up_rack(up_rack_s));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule

73
library/util_pmod_fmeter/util_pmod_fmeter_core.v
View File

@ -1,73 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
module util_pmod_fmeter_core (
input ref_clk,
input reset,
input square_signal,
output reg [31:0] signal_freq);
// registers
reg [31:0] signal_freq_counter = 'h0;
reg [ 2:0] square_signal_buf = 'h0;
wire signal_freq_en;
assign signal_freq_en = ~square_signal_buf[2] & square_signal_buf[1];
// internal signals
always @(posedge ref_clk) begin
square_signal_buf[0] <= square_signal;
square_signal_buf[2:1] <= square_signal_buf[1:0];
end
always @(posedge ref_clk) begin
if (reset == 1'b1) begin
signal_freq <= 32'b0;
signal_freq_counter <= 32'b0;
end else begin
if(signal_freq_en == 1'b1) begin
signal_freq <= signal_freq_counter;
signal_freq_counter <= 32'h0;
end else begin
signal_freq_counter <= signal_freq_counter + 32'h1;
end
end
end
endmodule

18
library/util_pmod_fmeter/util_pmod_fmeter_ip.tcl
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@ -1,18 +0,0 @@
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_pmod_fmeter
adi_ip_files util_pmod_fmeter [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_pmod.v" \
"util_pmod_fmeter.v" \
"util_pmod_fmeter_core.v"]
adi_ip_properties util_pmod_fmeter
ipx::save_core [ipx::current_core]

6
projects/Makefile
View File

@ -24,8 +24,6 @@ all:
-$(MAKE) -C adrv9379 all
-$(MAKE) -C adv7511 all
-$(MAKE) -C arradio all
-$(MAKE) -C cftl_cip all
-$(MAKE) -C cftl_std all
-$(MAKE) -C cn0363 all
-$(MAKE) -C daq1 all
-$(MAKE) -C daq2 all
@ -65,8 +63,6 @@ clean:
$(MAKE) -C adrv9379 clean
$(MAKE) -C adv7511 clean
$(MAKE) -C arradio clean
$(MAKE) -C cftl_cip clean
$(MAKE) -C cftl_std clean
$(MAKE) -C cn0363 clean
$(MAKE) -C daq1 clean
$(MAKE) -C daq2 clean
@ -106,8 +102,6 @@ clean-all:
$(MAKE) -C adrv9379 clean-all
$(MAKE) -C adv7511 clean-all
$(MAKE) -C arradio clean-all
$(MAKE) -C cftl_cip clean-all
$(MAKE) -C cftl_std clean-all
$(MAKE) -C cn0363 clean-all
$(MAKE) -C daq1 clean-all
$(MAKE) -C daq2 clean-all

21
projects/cftl_cip/Makefile
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@ -1,21 +0,0 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
.PHONY: all clean clean-all
all:
-$(MAKE) -C zed all
clean:
$(MAKE) -C zed clean
clean-all:
$(MAKE) -C zed clean-all
####################################################################################
####################################################################################

63
projects/cftl_cip/common/cftl_cip_bd.tcl
View File

@ -1,63 +0,0 @@
global adc_spi_freq
# pmod interfaces
create_bd_port -dir O pmod_spi_cs
create_bd_port -dir I pmod_spi_miso
create_bd_port -dir O pmod_spi_clk
create_bd_port -dir O pmod_spi_convst
create_bd_port -dir I pmod_gpio
# instances
ad_ip_instance util_pmod_adc pmod_spi_core
ad_ip_parameter pmod_spi_core CONFIG.FPGA_CLOCK_MHZ 100
ad_ip_instance axi_dmac pmod_spi_dma
ad_ip_parameter pmod_spi_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter pmod_spi_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter pmod_spi_dma CONFIG.ID 0
ad_ip_parameter pmod_spi_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter pmod_spi_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter pmod_spi_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter pmod_spi_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter pmod_spi_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter pmod_spi_dma CONFIG.CYCLIC 0
ad_ip_parameter pmod_spi_dma CONFIG.DMA_DATA_WIDTH_SRC 16
ad_ip_parameter pmod_spi_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_ip_instance util_pmod_fmeter pmod_gpio_core
# additional configurations
ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 1
ad_connect sys_cpu_clk pmod_spi_dma/fifo_wr_clk
ad_connect sys_cpu_clk pmod_spi_core/clk
ad_connect sys_cpu_clk pmod_gpio_core/ref_clk
ad_connect pmod_spi_core/resetn sys_rstgen/peripheral_aresetn
ad_connect pmod_spi_core/adc_data pmod_spi_dma/fifo_wr_din
ad_connect pmod_spi_core/adc_valid pmod_spi_dma/fifo_wr_en
ad_connect pmod_spi_miso pmod_spi_core/adc_sdo
ad_connect pmod_spi_clk pmod_spi_core/adc_sclk
ad_connect pmod_spi_cs pmod_spi_core/adc_cs_n
ad_connect pmod_spi_convst pmod_spi_core/adc_convst_n
ad_connect pmod_gpio pmod_gpio_core/square_signal
# interrupts
ad_cpu_interrupt ps-13 mb-12 pmod_spi_dma/irq
# cpu / memory interconnects
ad_cpu_interconnect 0x43010000 pmod_spi_dma
ad_cpu_interconnect 0x43C00000 pmod_gpio_core
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_cpu_clk pmod_spi_dma/m_dest_axi

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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += system_top.v
M_DEPS += system_project.tcl
M_DEPS += system_constr.xdc
M_DEPS += system_bd.tcl
M_DEPS += ../common/cftl_cip_bd.tcl
M_DEPS += ../../scripts/adi_project.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr
M_DEPS += ../../../library/util_pmod_adc/util_pmod_adc.xpr
M_DEPS += ../../../library/util_pmod_fmeter/util_pmod_fmeter.xpr
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.runs
M_FLIST += *.srcs
M_FLIST += *.sdk
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
M_FLIST += *.ip_user_files
.PHONY: all lib clean clean-all
all: lib cftl_custom_zed.sdk/system_top.hdf
clean:
rm -rf $(M_FLIST)
clean-all:clean
$(MAKE) -C ../../../library/axi_clkgen clean
$(MAKE) -C ../../../library/axi_dmac clean
$(MAKE) -C ../../../library/axi_hdmi_tx clean
$(MAKE) -C ../../../library/axi_i2s_adi clean
$(MAKE) -C ../../../library/axi_spdif_tx clean
$(MAKE) -C ../../../library/util_i2c_mixer clean
$(MAKE) -C ../../../library/util_pmod_adc clean
$(MAKE) -C ../../../library/util_pmod_fmeter clean
cftl_custom_zed.sdk/system_top.hdf: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) system_project.tcl >> cftl_custom_zed_vivado.log 2>&1
lib:
$(MAKE) -C ../../../library/axi_clkgen
$(MAKE) -C ../../../library/axi_dmac
$(MAKE) -C ../../../library/axi_hdmi_tx
$(MAKE) -C ../../../library/axi_i2s_adi
$(MAKE) -C ../../../library/axi_spdif_tx
$(MAKE) -C ../../../library/util_i2c_mixer
$(MAKE) -C ../../../library/util_pmod_adc
$(MAKE) -C ../../../library/util_pmod_fmeter
####################################################################################
####################################################################################

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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source ../common/cftl_cip_bd.tcl

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# pmod connectors
# JA supports : CN0350, CN0335, CN0336 and CN0337
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports pmod_spi_cs] ; ## JA1
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS33} [get_ports pmod_spi_miso] ; ## JA3
set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports pmod_spi_clk] ; ## JA4
set_property -dict {PACKAGE_PIN AB9 IOSTANDARD LVCMOS33} [get_ports pmod_spi_convst] ; ## JA9
# JB supports CN0332
set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS33} [get_ports pmod_gpio] ; ## JB4

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
# adc's SPI frequency in Mhz
global adc_spi_freq
# EVAL-CN0335[6/7]-PMDZ
set adc_spi_freq 7
# EVAL-CN0350-PMDZ
#set adc_spi_freq 50
adi_project_xilinx cftl_custom_zed
adi_project_files cftl_custom_zed [list \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"]
adi_project_run cftl_custom_zed

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [31:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [15:0] hdmi_data,
output i2s_mclk,
output i2s_bclk,
output i2s_lrclk,
output i2s_sdata_out,
input i2s_sdata_in,
output spdif,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
inout [ 1:0] iic_mux_sda,
input otg_vbusoc,
output pmod_spi_cs,
input pmod_spi_miso,
output pmod_spi_clk,
output pmod_spi_convst,
input pmod_gpio);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
assign gpio_i[63:32] = gpio_o[63:32];
// instantiations
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_12 (1'b0),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif),
.spi0_clk_i (1'b0),
.spi0_clk_o (),
.spi0_csn_0_o (),
.spi0_csn_1_o (),
.spi0_csn_2_o (),
.spi0_csn_i (1'b1),
.spi0_sdi_i (1'b0),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (),
.spi1_clk_i (1'b0),
.spi1_clk_o (),
.spi1_csn_0_o (),
.spi1_csn_1_o (),
.spi1_csn_2_o (),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0),
.spi1_sdo_o (),
.pmod_spi_cs (pmod_spi_cs),
.pmod_spi_miso (pmod_spi_miso),
.pmod_spi_clk (pmod_spi_clk),
.pmod_spi_convst (pmod_spi_convst),
.pmod_gpio (pmod_gpio));
endmodule
// ***************************************************************************
// ***************************************************************************

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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
.PHONY: all clean clean-all
all:
-$(MAKE) -C zed all
clean:
$(MAKE) -C zed clean
clean-all:
$(MAKE) -C zed clean-all
####################################################################################
####################################################################################

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projects/cftl_std/common/cftl_std_bd.tcl
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@ -1,13 +0,0 @@
# cftl
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_cftl
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_cftl
# iic
ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_PERIPHERAL_ENABLE 1
# iic cftl
ad_connect iic_cftl sys_ps7/IIC_0

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@ -1,72 +0,0 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += system_top.v
M_DEPS += system_project.tcl
M_DEPS += system_constr.xdc
M_DEPS += system_bd.tcl
M_DEPS += ../common/cftl_std_bd.tcl
M_DEPS += ../../scripts/adi_project.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.runs
M_FLIST += *.srcs
M_FLIST += *.sdk
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
M_FLIST += *.ip_user_files
.PHONY: all lib clean clean-all
all: lib cftl_std_zed.sdk/system_top.hdf
clean:
rm -rf $(M_FLIST)
clean-all:clean
$(MAKE) -C ../../../library/axi_clkgen clean
$(MAKE) -C ../../../library/axi_hdmi_tx clean
$(MAKE) -C ../../../library/axi_i2s_adi clean
$(MAKE) -C ../../../library/axi_spdif_tx clean
$(MAKE) -C ../../../library/util_i2c_mixer clean
cftl_std_zed.sdk/system_top.hdf: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) system_project.tcl >> cftl_std_zed_vivado.log 2>&1
lib:
$(MAKE) -C ../../../library/axi_clkgen
$(MAKE) -C ../../../library/axi_hdmi_tx
$(MAKE) -C ../../../library/axi_i2s_adi
$(MAKE) -C ../../../library/axi_spdif_tx
$(MAKE) -C ../../../library/util_i2c_mixer
####################################################################################
####################################################################################

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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source ../common/cftl_std_bd.tcl

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projects/cftl_std/zed/system_constr.xdc
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# CFTL
#port JA compatible with: CN0179, CN0216, CN10326, CN0354, CN0355
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports spi0_csn]; # "JA1"
set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS33} [get_ports spi0_mosi]; # "JA2"
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS33} [get_ports spi0_miso]; # "JA3"
set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports spi0_clk]; # "JA4"
set_property -dict {PACKAGE_PIN AB9 IOSTANDARD LVCMOS33} [get_ports gpio_cftl[0]]; # "JA9"
set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports gpio_cftl[1]]; # "JA10"
#port JB compatible with: CN0346, CN0349
set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports iic_cftl_scl_io]; # "JB3"
set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS33} [get_ports iic_cftl_sda_io]; # "JB4"
#port JC compatible with: CN0179, CN0357
set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports spi1_csn0]; # "JC1_P"
set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports spi1_mosi]; # "JC1_N"
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33} [get_ports spi1_miso]; # "JC2_P"
set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS33} [get_ports spi1_clk]; # "JC2_N"
set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports spi1_csn1]; # "JC4_N"

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_xilinx cftl_std_zed
adi_project_files cftl_std_zed [list \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ]
adi_project_run cftl_std_zed

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [31:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [15:0] hdmi_data,
output i2s_mclk,
output i2s_bclk,
output i2s_lrclk,
output i2s_sdata_out,
input i2s_sdata_in,
output spdif,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
inout [ 1:0] iic_mux_sda,
inout iic_cftl_scl_io,
inout iic_cftl_sda_io,
output spi0_mosi,
input spi0_miso,
output spi0_clk,
output spi0_csn,
output spi1_mosi,
input spi1_miso,
output spi1_clk,
output spi1_csn0,
output spi1_csn1,
inout [ 1:0] gpio_cftl,
input otg_vbusoc);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
wire [15:0] ps_intrs;
assign gpio_i[63:34] = gpio_o[63:34];
// instantiations
ad_iobuf #(
.DATA_WIDTH(32))
i_gpio_bd (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2))
i_gpio_cftl (
.dio_t(gpio_t[33:32]),
.dio_i(gpio_o[33:32]),
.dio_o(gpio_i[33:32]),
.dio_p(gpio_cftl));
ad_iobuf #(
.DATA_WIDTH(2))
i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2))
i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_cftl_scl_io(iic_cftl_scl_io),
.iic_cftl_sda_io(iic_cftl_sda_io),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_12 (1'b0),
.ps_intr_13 (1'b0),
.otg_vbusoc (otg_vbusoc),
.spi0_csn_i (1'b1),
.spi0_csn_0_o (spi0_csn),
.spi0_csn_1_o (),
.spi0_csn_2_o (),
.spi0_sdi_i (spi0_miso),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (spi0_mosi),
.spi0_clk_i (1'b0),
.spi0_clk_o (spi0_clk),
.spi1_csn_i (1'b1),
.spi1_csn_0_o (spi1_csn0),
.spi1_csn_1_o (spi1_csn1),
.spi1_csn_2_o (),
.spi1_sdi_i (spi1_miso),
.spi1_sdo_i (spi1_mosi),
.spi1_sdo_o (spi1_mosi),
.spi1_clk_i (1'b0),
.spi1_clk_o (spi1_clk),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************