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altera- remove lvds/serdes/cmos cores

main
Rejeesh Kutty 2017-07-20 14:19:40 -04:00
parent e1c95b23ea
commit 36a9ea40b1
9 changed files with 0 additions and 1105 deletions
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82
library/altera/common/ad_cmos_clk.v
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@ -1,82 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_cmos_clk #(
parameter DEVICE_TYPE = 0) (
input rst,
output locked,
input clk_in,
output clk);
// instantiations
generate
if (DEVICE_TYPE == 0) begin
alt_clk i_clk (
.rst (rst),
.refclk (clk_in),
.outclk_0 (clk),
.locked (locked));
end
endgenerate
generate
if (DEVICE_TYPE == 1) begin
altera_pll #(
.reference_clock_frequency("250.0 MHz"),
.operation_mode("source synchronous"),
.number_of_clocks(1),
.output_clock_frequency0("0 MHz"),
.phase_shift0("0"))
i_clk (
.rst (rst),
.refclk (clk_in),
.outclk (clk),
.fboutclk (),
.fbclk (1'b0),
.locked (locked));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

114
library/altera/common/ad_cmos_in.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_cmos_in #(
parameter DEVICE_TYPE = 0,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group") (
// data interface
input rx_clk,
input rx_data_in,
output reg rx_data_p,
output reg rx_data_n,
// delay-data interface
input up_clk,
input up_dld,
input [ 4:0] up_dwdata,
output [ 4:0] up_drdata,
// delay-cntrl interface
input delay_clk,
input delay_rst,
output delay_locked);
// local parameter
localparam ARRIA10 = 0;
localparam CYCLONE5 = 1;
// internal signals
wire rx_data_p_s;
wire rx_data_n_s;
// defaults
assign up_drdata = 5'd0;
assign delay_locked = 1'b1;
// instantiations
generate
if (DEVICE_TYPE == ARRIA10) begin
alt_ddio_in i_rx_data_iddr (
.ck (rx_clk),
.pad_in (rx_data_in),
.dout ({rx_data_p_s, rx_data_n_s}));
end
endgenerate
generate
if (DEVICE_TYPE == CYCLONE5) begin
altddio_in #(.width (1), .lpm_hint("UNUSED")) i_rx_data_iddr (
.inclock (rx_clk),
.datain (rx_data_in),
.dataout_h (rx_data_p_s),
.dataout_l (rx_data_n_s),
.inclocken (1'b1),
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0));
end
endgenerate
always @(posedge rx_clk) begin
rx_data_p <= rx_data_p_s;
rx_data_n <= rx_data_n_s;
end
endmodule
// ***************************************************************************
// ***************************************************************************

98
library/altera/common/ad_cmos_out.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module __ad_cmos_out__ #(
parameter DEVICE_TYPE = 0,
parameter IODELAY_ENABLE = 0,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group") (
// data interface
input tx_clk,
input tx_data_p,
input tx_data_n,
output tx_data_out,
// delay-data interface
input up_clk,
input up_dld,
input [ 4:0] up_dwdata,
output [ 4:0] up_drdata,
// delay-cntrl interface
input delay_clk,
input delay_rst,
output delay_locked);
// local parameter
localparam ARRIA10 = 0;
localparam CYCLONE5 = 1;
// defaults
assign up_drdata = 5'd0;
assign delay_locked = 1'b1;
// instantiations
generate
if (DEVICE_TYPE == ARRIA10) begin
__ad_cmos_out_1__ i_tx_data_oddr (
.clk_export (tx_clk),
.din_export ({tx_data_p, tx_data_n}),
.pad_out_export (tx_data_out));
end
endgenerate
generate
if (DEVICE_TYPE == CYCLONE5) begin
ad_cmos_out_core_c5 i_tx_data_oddr (
.clk (tx_clk),
.din ({tx_data_p, tx_data_n}),
.pad_out (tx_data_out));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

82
library/altera/common/ad_lvds_clk.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_lvds_clk #(
parameter DEVICE_TYPE = 0) (
input rst,
output locked,
input clk_in_p,
input clk_in_n,
output clk);
// instantiations
generate
if (DEVICE_TYPE == 0) begin
alt_clk i_clk (
.rst (rst),
.refclk (clk_in_p),
.outclk_0 (clk),
.locked (locked));
end
endgenerate
generate
if (DEVICE_TYPE == 1) begin
altera_pll #(
.reference_clock_frequency("250.0 MHz"),
.operation_mode("lvds"),
.number_of_clocks(1),
.output_clock_frequency0("250.0 MHz"),
.phase_shift0("0"))
i_clk (
.rst (rst),
.refclk (clk_in_p),
.outclk (clk),
.locked (locked));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

113
library/altera/common/ad_lvds_in.v
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@ -1,113 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_lvds_in #(
parameter SINGLE_ENDED = 0,
parameter DEVICE_TYPE = 0,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group") (
// data interface
input rx_clk,
input rx_data_in_p,
input rx_data_in_n,
output reg rx_data_p,
output reg rx_data_n,
// delay-data interface
input up_clk,
input up_dld,
input [ 4:0] up_dwdata,
output [ 4:0] up_drdata,
// delay-cntrl interface
input delay_clk,
input delay_rst,
output delay_locked);
// internal registers
// internal signals
wire rx_data_p_s;
wire rx_data_n_s;
// defaults
assign up_drdata = 5'd0;
assign delay_locked = 1'b1;
// instantiations
generate
if (DEVICE_TYPE == 0) begin
alt_ddio_in i_rx_data_iddr (
.ck (rx_clk),
.pad_in (rx_data_in_p),
.dout ({rx_data_p_s, rx_data_n_s}));
end
endgenerate
generate
if (DEVICE_TYPE == 1) begin
altddio_in #(.width (1), .lpm_hint("UNUSED")) i_rx_data_iddr (
.inclock (rx_clk),
.datain (rx_data_in_p),
.dataout_h (rx_data_p_s),
.dataout_l (rx_data_n_s),
.inclocken (1'b1),
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0));
end
endgenerate
always @(posedge rx_clk) begin
rx_data_p <= rx_data_p_s;
rx_data_n <= rx_data_n_s;
end
endmodule
// ***************************************************************************
// ***************************************************************************

104
library/altera/common/ad_lvds_out.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_lvds_out #(
parameter DEVICE_TYPE = 0,
parameter SINGLE_ENDED = 0,
parameter IODELAY_ENABLE = 0,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group") (
// data interface
input tx_clk,
input tx_data_p,
input tx_data_n,
output tx_data_out_p,
output tx_data_out_n,
// delay-data interface
input up_clk,
input up_dld,
input [ 4:0] up_dwdata,
output [ 4:0] up_drdata,
// delay-cntrl interface
input delay_clk,
input delay_rst,
output delay_locked);
// defaults
assign up_drdata = 5'd0;
assign delay_locked = 1'b1;
// instantiations
generate
if (DEVICE_TYPE == 0) begin
alt_ddio_out i_tx_data_oddr (
.ck (tx_clk),
.din ({tx_data_p, tx_data_n}),
.pad_out (tx_data_out_p));
end
endgenerate
generate
if (DEVICE_TYPE == 1) begin
altddio_out #(.width (1), .lpm_hint ("UNUSED")) i_tx_data_oddr (
.outclock (tx_clk),
.datain_h (tx_data_p),
.datain_l (tx_data_n),
.dataout (tx_data_out_p),
.outclocken (1'b1),
.oe_out (),
.oe (1'b1),
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

209
library/altera/common/ad_serdes_clk.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module __ad_serdes_clk__ #(
// parameters
parameter DEVICE_TYPE = 0,
parameter DDR_OR_SDR_N = 1,
parameter SERDES_FACTOR = 8,
parameter MMCM_OR_BUFR_N = 1,
parameter MMCM_CLKIN_PERIOD = 1.667,
parameter MMCM_VCO_DIV = 6,
parameter MMCM_VCO_MUL = 12.000,
parameter MMCM_CLK0_DIV = 2.000,
parameter MMCM_CLK1_DIV = 6) (
// clock and divided clock
input rst,
input clk_in_p,
input clk_in_n,
output clk,
output div_clk,
output out_clk,
output loaden,
output [ 7:0] phase,
// drp interface
input up_clk,
input up_rstn,
input up_drp_sel,
input up_drp_wr,
input [11:0] up_drp_addr,
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked);
// local parameter
localparam ARRIA10 = 0;
localparam CYCLONE5 = 1;
// internal registers
reg up_drp_sel_int = 'd0;
reg up_drp_rd_int = 'd0;
reg up_drp_wr_int = 'd0;
reg [ 8:0] up_drp_addr_int = 'd0;
reg [31:0] up_drp_wdata_int = 'd0;
reg [31:0] up_drp_rdata_int = 'd0;
reg up_drp_ready_int = 'd0;
reg up_drp_locked_int_m = 'd0;
reg up_drp_locked_int = 'd0;
// internal signals
wire up_drp_reset;
wire [31:0] up_drp_rdata_int_s;
wire up_drp_busy_int_s;
wire up_drp_locked_int_s;
wire loaden_s;
wire clk_s;
// defaults
assign up_drp_reset = ~up_rstn;
assign out_clk = div_clk;
assign up_drp_rdata = up_drp_rdata_int;
assign up_drp_ready = up_drp_ready_int;
assign up_drp_locked = up_drp_locked_int;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_drp_sel_int <= 1'b0;
up_drp_rd_int <= 1'b0;
up_drp_wr_int <= 1'b0;
up_drp_addr_int <= 9'd0;
up_drp_wdata_int <= 32'd0;
up_drp_rdata_int <= 32'd0;
up_drp_ready_int <= 1'b0;
up_drp_locked_int_m <= 1'd0;
up_drp_locked_int <= 1'd0;
end else begin
if (up_drp_sel_int == 1'b1) begin
if (up_drp_busy_int_s == 1'b0) begin
up_drp_sel_int <= 1'b0;
up_drp_rd_int <= 1'b0;
up_drp_wr_int <= 1'b0;
up_drp_addr_int <= 9'd0;
up_drp_wdata_int <= 32'd0;
up_drp_rdata_int <= up_drp_rdata_int_s;
up_drp_ready_int <= 1'b1;
end
end else if (up_drp_sel == 1'b1) begin
up_drp_sel_int <= 1'b1;
up_drp_rd_int <= ~up_drp_wr;
up_drp_wr_int <= up_drp_wr;
up_drp_addr_int <= up_drp_addr[8:0];
up_drp_wdata_int <= up_drp_wdata;
up_drp_rdata_int <= 32'd0;
up_drp_ready_int <= 1'b0;
end else begin
up_drp_sel_int <= 1'b0;
up_drp_rd_int <= 1'b0;
up_drp_wr_int <= 1'b0;
up_drp_addr_int <= 9'd0;
up_drp_wdata_int <= 32'd0;
up_drp_rdata_int <= 32'd0;
up_drp_ready_int <= 1'b0;
end
up_drp_locked_int_m <= up_drp_locked_int_s;
up_drp_locked_int <= up_drp_locked_int_m;
end
end
generate
if (DEVICE_TYPE == ARRIA10) begin
__ad_serdes_clk_1__ i_core (
.rst_reset (rst),
.ref_clk_clk (clk_in_p),
.locked_export (up_drp_locked_int_s),
.hs_phase_phout (phase),
.hs_clk_lvds_clk (clk),
.loaden_loaden (loaden),
.ls_clk_clk (div_clk),
.drp_clk_clk (up_clk),
.drp_rst_reset (up_drp_reset),
.pll_reconfig_waitrequest (up_drp_busy_int_s),
.pll_reconfig_read (up_drp_rd_int),
.pll_reconfig_write (up_drp_wr_int),
.pll_reconfig_readdata (up_drp_rdata_int_s),
.pll_reconfig_address (up_drp_addr_int),
.pll_reconfig_writedata (up_drp_wdata_int));
end
endgenerate
generate
if (DEVICE_TYPE == CYCLONE5) begin
assign phase = 8'd0;
__ad_serdes_clk_1__ i_core (
.rst_reset (rst),
.ref_clk_clk (clk_in_p),
.locked_export (up_drp_locked_int_s),
.hs_clk_clk (clk_s),
.loaden_clk (loaden_s),
.ls_clk_clk (div_clk),
.drp_clk_clk (up_clk),
.drp_rst_reset (up_drp_reset),
.pll_reconfig_waitrequest (up_drp_busy_int_s),
.pll_reconfig_read (up_drp_rd_int),
.pll_reconfig_write (up_drp_wr_int),
.pll_reconfig_readdata (up_drp_rdata_int_s),
.pll_reconfig_address (up_drp_addr_int[5:0]),
.pll_reconfig_writedata (up_drp_wdata_int));
cyclonev_pll_lvds_output #(
.pll_loaden_enable_disable ("true"),
.pll_lvdsclk_enable_disable ("true"))
i_clk_buf (
.ccout ({loaden_s, clk_s}),
.loaden (loaden),
.lvdsclk (clk));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

167
library/altera/common/ad_serdes_in.v
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@ -1,167 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module __ad_serdes_in__ #(
// parameters
parameter DEVICE_TYPE = 0,
parameter DDR_OR_SDR_N = 0,
parameter SERDES_FACTOR = 8,
parameter DATA_WIDTH = 16,
parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group") (
// reset and clocks
input rst,
input clk,
input div_clk,
input loaden,
input [ 7:0] phase,
input locked,
// data interface
output [(DATA_WIDTH-1):0] data_s0,
output [(DATA_WIDTH-1):0] data_s1,
output [(DATA_WIDTH-1):0] data_s2,
output [(DATA_WIDTH-1):0] data_s3,
output [(DATA_WIDTH-1):0] data_s4,
output [(DATA_WIDTH-1):0] data_s5,
output [(DATA_WIDTH-1):0] data_s6,
output [(DATA_WIDTH-1):0] data_s7,
input [(DATA_WIDTH-1):0] data_in_p,
input [(DATA_WIDTH-1):0] data_in_n,
// delay-data interface
input up_clk,
input [(DATA_WIDTH-1):0] up_dld,
input [((DATA_WIDTH*5)-1):0] up_dwdata,
output [((DATA_WIDTH*5)-1):0] up_drdata,
// delay-control interface
input delay_clk,
input delay_rst,
output delay_locked);
// local parameter
localparam ARRIA10 = 0;
localparam CYCLONE5 = 1;
// internal signals
wire [(DATA_WIDTH-1):0] delay_locked_s;
wire [(DATA_WIDTH-1):0] data_samples_s[0:(SERDES_FACTOR-1)];
wire [(SERDES_FACTOR-1):0] data_out_s[0:(DATA_WIDTH-1)];
// assignments
assign up_drdata = 5'd0;
assign delay_locked = & delay_locked_s;
// instantiations
genvar n;
genvar i;
generate
if (SERDES_FACTOR == 8) begin
assign data_s7 = data_samples_s[7];
assign data_s6 = data_samples_s[6];
assign data_s5 = data_samples_s[5];
assign data_s4 = data_samples_s[4];
end else begin
assign data_s7 = 'd0;
assign data_s6 = 'd0;
assign data_s5 = 'd0;
assign data_s4 = 'd0;
end
endgenerate
assign data_s3 = data_samples_s[3];
assign data_s2 = data_samples_s[2];
assign data_s1 = data_samples_s[1];
assign data_s0 = data_samples_s[0];
generate
for (i = 0; i < SERDES_FACTOR; i = i + 1) begin: g_samples
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_swap
assign data_samples_s[i][n] = data_out_s[n][i];
end
end
endgenerate
generate
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data
if (DEVICE_TYPE == CYCLONE5) begin
assign delay_locked_s[n] = 1'b1;
ad_serdes_in_core_c5 #(
.SERDES_FACTOR (SERDES_FACTOR))
i_core (
.clk (clk),
.div_clk (div_clk),
.enable (loaden),
.data_in (data_in_p[n]),
.data (data_out_s[n]));
end
if (DEVICE_TYPE == ARRIA10) begin
__ad_serdes_in_1__ i_core (
.clk_export (clk),
.div_clk_export (div_clk),
.hs_phase_export (phase),
.loaden_export (loaden),
.locked_export (locked),
.data_in_export (data_in_p[n]),
.data_s_export (data_out_s[n]),
.delay_locked_export (delay_locked_s[n]));
end
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************

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library/altera/common/ad_serdes_out.v
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@ -1,136 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module __ad_serdes_out__ #(
parameter DEVICE_TYPE = 0,
parameter DDR_OR_SDR_N = 1,
parameter SERDES_FACTOR = 8,
parameter DATA_WIDTH = 16) (
// reset and clocks
input rst,
input clk,
input div_clk,
input loaden,
// data interface
input [(DATA_WIDTH-1):0] data_s0,
input [(DATA_WIDTH-1):0] data_s1,
input [(DATA_WIDTH-1):0] data_s2,
input [(DATA_WIDTH-1):0] data_s3,
input [(DATA_WIDTH-1):0] data_s4,
input [(DATA_WIDTH-1):0] data_s5,
input [(DATA_WIDTH-1):0] data_s6,
input [(DATA_WIDTH-1):0] data_s7,
output [(DATA_WIDTH-1):0] data_out_p,
output [(DATA_WIDTH-1):0] data_out_n);
// local parameter
localparam ARRIA10 = 0;
localparam CYCLONE5 = 1;
// internal signals
wire [(DATA_WIDTH-1):0] data_samples_s[0:(SERDES_FACTOR-1)];
wire [(SERDES_FACTOR-1):0] data_in_s[0:(DATA_WIDTH-1)];
// defaults
assign data_out_n = 'd0;
// instantiations
genvar n;
genvar i;
generate
if (SERDES_FACTOR == 8) begin
assign data_samples_s[7] = data_s7;
assign data_samples_s[6] = data_s6;
assign data_samples_s[5] = data_s5;
assign data_samples_s[4] = data_s4;
end
endgenerate
assign data_samples_s[3] = data_s3;
assign data_samples_s[2] = data_s2;
assign data_samples_s[1] = data_s1;
assign data_samples_s[0] = data_s0;
generate
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_swap
for (i = 0; i < SERDES_FACTOR; i = i + 1) begin: g_samples
assign data_in_s[n][((SERDES_FACTOR-1)-i)] = data_samples_s[i][n];
end
end
endgenerate
generate
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data
if (DEVICE_TYPE == CYCLONE5) begin
ad_serdes_out_core_c5 #(
.SERDES_FACTOR (SERDES_FACTOR))
i_core (
.clk (clk),
.div_clk (div_clk),
.enable (loaden),
.data_out (data_out_p[n]),
.data (data_in_s[n]));
end
if (DEVICE_TYPE == ARRIA10) begin
__ad_serdes_out_1__ i_core (
.clk_export (clk),
.div_clk_export (div_clk),
.loaden_export (loaden),
.data_out_export (data_out_p[n]),
.data_s_export (data_in_s[n]));
end
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************