From 36a1767329bb25cc2c05b8c370000abb80c106f5 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Mon, 24 Jun 2019 14:08:39 +0100 Subject: [PATCH] Add generic fir filters processes for RF projects --- library/common/ad_bus_mux.v | 61 ++++++ projects/adrv9009/common/adrv9009_bd.tcl | 1 + projects/adrv9371x/common/adrv9371x_bd.tcl | 1 + projects/common/xilinx/adi_fir_filter_bd.tcl | 189 +++++++++++++++++++ projects/scripts/adi_board.tcl | 3 + 5 files changed, 255 insertions(+) create mode 100644 library/common/ad_bus_mux.v create mode 100644 projects/common/xilinx/adi_fir_filter_bd.tcl diff --git a/library/common/ad_bus_mux.v b/library/common/ad_bus_mux.v new file mode 100644 index 000000000..95933568e --- /dev/null +++ b/library/common/ad_bus_mux.v @@ -0,0 +1,61 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_bus_mux #( + + // Channel data width + parameter DATA_WIDTH = 16) ( + + input select_path, + + input valid_in_0, + input enable_in_0, + input [DATA_WIDTH-1:0] data_in_0, + + input valid_in_1, + input enable_in_1, + input [DATA_WIDTH-1:0] data_in_1, + + output valid_out, + output enable_out, + output [DATA_WIDTH-1:0] data_out); + + assign valid_out = (select_path == 0) ? valid_in_0 : valid_in_1; + assign enable_out = (select_path == 0) ? enable_in_0 : enable_in_1; + assign data_out = (select_path == 0) ? data_in_0 : data_in_1; + +endmodule diff --git a/projects/adrv9009/common/adrv9009_bd.tcl b/projects/adrv9009/common/adrv9009_bd.tcl index c1123455c..5884c3c02 100644 --- a/projects/adrv9009/common/adrv9009_bd.tcl +++ b/projects/adrv9009/common/adrv9009_bd.tcl @@ -28,6 +28,7 @@ set dac_data_width [expr 32*$TX_NUM_OF_LANES] set dac_dma_data_width 128 source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl +source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl # adrv9009 diff --git a/projects/adrv9371x/common/adrv9371x_bd.tcl b/projects/adrv9371x/common/adrv9371x_bd.tcl index 3a9a8900b..0ef7fa382 100644 --- a/projects/adrv9371x/common/adrv9371x_bd.tcl +++ b/projects/adrv9371x/common/adrv9371x_bd.tcl @@ -28,6 +28,7 @@ set dac_data_width [expr 32*$TX_NUM_OF_LANES] set dac_dma_data_width 128 source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl +source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl # ad9371 diff --git a/projects/common/xilinx/adi_fir_filter_bd.tcl b/projects/common/xilinx/adi_fir_filter_bd.tcl new file mode 100644 index 000000000..58bc0f2dd --- /dev/null +++ b/projects/common/xilinx/adi_fir_filter_bd.tcl @@ -0,0 +1,189 @@ + +################################################################################################### +################################################################################################### +## +# ad_add_decimation_filter - Creates a subsystem based on the Xilinx fir_compiler IP. +# \param[name] - Subsystem name +# \param[filter_rate] - Filter rate. E.g., 8 +# \param[n_chan] - Number of channels to filter +# \param[parallel_paths] - Number of paralell paths. For scenarios where +# the sampling rate is x times the core clock. +# \param[core_clk_mhz] - Core clock in MHz +# \param[sampl_freq_mhz] - Sampling frequency in MHz +proc ad_add_decimation_filter {name filter_rate n_chan parallel_paths \ + core_clk_mhz sampl_freq_mhz coe_file} { + global ad_hdl_dir + + create_bd_cell -type hier $name + set filter_name "fir_decimation" + + create_bd_pin -dir I $name/aclk + create_bd_pin -dir I $name/active + + # Adding the ad_bus_axis.v file in the project fileset sources_1 will not work + add_files -norecurse $ad_hdl_dir/library/common/ad_bus_mux.v + + + # add filter instances for n channels + for {set i 0} {$i < $n_chan} {incr i} { + ad_ip_instance fir_compiler $name/${filter_name}_${i} [ list \ + Decimation_Rate $filter_rate \ + Filter_Type "Decimation" \ + Interpolation_Rate 1 \ + Number_Paths $parallel_paths \ + Clock_Frequency $core_clk_mhz \ + Sample_Frequency $sampl_freq_mhz \ + CoefficientSource COE_File \ + Coefficient_File $coe_file \ + Coefficient_Fractional_Bits 0 \ + Data_Fractional_Bits 15 \ + Coefficient_Sets 1 \ + Coefficient_Sign Signed \ + Coefficient_Structure Inferred \ + Coefficient_Width 16 \ + ColumnConfig 5 \ + Filter_Architecture Systolic_Multiply_Accumulate \ + Number_Channels 1 \ + Output_Rounding_Mode Symmetric_Rounding_to_Zero \ + Output_Width 16 \ + Quantization Integer_Coefficients \ + RateSpecification Frequency_Specification \ + Zero_Pack_Factor 1 + ] + + ad_connect $name/aclk $name/${filter_name}_${i}/aclk + + create_bd_pin -dir I $name/valid_in_$i + create_bd_pin -dir I $name/enable_in_$i + create_bd_pin -dir O $name/valid_out_$i + create_bd_pin -dir O $name/enable_out_$i + create_bd_pin -dir I -from [expr 16*$parallel_paths-1] -to 0 $name/data_in_$i + create_bd_pin -dir O -from [expr 16*$parallel_paths-1] -to 0 $name/data_out_$i + + create_bd_cell -type module -reference ad_bus_mux $name/out_mux_$i + set_property -dict [list \ + CONFIG.DATA_WIDTH [expr 16 * $parallel_paths]] [get_bd_cells $name/out_mux_$i] + + ad_connect $name/valid_in_$i $name/out_mux_${i}/valid_in_0 + ad_connect $name/enable_in_$i $name/out_mux_${i}/enable_in_0 + ad_connect $name/data_in_$i $name/out_mux_${i}/data_in_0 + + ad_connect $name/valid_in_$i $name/${filter_name}_${i}/s_axis_data_tvalid + ad_connect $name/enable_in_$i $name/out_mux_${i}/enable_in_1 + ad_connect $name/data_in_$i $name/${filter_name}_${i}/s_axis_data_tdata + + ad_connect $name/${filter_name}_${i}/m_axis_data_tvalid $name/out_mux_${i}/valid_in_1 + ad_connect $name/${filter_name}_${i}/m_axis_data_tdata $name/out_mux_${i}/data_in_1 + + ad_connect $name/valid_out_$i $name/out_mux_${i}/valid_out + ad_connect $name/enable_out_$i $name/out_mux_${i}/enable_out + ad_connect $name/data_out_$i $name/out_mux_${i}/data_out + + ad_connect $name/out_mux_${i}/select_path $name/active + } +} + + +################################################################################################### +################################################################################################### +## +# ad_add_interpolation_filter - Creates a subsystem based on the Xilinx fir_compiler IP. +# \param[name] - Subsystem name +# \param[filter_rate] - Filter rate. E.g., 8 +# \param[n_chan] - Number of channels to filter +# \param[parallel_paths] - Number of paralell paths. For scenarios where +# the sampling rate is x times the core clock. +# \param[core_clk_mhz] - Core clock in MHz +# \param[sampl_freq_mhz] - Sampling frequency in MHz +proc ad_add_interpolation_filter {name filter_rate n_chan parallel_paths \ + core_clk_mhz sampl_freq_mhz coe_file} { + global ad_hdl_dir + + create_bd_cell -type hier $name + set filter_name "fir_interpolation" + + add_files -norecurse $ad_hdl_dir/library/common/ad_bus_mux.v + add_files -norecurse $ad_hdl_dir/library/common/util_pulse_gen.v + + create_bd_pin -dir I $name/aclk + create_bd_pin -dir I $name/active + + # Create pulse generator for ready/valid signals - This is required because + # there is only one clock domain for the slave and master data paths. + # The generator will give a 1 clock cycle pulse every N clock cycle periods. + # N = data rate. + create_bd_cell -type module -reference util_pulse_gen $name/rate_gen + set_property -dict [list \ + CONFIG.PULSE_WIDTH {1} \ + CONFIG.PULSE_PERIOD [expr $filter_rate -1]] [get_bd_cells $name/rate_gen] + + ad_connect $name/aclk $name/rate_gen/clk + ad_connect $name/rate_gen/pulse_width GND + ad_connect $name/rate_gen/pulse_period GND + ad_connect $name/rate_gen/load_config GND + ad_connect $name/active $name/rate_gen/rstn + + # add filter instances for n channels + for {set i 0} {$i < $n_chan} {incr i} { + ad_ip_instance fir_compiler $name/${filter_name}_${i} [ list \ + Decimation_Rate 1 \ + Filter_Type "Interpolation" \ + Interpolation_Rate $filter_rate \ + Number_Paths $parallel_paths \ + Clock_Frequency $core_clk_mhz \ + Sample_Frequency $sampl_freq_mhz \ + CoefficientSource COE_File \ + Coefficient_File $coe_file \ + Coefficient_Fractional_Bits 0 \ + Data_Fractional_Bits 15 \ + Coefficient_Sets 1 \ + Coefficient_Sign Signed \ + Coefficient_Structure Inferred \ + Coefficient_Width 16 \ + ColumnConfig 5 \ + Filter_Architecture Systolic_Multiply_Accumulate \ + Number_Channels 1 \ + Output_Rounding_Mode Symmetric_Rounding_to_Zero \ + Output_Width 16 \ + Quantization Integer_Coefficients \ + RateSpecification Frequency_Specification \ + Zero_Pack_Factor 1 + ] + + ad_connect $name/aclk $name/${filter_name}_${i}/aclk + + create_bd_pin -dir I $name/dac_valid_$i + create_bd_pin -dir I $name/dac_enable_$i + create_bd_pin -dir O $name/valid_out_$i + create_bd_pin -dir O $name/enable_out_$i + create_bd_pin -dir I -from [expr 16*$parallel_paths-1] -to 0 $name/data_in_$i + create_bd_pin -dir O -from [expr 16*$parallel_paths-1] -to 0 $name/data_out_$i + + ad_ip_instance util_vector_logic $name/logic_and_$i [list \ + C_SIZE 1] + + create_bd_cell -type module -reference ad_bus_mux $name/out_mux_$i + set_property -dict [list \ + CONFIG.DATA_WIDTH [expr 16 * $parallel_paths]] [get_bd_cells $name/out_mux_$i] + + ad_connect $name/rate_gen/pulse $name/logic_and_$i/Op1 + ad_connect $name/dac_valid_$i $name/logic_and_$i/Op2 + ad_connect $name/logic_and_$i/Res $name/${filter_name}_${i}/s_axis_data_tvalid + ad_connect $name/${filter_name}_${i}/s_axis_data_tdata $name/data_in_$i + + ad_connect $name/rate_gen/pulse $name/out_mux_${i}/valid_in_1 + ad_connect $name/dac_enable_$i $name/out_mux_${i}/enable_in_1 + ad_connect $name/${filter_name}_${i}/m_axis_data_tdata $name/out_mux_${i}/data_in_1 + + ad_connect $name/dac_valid_$i $name/out_mux_${i}/valid_in_0 + ad_connect $name/dac_enable_$i $name/out_mux_${i}/enable_in_0 + ad_connect $name/data_in_$i $name/out_mux_${i}/data_in_0 + + ad_connect $name/out_mux_${i}/valid_out $name/valid_out_$i + ad_connect $name/out_mux_${i}/enable_out $name/enable_out_$i + ad_connect $name/out_mux_${i}/data_out $name/data_out_$i + + ad_connect $name/active $name/out_mux_${i}/select_path + } +} + diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl index 842b47f5d..f8f151156 100644 --- a/projects/scripts/adi_board.tcl +++ b/projects/scripts/adi_board.tcl @@ -335,6 +335,9 @@ proc ad_xcvrpll {m_src m_dst} { } } +################################################################################################### +################################################################################################### + ## Create an memory mapped interface connection to a MIG or PS7/8 IP, using a # HP0 high speed interface in case of PSx. #