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jesd204: tx_ctrl: Fix status_sync assignment 

The SYNC signal that gets reported through the status interface should be
the output (second stage) of the synchronizer circuit.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-07-17 15:15:56 +02:00
parent 1f2e189ff2
commit 369fe69d34
1 changed files with 1 additions and 1 deletions
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2
library/jesd204/jesd204_tx/tx_ctrl.v
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@ -94,7 +94,7 @@ always @(posedge clk) begin
sync_sync <= {sync_sync[0],sync}; sync_sync <= {sync_sync[0],sync};
end end
assign status_sync = sync_sync; assign status_sync = sync_sync[1];
always @(posedge clk) begin always @(posedge clk) begin
if (reset == 1'b1) begin if (reset == 1'b1) begin