jesd204: tx_ctrl: Fix status_sync assignment

The SYNC signal that gets reported through the status interface should be
the output (second stage) of the synchronizer circuit.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

library/jesd204/jesd204_tx/tx_ctrl.v

@@ -94,7 +94,7 @@ always @(posedge clk) begin
   sync_sync <= {sync_sync[0],sync};
 end
 
-assign status_sync = sync_sync;
+assign status_sync = sync_sync[1];
 
 always @(posedge clk) begin
   if (reset == 1'b1) begin