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ad_ip_jesd204_tpl_dac: Add Intel Platform Designer GUI integration 

The ad_ip_jesd204_tpl_dac currently is only instantiated as a submodule by
other cores like the axi_ad9144 or axi_ad9152. These cores typically only
support one specific framer configuration.

In an effort to allow more framer configurations to be used the core is
re-worked, so it can be instantiated standalone.

As part of this effort provide GUI integration for Intel Platform Designer
(previously known as Qsys) where users can instantiate and configure the
core.

For this group the configuration parameters by function, provide
descriptive label and a list of allowed values for parameter validation.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2018-08-03 08:42:01 +02:00 committed by István Csomortáni
parent 07ca770607
commit 362ad79e05
1 changed files with 62 additions and 4 deletions
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66
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl
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@ -25,7 +25,8 @@ package require qsys
source ../../scripts/adi_env.tcl
source ../../scripts/adi_ip_alt.tcl
ad_ip_create ad_ip_jesd204_tpl_dac {ADI JESD204 Transport DAC Layer} p_ad_ip_jesd204_tpl_dac_elab
ad_ip_create ad_ip_jesd204_tpl_dac "JESD204 Transport Layer for DACs" p_ad_ip_jesd204_tpl_dac_elab
set_module_property VALIDATION_CALLBACK p_ad_ip_jesd204_tpl_dac_validate
ad_ip_files ad_ip_jesd204_tpl_dac [list \
$ad_hdl_dir/library/altera/common/ad_mul.v \
$ad_hdl_dir/library/common/ad_dds_sine.v \
@ -57,9 +58,55 @@ ad_ip_files ad_ip_jesd204_tpl_dac [list \
# parameters
ad_ip_parameter ID INTEGER 0
ad_ip_parameter NUM_CHANNELS INTEGER 1
ad_ip_parameter NUM_LANES INTEGER 1
set group "General Configuration"
ad_ip_parameter ID INTEGER 0 true [list \
DISPLAY_NAME "Core ID" \
GROUP $group \
]
set group "JESD204 Framer Configuration"
ad_ip_parameter NUM_LANES INTEGER 1 true [list \
DISPLAY_NAME "Number of Lanes (L)" \
DISPLAY_UNITS "lanes" \
ALLOWED_RANGES {1 2 3 4 8} \
GROUP $group \
]
ad_ip_parameter NUM_CHANNELS INTEGER 1 true [list \
DISPLAY_NAME "Number of Converters (M)" \
DISPLAY_UNITS "converters" \
ALLOWED_RANGES {1 2 4 6 8} \
GROUP $group \
]
set group "Datapath Configuration"
ad_ip_parameter DATAPATH_DISABLE boolean 0 true [list \
DISPLAY_NAME "Disable Datapath" \
GROUP $group \
]
ad_ip_parameter DDS_TYPE INTEGER 1 true [list \
DISPLAY_NAME "DDS Type" \
ALLOWED_RANGES {"0:Polynominal" "1:CORDIC"} \
GROUP $group \
]
ad_ip_parameter DDS_CORDIC_DW INTEGER 16 true [list \
DISPLAY_NAME "CORDIC DDS Data Width" \
ALLOWED_RANGES {8:20} \
UNITS bits \
GROUP $group \
]
ad_ip_parameter DDS_CORDIC_PHASE_DW INTEGER 16 true [list \
DISPLAY_NAME "CORDIC DDS Phase Width" \
ALLOWED_RANGES {8:20} \
UNITS bits \
GROUP $group \
]
# axi4 slave
@ -70,6 +117,17 @@ ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
add_interface link_clk clock end
add_interface_port link_clk link_clk clk Input 1
# validate
proc p_ad_ip_jesd204_tpl_dac_validate {} {
set data_path_enabled [expr ![get_parameter_value DATAPATH_DISABLE]]
set cordic_enabled [expr $data_path_enabled && [get_parameter_value DDS_TYPE] == 1]
set_parameter_property DDS_TYPE ENABLED $data_path_enabled
set_parameter_property DDS_CORDIC_DW ENABLED $cordic_enabled
set_parameter_property DDS_CORDIC_PHASE_DW ENABLED $cordic_enabled
}
# elaborate
proc p_ad_ip_jesd204_tpl_dac_elab {} {