initial checkin
Rejeesh Kutty
parent
82115b138e
commit
360f10395a
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@ -0,0 +1,468 @@
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set sys_rst [create_bd_port -dir I -type rst sys_rst]
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set sys_clk_p [create_bd_port -dir I sys_clk_p]
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set sys_clk_n [create_bd_port -dir I sys_clk_n]
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set fan_pwm [create_bd_port -dir O fan_pwm]
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set ddr3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3]
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set mgt_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 mgt_clk]
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set sfp [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:sfp_rtl:1.0 sfp]
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set gpio_sw [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_sw]
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set gpio_led [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_led]
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set gpio_lcd [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_lcd]
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set iic_rstn [create_bd_port -dir O iic_rstn]
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set iic_main [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main]
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set uart_sin [create_bd_port -dir I uart_sin]
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set uart_sout [create_bd_port -dir O uart_sout]
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set hdmi_out_clk [create_bd_port -dir O hdmi_out_clk]
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set hdmi_hsync [create_bd_port -dir O hdmi_hsync]
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set hdmi_vsync [create_bd_port -dir O hdmi_vsync]
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set hdmi_data_e [create_bd_port -dir O hdmi_data_e]
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set hdmi_data [create_bd_port -dir O -from 23 -to 0 hdmi_data]
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# spdif audio
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set spdif [create_bd_port -dir O spdif]
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set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] $sys_rst
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# instance: microblaze - processor
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set microblaze_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.2 microblaze_1]
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set_property -dict [list CONFIG.C_FAULT_TOLERANT {0}] $microblaze_1
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set_property -dict [list CONFIG.C_D_AXI {1}] $microblaze_1
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set_property -dict [list CONFIG.C_D_LMB {1}] $microblaze_1
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set_property -dict [list CONFIG.C_I_LMB {1}] $microblaze_1
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set_property -dict [list CONFIG.C_DEBUG_ENABLED {1}] $microblaze_1
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set_property -dict [list CONFIG.C_USE_ICACHE {1}] $microblaze_1
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set_property -dict [list CONFIG.C_ICACHE_LINE_LEN {8}] $microblaze_1
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set_property -dict [list CONFIG.C_ICACHE_ALWAYS_USED {1}] $microblaze_1
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set_property -dict [list CONFIG.C_ICACHE_FORCE_TAG_LUTRAM {1}] $microblaze_1
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set_property -dict [list CONFIG.C_USE_DCACHE {1}] $microblaze_1
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set_property -dict [list CONFIG.C_DCACHE_LINE_LEN {8}] $microblaze_1
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set_property -dict [list CONFIG.C_DCACHE_ALWAYS_USED {1}] $microblaze_1
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set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $microblaze_1
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set_property -dict [list CONFIG.C_ICACHE_HIGHADDR {0xBFFFFFFF}] $microblaze_1
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set_property -dict [list CONFIG.C_ICACHE_BASEADDR {0x80000000}] $microblaze_1
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set_property -dict [list CONFIG.C_DCACHE_HIGHADDR {0xBFFFFFFF}] $microblaze_1
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set_property -dict [list CONFIG.C_DCACHE_BASEADDR {0x80000000}] $microblaze_1
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# instance: microblaze - local memory & bus
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set dlmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb]
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set ilmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb]
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set dlmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_cntlr]
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set_property -dict [list CONFIG.C_ECC {0}] $dlmb_cntlr
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set ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_cntlr]
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set_property -dict [list CONFIG.C_ECC {0}] $ilmb_cntlr
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set lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.1 lmb_bram]
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set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $lmb_bram
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# instance: microblaze- mdm
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set mb_debug [create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.0 mb_debug]
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set_property -dict [list CONFIG.C_USE_UART {1}] $mb_debug
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# instance: system reset/clocks
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set proc_sys_reset_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1]
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set proc_sys_clock_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 proc_sys_clock_1]
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set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000}] $proc_sys_clock_1
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set_property -dict [list CONFIG.PRIM_SOURCE {Global_buffer}] $proc_sys_clock_1
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set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200}] $proc_sys_clock_1
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set_property -dict [list CONFIG.USE_RESET {false}] $proc_sys_clock_1
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set proc_const_vcc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 proc_const_vcc_1]
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# instance: ddr (mig)
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set axi_ddr_cntrl_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.0 axi_ddr_cntrl_1]
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set axi_ddr_cntrl_1_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl_1]]]
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file copy -force ../../scripts/ac701_system_mig.prj "$axi_ddr_cntrl_1_dir/"
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set_property -dict [list CONFIG.XML_INPUT_FILE {ac701_system_mig.prj}] $axi_ddr_cntrl_1
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set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {Custom}] $axi_ddr_cntrl_1
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# instance: axi interconnect (lite)
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set axi_interconnect_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_1]
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set_property -dict [list CONFIG.NUM_MI {14}] $axi_interconnect_1
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# instance: axi interconnect
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set axi_interconnect_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_2]
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set_property -dict [list CONFIG.NUM_SI {8}] $axi_interconnect_2
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_interconnect_2
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set_property -dict [list CONFIG.ENABLE_ADVANCED_OPTIONS {1}] $axi_interconnect_2
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set_property -dict [list CONFIG.XBAR_DATA_WIDTH {512}] $axi_interconnect_2
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# instance: default peripherals
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set axi_ethernet_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:6.0 axi_ethernet_1]
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set_property -dict [list CONFIG.PHY_TYPE {1000BaseX}] $axi_ethernet_1
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set_property -dict [list CONFIG.Statistics_Counters {true}] $axi_ethernet_1
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set_property -dict [list CONFIG.MCAST_EXTEND {true}] $axi_ethernet_1
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set_property -dict [list CONFIG.TXVLAN_TRAN {true}] $axi_ethernet_1
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set_property -dict [list CONFIG.TXVLAN_TAG {true}] $axi_ethernet_1
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set_property -dict [list CONFIG.TXVLAN_STRP {true}] $axi_ethernet_1
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set_property -dict [list CONFIG.RXVLAN_TRAN {true}] $axi_ethernet_1
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set_property -dict [list CONFIG.RXVLAN_TAG {true}] $axi_ethernet_1
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set_property -dict [list CONFIG.RXVLAN_STRP {true}] $axi_ethernet_1
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set_property -dict [list CONFIG.TXMEM {32k}] $axi_ethernet_1
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set_property -dict [list CONFIG.RXMEM {32k}] $axi_ethernet_1
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set axi_ethernet_dma_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_dma_1]
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set_property -dict [list CONFIG.c_include_mm2s_dre {1}] $axi_ethernet_dma_1
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set_property -dict [list CONFIG.c_sg_use_stsapp_length {1}] $axi_ethernet_dma_1
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set_property -dict [list CONFIG.c_include_s2mm_dre {1}] $axi_ethernet_dma_1
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set axi_iic_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_1]
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set axi_uart_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart_1]
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set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart_1
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set axi_timer_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_1]
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set axi_gpio_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1]
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set_property -dict [list CONFIG.C_GPIO_WIDTH {7}] $axi_gpio_1
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set_property -dict [list CONFIG.C_ALL_OUTPUTS {1}] $axi_gpio_1
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set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_1
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set axi_gpio_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2]
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set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio_2
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set_property -dict [list CONFIG.C_GPIO_WIDTH {9}] $axi_gpio_2
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set_property -dict [list CONFIG.C_GPIO2_WIDTH {4}] $axi_gpio_2
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set_property -dict [list CONFIG.C_ALL_INPUTS {1}] $axi_gpio_2
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set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_2
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set_property -dict [list CONFIG.C_ALL_OUTPUTS_2 {1}] $axi_gpio_2
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# instance: interrupt
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set axi_intc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_1]
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set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc_1
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set concat_intc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 concat_intc_1]
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set_property -dict [list CONFIG.NUM_PORTS {10}] $concat_intc_1
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# hdmi peripherals
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set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
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set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
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set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.1 axi_hdmi_dma]
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set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
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set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
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set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
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# audio peripherals
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set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
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set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
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set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
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set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
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set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core
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set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
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set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core
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set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core
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set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_spdif_tx_dma]
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set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma
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set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_spdif_tx_dma
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# connections
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connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mb_debug/Debug_SYS_Rst]
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connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins proc_sys_reset_1/mb_debug_sys_rst]
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connect_bd_net -net proc_sys_reset_1_mb_reset [get_bd_pins proc_sys_reset_1/mb_reset]
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connect_bd_net -net proc_sys_reset_1_mb_reset [get_bd_pins microblaze_1/Reset]
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connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins proc_sys_reset_1/bus_struct_reset]
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connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins dlmb/SYS_Rst]
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connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins ilmb/SYS_Rst]
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connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins dlmb_cntlr/LMB_Rst]
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connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins ilmb_cntlr/LMB_Rst]
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# microblaze local memory
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connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb [get_bd_intf_pins dlmb/LMB_Sl_0] [get_bd_intf_pins dlmb_cntlr/SLMB]
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connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb [get_bd_intf_pins ilmb/LMB_Sl_0] [get_bd_intf_pins ilmb_cntlr/SLMB]
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connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb_bram [get_bd_intf_pins dlmb_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA]
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connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb_bram [get_bd_intf_pins ilmb_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB]
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connect_bd_intf_net -intf_net microblaze_1_dlmb [get_bd_intf_pins microblaze_1/DLMB] [get_bd_intf_pins dlmb/LMB_M]
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connect_bd_intf_net -intf_net microblaze_1_ilmb [get_bd_intf_pins microblaze_1/ILMB] [get_bd_intf_pins ilmb/LMB_M]
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# microblaze debug & interrupt
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connect_bd_intf_net -intf_net microblaze_1_debug [get_bd_intf_pins mb_debug/MBDEBUG_0] [get_bd_intf_pins microblaze_1/DEBUG]
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connect_bd_net -net concat_intc_1_intr [get_bd_pins concat_intc_1/dout] [get_bd_pins axi_intc_1/intr]
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connect_bd_intf_net -intf_net microblaze_1_interrupt [get_bd_intf_pins axi_intc_1/interrupt] [get_bd_intf_pins microblaze_1/INTERRUPT]
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# defaults (peripherals)
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connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
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connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
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connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
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connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins proc_sys_reset_1/peripheral_aresetn]
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connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins mb_debug/S_AXI_ARESETN]
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connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_ddr_cntrl_1/aresetn]
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connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_ethernet_1/s_axi_lite_resetn] [get_bd_pins proc_sys_reset_1/peripheral_aresetn]
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connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_uart_1/s_axi_aresetn]
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connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_timer_1/s_axi_aresetn]
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connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_intc_1/s_axi_aresetn]
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connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_gpio_1/s_axi_aresetn]
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connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_gpio_2/s_axi_aresetn]
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connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_iic_1/s_axi_aresetn]
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||||||
|
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_ethernet_dma_1/axi_resetn]
|
||||||
|
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins proc_sys_clock_1/clk_in1]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_1/ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins proc_sys_reset_1/slowest_sync_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins microblaze_1/Clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins mb_debug/S_AXI_ACLK]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins dlmb/LMB_Clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins ilmb/LMB_Clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins dlmb_cntlr/LMB_Clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins ilmb_cntlr/LMB_Clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_1/s_axi_lite_clk] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_uart_1/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_timer_1/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_intc_1/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_gpio_1/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_gpio_2/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_1/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_1/axis_clk] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_dma_1/m_axi_sg_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_dma_1/m_axi_mm2s_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_dma_1/m_axi_s2mm_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_dma_1/s_axi_lite_aclk]
|
||||||
|
|
||||||
|
connect_bd_net -net sys_200m_clk [get_bd_pins proc_sys_clock_1/clk_out1]
|
||||||
|
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ethernet_1/ref_clk] [get_bd_pins proc_sys_clock_1/clk_out1]
|
||||||
|
connect_bd_net -net sys_200m_clk [get_bd_pins axi_interconnect_2/ACLK] [get_bd_pins proc_sys_clock_1/clk_out1]
|
||||||
|
|
||||||
|
# defaults (interconnect - processor)
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_1_s00 [get_bd_intf_pins axi_interconnect_1/S00_AXI] [get_bd_intf_pins microblaze_1/M_AXI_DP]
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_1_m00 [get_bd_intf_pins axi_interconnect_1/M00_AXI] [get_bd_intf_pins mb_debug/S_AXI]
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_1_m01 [get_bd_intf_pins axi_interconnect_1/M01_AXI] [get_bd_intf_pins axi_ethernet_1/s_axi]
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_1_m02 [get_bd_intf_pins axi_interconnect_1/M02_AXI] [get_bd_intf_pins axi_uart_1/s_axi]
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_1_m03 [get_bd_intf_pins axi_interconnect_1/M03_AXI] [get_bd_intf_pins axi_timer_1/s_axi]
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_1_m04 [get_bd_intf_pins axi_interconnect_1/M04_AXI] [get_bd_intf_pins axi_intc_1/s_axi]
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_1_m05 [get_bd_intf_pins axi_interconnect_1/M05_AXI] [get_bd_intf_pins axi_gpio_1/s_axi]
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_1_m06 [get_bd_intf_pins axi_interconnect_1/M06_AXI] [get_bd_intf_pins axi_gpio_2/s_axi]
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_1_m07 [get_bd_intf_pins axi_interconnect_1/M07_AXI] [get_bd_intf_pins axi_iic_1/s_axi]
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_1_m13 [get_bd_intf_pins axi_interconnect_1/M13_AXI] [get_bd_intf_pins axi_ethernet_dma_1/S_AXI_LITE]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/S00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M01_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M02_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M03_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M04_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M05_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M06_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M07_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M13_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_1/S00_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_1/M00_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_1/M01_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_1/M02_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_1/M03_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_1/M04_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_1/M05_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_1/M06_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_1/M07_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_1/M13_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
|
||||||
|
# defaults (interconnect - memory)
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_2_m00 [get_bd_intf_pins axi_interconnect_2/M00_AXI] [get_bd_intf_pins axi_ddr_cntrl_1/S_AXI]
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_2_s00 [get_bd_intf_pins axi_interconnect_2/S00_AXI] [get_bd_intf_pins microblaze_1/M_AXI_DC]
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_2_s01 [get_bd_intf_pins axi_interconnect_2/S01_AXI] [get_bd_intf_pins microblaze_1/M_AXI_IC]
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_2_s05 [get_bd_intf_pins axi_interconnect_2/S05_AXI] [get_bd_intf_pins axi_ethernet_dma_1/M_AXI_SG]
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_2_s06 [get_bd_intf_pins axi_interconnect_2/S06_AXI] [get_bd_intf_pins axi_ethernet_dma_1/M_AXI_MM2S]
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_2_s07 [get_bd_intf_pins axi_interconnect_2/S07_AXI] [get_bd_intf_pins axi_ethernet_dma_1/M_AXI_S2MM]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/M00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S01_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S05_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S06_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S07_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_2/M00_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_2/S00_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_2/S01_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_2/S05_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_2/S06_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_2/S07_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
|
||||||
|
# ethernet & ethernet dma
|
||||||
|
|
||||||
|
connect_bd_net -net axi_ethernet_dma_1_txd_rstn [get_bd_pins axi_ethernet_1/axi_txd_arstn] [get_bd_pins axi_ethernet_dma_1/mm2s_prmry_reset_out_n]
|
||||||
|
connect_bd_net -net axi_ethernet_dma_1_txc_rstn [get_bd_pins axi_ethernet_1/axi_txc_arstn] [get_bd_pins axi_ethernet_dma_1/mm2s_cntrl_reset_out_n]
|
||||||
|
connect_bd_net -net axi_ethernet_dma_1_rxd_rstn [get_bd_pins axi_ethernet_1/axi_rxd_arstn] [get_bd_pins axi_ethernet_dma_1/s2mm_prmry_reset_out_n]
|
||||||
|
connect_bd_net -net axi_ethernet_dma_1_rxs_rstn [get_bd_pins axi_ethernet_1/axi_rxs_arstn] [get_bd_pins axi_ethernet_dma_1/s2mm_sts_reset_out_n]
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net axi_ethernet_dma_1_txd [get_bd_intf_pins axi_ethernet_1/s_axis_txd] [get_bd_intf_pins axi_ethernet_dma_1/M_AXIS_MM2S]
|
||||||
|
connect_bd_intf_net -intf_net axi_ethernet_dma_1_txc [get_bd_intf_pins axi_ethernet_1/s_axis_txc] [get_bd_intf_pins axi_ethernet_dma_1/M_AXIS_CNTRL]
|
||||||
|
connect_bd_intf_net -intf_net axi_ethernet_dma_1_rxd [get_bd_intf_pins axi_ethernet_1/m_axis_rxd] [get_bd_intf_pins axi_ethernet_dma_1/S_AXIS_S2MM]
|
||||||
|
connect_bd_intf_net -intf_net axi_ethernet_dma_1_rxs [get_bd_intf_pins axi_ethernet_1/m_axis_rxs] [get_bd_intf_pins axi_ethernet_dma_1/S_AXIS_STS]
|
||||||
|
|
||||||
|
# defaults (interrupts)
|
||||||
|
|
||||||
|
connect_bd_net -net concat_intc_1_intr_00 [get_bd_pins concat_intc_1/In0] [get_bd_pins axi_timer_1/interrupt]
|
||||||
|
connect_bd_net -net concat_intc_1_intr_01 [get_bd_pins concat_intc_1/In1] [get_bd_pins axi_ethernet_1/interrupt]
|
||||||
|
connect_bd_net -net concat_intc_1_intr_02 [get_bd_pins concat_intc_1/In2] [get_bd_pins axi_uart_1/interrupt]
|
||||||
|
connect_bd_net -net concat_intc_1_intr_03 [get_bd_pins concat_intc_1/In3] [get_bd_pins axi_gpio_1/ip2intc_irpt]
|
||||||
|
connect_bd_net -net concat_intc_1_intr_04 [get_bd_pins concat_intc_1/In4] [get_bd_pins axi_gpio_2/ip2intc_irpt]
|
||||||
|
connect_bd_net -net concat_intc_1_intr_05 [get_bd_pins concat_intc_1/In5] [get_bd_pins axi_iic_1/iic2intc_irpt]
|
||||||
|
connect_bd_net -net concat_intc_1_intr_08 [get_bd_pins concat_intc_1/In8] [get_bd_pins axi_ethernet_dma_1/mm2s_introut]
|
||||||
|
connect_bd_net -net concat_intc_1_intr_09 [get_bd_pins concat_intc_1/In9] [get_bd_pins axi_ethernet_dma_1/s2mm_introut]
|
||||||
|
|
||||||
|
# defaults (external interface)
|
||||||
|
|
||||||
|
connect_bd_net -net proc_const_vcc_1_vcc [get_bd_pins proc_const_vcc_1/const] [get_bd_ports fan_pwm] [get_bd_pins axi_ethernet_1/signal_detect]
|
||||||
|
connect_bd_net -net sys_rst_s [get_bd_ports sys_rst]
|
||||||
|
connect_bd_net -net sys_rst_s [get_bd_pins proc_sys_reset_1/ext_reset_in]
|
||||||
|
connect_bd_net -net sys_rst_s [get_bd_pins axi_ddr_cntrl_1/sys_rst]
|
||||||
|
|
||||||
|
connect_bd_net -net sys_clk_p_s [get_bd_ports sys_clk_p] [get_bd_pins axi_ddr_cntrl_1/sys_clk_p]
|
||||||
|
connect_bd_net -net sys_clk_n_s [get_bd_ports sys_clk_n] [get_bd_pins axi_ddr_cntrl_1/sys_clk_n]
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net axi_ddr_cntrl_1_ddr3 [get_bd_intf_ports ddr3] [get_bd_intf_pins axi_ddr_cntrl_1/DDR3]
|
||||||
|
connect_bd_intf_net -intf_net axi_ethernet_1_mgt_clk [get_bd_intf_ports mgt_clk] [get_bd_intf_pins axi_ethernet_1/mgt_clk]
|
||||||
|
connect_bd_intf_net -intf_net axi_ethernet_1_sfp [get_bd_intf_ports sfp] [get_bd_intf_pins axi_ethernet_1/sfp]
|
||||||
|
|
||||||
|
connect_bd_net -net axi_uart_1_sin [get_bd_ports uart_sin] [get_bd_pins axi_uart_1/rx]
|
||||||
|
connect_bd_net -net axi_uart_1_sout [get_bd_ports uart_sout] [get_bd_pins axi_uart_1/tx]
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net axi_gpio_1_gpio [get_bd_intf_ports gpio_lcd] [get_bd_intf_pins axi_gpio_1/gpio]
|
||||||
|
connect_bd_intf_net -intf_net axi_gpio_2_gpio [get_bd_intf_ports gpio_sw] [get_bd_intf_pins axi_gpio_2/gpio]
|
||||||
|
connect_bd_intf_net -intf_net axi_gpio_2_gpio2 [get_bd_intf_ports gpio_led] [get_bd_intf_pins axi_gpio_2/gpio2]
|
||||||
|
|
||||||
|
connect_bd_net -net axi_iic_1_rstn [get_bd_ports iic_rstn] [get_bd_pins axi_iic_1/gpo]
|
||||||
|
connect_bd_intf_net -intf_net axi_iic_1_iic [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_1/iic]
|
||||||
|
|
||||||
|
# hdmi peripherals
|
||||||
|
|
||||||
|
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_hdmi_dma/axi_resetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_hdmi_core/s_axi_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/drp_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk]
|
||||||
|
connect_bd_net -net sys_200m_clk [get_bd_pins axi_hdmi_clkgen/clk]
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_1_m08 [get_bd_intf_pins axi_interconnect_1/M08_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi]
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_1_m09 [get_bd_intf_pins axi_interconnect_1/M09_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE]
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_1_m10 [get_bd_intf_pins axi_interconnect_1/M10_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M08_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M09_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M10_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_1/M08_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_1/M09_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_1/M10_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_2_s02 [get_bd_intf_pins axi_interconnect_2/S02_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S02_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_2/S02_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
|
||||||
|
connect_bd_net -net concat_intc_1_intr_06 [get_bd_pins concat_intc_1/In6] [get_bd_pins axi_hdmi_dma/mm2s_introut]
|
||||||
|
|
||||||
|
connect_bd_net -net axi_hdmi_core_hdmi_out_clk [get_bd_ports hdmi_out_clk] [get_bd_pins axi_hdmi_core/hdmi_out_clk]
|
||||||
|
connect_bd_net -net axi_hdmi_core_hdmi_hsync [get_bd_ports hdmi_hsync] [get_bd_pins axi_hdmi_core/hdmi_24_hsync]
|
||||||
|
connect_bd_net -net axi_hdmi_core_hdmi_vsync [get_bd_ports hdmi_vsync] [get_bd_pins axi_hdmi_core/hdmi_24_vsync]
|
||||||
|
connect_bd_net -net axi_hdmi_core_hdmi_data_e [get_bd_ports hdmi_data_e] [get_bd_pins axi_hdmi_core/hdmi_24_data_e]
|
||||||
|
connect_bd_net -net axi_hdmi_core_hdmi_data [get_bd_ports hdmi_data] [get_bd_pins axi_hdmi_core/hdmi_24_data]
|
||||||
|
|
||||||
|
connect_bd_net -net axi_hdmi_clkgen_clk [get_bd_pins axi_hdmi_clkgen/clk_0] [get_bd_pins axi_hdmi_core/hdmi_clk]
|
||||||
|
connect_bd_net -net axi_hdmi_core_valid [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tvalid] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tvalid]
|
||||||
|
connect_bd_net -net axi_hdmi_core_data [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tdata] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tdata]
|
||||||
|
connect_bd_net -net axi_hdmi_core_keep [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tkeep] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tkeep]
|
||||||
|
connect_bd_net -net axi_hdmi_core_last [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tlast] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tlast]
|
||||||
|
connect_bd_net -net axi_hdmi_core_ready [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tready] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tready]
|
||||||
|
connect_bd_net -net axi_hdmi_core_fsync [get_bd_pins axi_hdmi_dma/mm2s_fsync] [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync]
|
||||||
|
connect_bd_net -net axi_hdmi_core_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret]
|
||||||
|
|
||||||
|
# spdif audio
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_1_m11 [get_bd_intf_pins axi_interconnect_1/M11_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi]
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_1_m12 [get_bd_intf_pins axi_interconnect_1/M12_AXI] [get_bd_intf_pins axi_spdif_tx_dma/S_AXI_LITE]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M11_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M12_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_spdif_tx_core/S_AXIS_ARESETN]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_spdif_tx_dma/axi_resetn]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_1/M11_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_1/M12_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/s_axi_lite_aclk]
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_2_s03 [get_bd_intf_pins axi_interconnect_2/S03_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_SG]
|
||||||
|
connect_bd_intf_net -intf_net axi_interconnect_2_s04 [get_bd_intf_pins axi_interconnect_2/S04_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_MM2S]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S03_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S04_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_2/S03_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_interconnect_2/S04_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXIS_ACLK]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/m_axi_mm2s_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/m_axi_sg_aclk]
|
||||||
|
|
||||||
|
connect_bd_net -net axi_spdif_tx_dma_mm2s_valid [get_bd_pins axi_spdif_tx_core/S_AXIS_TVALID] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tvalid]
|
||||||
|
connect_bd_net -net axi_spdif_tx_dma_mm2s_data [get_bd_pins axi_spdif_tx_core/S_AXIS_TDATA] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tdata]
|
||||||
|
connect_bd_net -net axi_spdif_tx_dma_mm2s_last [get_bd_pins axi_spdif_tx_core/S_AXIS_TLAST] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tlast]
|
||||||
|
connect_bd_net -net axi_spdif_tx_dma_mm2s_ready [get_bd_pins axi_spdif_tx_core/S_AXIS_TREADY] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tready]
|
||||||
|
|
||||||
|
connect_bd_net -net concat_intc_1_intr_07 [get_bd_pins concat_intc_1/In7] [get_bd_pins axi_spdif_tx_dma/mm2s_introut]
|
||||||
|
|
||||||
|
connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1]
|
||||||
|
connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk]
|
||||||
|
connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o]
|
||||||
|
|
||||||
|
# address mapping
|
||||||
|
|
||||||
|
create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs dlmb_cntlr/SLMB/Mem] SEG_data_dlmb_cntlr
|
||||||
|
create_bd_addr_seg -range 0x00001000 -offset 0x41400000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs mb_debug/S_AXI/Reg] SEG_data_mb_debug
|
||||||
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_data_ddr_cntrl_1
|
||||||
|
create_bd_addr_seg -range 0x00040000 -offset 0x40E00000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_ethernet_1/eth_buf/S_AXI/REG] SEG_data_ethernetlite_1
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x40010000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_gpio_1/s_axi/Reg] SEG_data_gpio_1
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x40020000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_gpio_2/s_axi/Reg] SEG_data_gpio_2
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x41600000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_iic_1/s_axi/Reg] SEG_data_iic_1
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_intc_1/s_axi/Reg] SEG_data_intc_1
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x41C00000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_timer_1/s_axi/Reg] SEG_data_timer_1
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x40600000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_uart_1/s_axi/Reg] SEG_data_uart_1
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x41E10000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_ethernet_dma_1/S_AXI_LITE/Reg] SEG_data_ethernet_dma_1
|
||||||
|
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x79000000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite] SEG_data_hdmi_clkgen
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg] SEG_data_hdmi_dma
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite] SEG_data_hdmi_core
|
||||||
|
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0] SEG_data_spdif_tx_core
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x41E00000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_spdif_tx_dma/S_AXI_LITE/Reg] SEG_data_spdif_tx_dma
|
||||||
|
|
||||||
|
create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces microblaze_1/Instruction] [get_bd_addr_segs ilmb_cntlr/SLMB/Mem] SEG_instr_ilmb_cntlr
|
||||||
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_1/Instruction] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_instr_ddr_cntrl_1
|
||||||
|
|
||||||
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_mem_ddr_cntrl_1
|
||||||
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_axi_ddr_cntrl_1
|
||||||
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_axi_ddr_cntrl_1
|
||||||
|
|
||||||
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma_1/Data_SG] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_axi_ddr_cntrl_1
|
||||||
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma_1/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_axi_ddr_cntrl_1
|
||||||
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma_1/Data_S2MM] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_axi_ddr_cntrl_1
|
||||||
|
|
||||||
|
create_bd_addr_seg -range 0x00001000 -offset 0x00000000 [get_bd_addr_spaces axi_ethernet_1/eth_buf/S_AXI_2TEMAC] [get_bd_addr_segs axi_ethernet_1/eth_mac/s_axi/Reg] SEG_eth_mac_reg
|
||||||
|
|
@ -0,0 +1,112 @@
|
||||||
|
|
||||||
|
# constraints
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS15} [get_ports sys_rst]
|
||||||
|
|
||||||
|
# clocks
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN R3 IOSTANDARD DIFF_SSTL15} [get_ports sys_clk_p]
|
||||||
|
set_property -dict {PACKAGE_PIN P3 IOSTANDARD DIFF_SSTL15} [get_ports sys_clk_n]
|
||||||
|
|
||||||
|
create_clock -name sys_clk -period 5.00 [get_ports sys_clk_p]
|
||||||
|
|
||||||
|
# ethernet
|
||||||
|
|
||||||
|
set_property PACKAGE_PIN AC10 [get_ports sfp_txp]
|
||||||
|
set_property PACKAGE_PIN AD10 [get_ports sfp_txn]
|
||||||
|
set_property PACKAGE_PIN AC12 [get_ports sfp_rxp]
|
||||||
|
set_property PACKAGE_PIN AD12 [get_ports sfp_rxn]
|
||||||
|
|
||||||
|
set_property PACKAGE_PIN AA13 [get_ports mgt_clk_p]
|
||||||
|
set_property PACKAGE_PIN AB13 [get_ports mgt_clk_n]
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN C24 IOSTANDARD LVCMOS18} [get_ports mgt_clk_sel[1]]
|
||||||
|
set_property -dict {PACKAGE_PIN B26 IOSTANDARD LVCMOS18} [get_ports mgt_clk_sel[0]]
|
||||||
|
|
||||||
|
# uart
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS18} [get_ports uart_sin]
|
||||||
|
set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS18} [get_ports uart_sout]
|
||||||
|
|
||||||
|
# fan
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN J26 IOSTANDARD LVCMOS25} [get_ports fan_pwm]
|
||||||
|
|
||||||
|
# lcd
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[6]] ; ## lcd_e
|
||||||
|
set_property -dict {PACKAGE_PIN L23 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[5]] ; ## lcd_rs
|
||||||
|
set_property -dict {PACKAGE_PIN L24 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[4]] ; ## lcd_rw
|
||||||
|
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[3]] ; ## lcd_db[7]
|
||||||
|
set_property -dict {PACKAGE_PIN M25 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[2]] ; ## lcd_db[6]
|
||||||
|
set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[1]] ; ## lcd_db[5]
|
||||||
|
set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[0]] ; ## lcd_db[4]
|
||||||
|
set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS15} [get_ports gpio_sw[0]] ; ## GPIO_DIP_SW0
|
||||||
|
set_property -dict {PACKAGE_PIN P8 IOSTANDARD LVCMOS15} [get_ports gpio_sw[1]] ; ## GPIO_DIP_SW1
|
||||||
|
set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS15} [get_ports gpio_sw[2]] ; ## GPIO_DIP_SW2
|
||||||
|
set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS15} [get_ports gpio_sw[3]] ; ## GPIO_DIP_SW3
|
||||||
|
set_property -dict {PACKAGE_PIN P6 IOSTANDARD LVCMOS15} [get_ports gpio_sw[4]] ; ## GPIO_SW_N
|
||||||
|
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS15} [get_ports gpio_sw[5]] ; ## GPIO_SW_E
|
||||||
|
set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS15} [get_ports gpio_sw[6]] ; ## GPIO_SW_S
|
||||||
|
set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS15} [get_ports gpio_sw[7]] ; ## GPIO_SW_W
|
||||||
|
set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS15} [get_ports gpio_sw[8]] ; ## GPIO_SW_C
|
||||||
|
set_property -dict {PACKAGE_PIN M26 IOSTANDARD LVCMOS15} [get_ports gpio_led[0]] ; ## GPIO_LED_0_LS
|
||||||
|
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS15} [get_ports gpio_led[1]] ; ## GPIO_LED_1_LS
|
||||||
|
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS15} [get_ports gpio_led[2]] ; ## GPIO_LED_2_LS
|
||||||
|
set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS15} [get_ports gpio_led[3]] ; ## GPIO_LED_3_LS
|
||||||
|
|
||||||
|
# iic
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS15} [get_ports iic_rstn]
|
||||||
|
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS15 DRIVE 8 SLEW SLOW} [get_ports iic_scl]
|
||||||
|
set_property -dict {PACKAGE_PIN K25 IOSTANDARD LVCMOS15 DRIVE 8 SLEW SLOW} [get_ports iic_sda]
|
||||||
|
|
||||||
|
# hdmi
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS18} [get_ports hdmi_out_clk]
|
||||||
|
set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS18} [get_ports hdmi_hsync]
|
||||||
|
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS18} [get_ports hdmi_vsync]
|
||||||
|
set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS18} [get_ports hdmi_data_e]
|
||||||
|
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[0]]
|
||||||
|
set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[1]]
|
||||||
|
set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS18} [get_ports hdmi_data[2]]
|
||||||
|
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS18} [get_ports hdmi_data[3]]
|
||||||
|
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS18} [get_ports hdmi_data[4]]
|
||||||
|
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[5]]
|
||||||
|
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[6]]
|
||||||
|
set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS18} [get_ports hdmi_data[7]]
|
||||||
|
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[8]]
|
||||||
|
set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[9]]
|
||||||
|
set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS18} [get_ports hdmi_data[10]]
|
||||||
|
set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[11]]
|
||||||
|
set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS18} [get_ports hdmi_data[12]]
|
||||||
|
set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[13]]
|
||||||
|
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS18} [get_ports hdmi_data[14]]
|
||||||
|
set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[15]]
|
||||||
|
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[16]]
|
||||||
|
set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[17]]
|
||||||
|
set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[18]]
|
||||||
|
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[19]]
|
||||||
|
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[20]]
|
||||||
|
set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS18} [get_ports hdmi_data[21]]
|
||||||
|
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[22]]
|
||||||
|
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS18} [get_ports hdmi_data[23]]
|
||||||
|
|
||||||
|
# spdif
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS18} [get_ports spdif]
|
||||||
|
|
||||||
|
# clocks
|
||||||
|
|
||||||
|
# create_generated_clock -source sys_clk -name cpu_clk -multiply_by 1 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl_1/ui_clk]
|
||||||
|
# create_generated_clock -source cpu_clk -name m200_clk -multiply_by 2 [get_pins i_system_wrapper/system_i/proc_sys_clock_1/clk_out1]
|
||||||
|
# create_generated_clock -source m200_clk -name hdmi_clk -period 6.73 [get_pins i_system_wrapper/system_i/axi_hdmi_clkgen/clk_0]
|
||||||
|
# create_generated_clock -source m200_clk -name spdif_clk -period 50.00 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out1]
|
||||||
|
|
||||||
|
# set_clock_groups -asynchronous -group {cpu_clk}
|
||||||
|
# set_clock_groups -asynchronous -group {m200_clk}
|
||||||
|
# set_clock_groups -asynchronous -group {hdmi_clk}
|
||||||
|
# set_clock_groups -asynchronous -group {spdif_clk}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,202 @@
|
||||||
|
<?xml version='1.0' encoding='UTF-8'?>
|
||||||
|
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
|
||||||
|
<Project NoOfControllers="1" >
|
||||||
|
<ModuleName>system_axi_ddr_cntrl_1_0</ModuleName>
|
||||||
|
<dci_inouts_inputs>1</dci_inouts_inputs>
|
||||||
|
<dci_inputs>1</dci_inputs>
|
||||||
|
<Debug_En>OFF</Debug_En>
|
||||||
|
<DataDepth_En>1024</DataDepth_En>
|
||||||
|
<LowPower_En>OFF</LowPower_En>
|
||||||
|
<XADC_En>Disabled</XADC_En>
|
||||||
|
<TargetFPGA>xc7a200t-fbg676/-2</TargetFPGA>
|
||||||
|
<Version>2.0</Version>
|
||||||
|
<SystemClock>Differential</SystemClock>
|
||||||
|
<ReferenceClock>Use System Clock</ReferenceClock>
|
||||||
|
<SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
|
||||||
|
<BankSelectionFlag>FALSE</BankSelectionFlag>
|
||||||
|
<InternalVref>0</InternalVref>
|
||||||
|
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
|
||||||
|
<dci_cascade>0</dci_cascade>
|
||||||
|
<Controller number="0" >
|
||||||
|
<MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>
|
||||||
|
<TimePeriod>2500</TimePeriod>
|
||||||
|
<VccAuxIO>1.8V</VccAuxIO>
|
||||||
|
<PHYRatio>4:1</PHYRatio>
|
||||||
|
<InputClkFreq>200</InputClkFreq>
|
||||||
|
<UIExtraClocks>0</UIExtraClocks>
|
||||||
|
<MMCMClkOut0> 1.000</MMCMClkOut0>
|
||||||
|
<MMCMClkOut1>1</MMCMClkOut1>
|
||||||
|
<MMCMClkOut2>1</MMCMClkOut2>
|
||||||
|
<MMCMClkOut3>1</MMCMClkOut3>
|
||||||
|
<MMCMClkOut4>1</MMCMClkOut4>
|
||||||
|
<DataWidth>64</DataWidth>
|
||||||
|
<DeepMemory>1</DeepMemory>
|
||||||
|
<DataMask>1</DataMask>
|
||||||
|
<ECC>Disabled</ECC>
|
||||||
|
<Ordering>Normal</Ordering>
|
||||||
|
<CustomPart>FALSE</CustomPart>
|
||||||
|
<NewPartName></NewPartName>
|
||||||
|
<RowAddress>14</RowAddress>
|
||||||
|
<ColAddress>10</ColAddress>
|
||||||
|
<BankAddress>3</BankAddress>
|
||||||
|
<MemoryVoltage>1.5V</MemoryVoltage>
|
||||||
|
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
|
||||||
|
<PinSelection>
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M4" SLEW="FAST" name="ddr3_addr[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N7" SLEW="FAST" name="ddr3_addr[10]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L5" SLEW="FAST" name="ddr3_addr[11]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L7" SLEW="FAST" name="ddr3_addr[12]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N6" SLEW="FAST" name="ddr3_addr[13]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J3" SLEW="FAST" name="ddr3_addr[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J1" SLEW="FAST" name="ddr3_addr[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L4" SLEW="FAST" name="ddr3_addr[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K5" SLEW="FAST" name="ddr3_addr[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M7" SLEW="FAST" name="ddr3_addr[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K1" SLEW="FAST" name="ddr3_addr[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M6" SLEW="FAST" name="ddr3_addr[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H1" SLEW="FAST" name="ddr3_addr[8]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K3" SLEW="FAST" name="ddr3_addr[9]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N1" SLEW="FAST" name="ddr3_ba[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M1" SLEW="FAST" name="ddr3_ba[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H2" SLEW="FAST" name="ddr3_ba[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T4" SLEW="FAST" name="ddr3_cas_n" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="L2" SLEW="FAST" name="ddr3_ck_n[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="M2" SLEW="FAST" name="ddr3_ck_p[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="P4" SLEW="FAST" name="ddr3_cke[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T3" SLEW="FAST" name="ddr3_cs_n[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AC6" SLEW="FAST" name="ddr3_dm[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AC4" SLEW="FAST" name="ddr3_dm[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA3" SLEW="FAST" name="ddr3_dm[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U7" SLEW="FAST" name="ddr3_dm[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G1" SLEW="FAST" name="ddr3_dm[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F3" SLEW="FAST" name="ddr3_dm[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G5" SLEW="FAST" name="ddr3_dm[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H9" SLEW="FAST" name="ddr3_dm[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB6" SLEW="FAST" name="ddr3_dq[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AF3" SLEW="FAST" name="ddr3_dq[10]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AE3" SLEW="FAST" name="ddr3_dq[11]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AD3" SLEW="FAST" name="ddr3_dq[12]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AC3" SLEW="FAST" name="ddr3_dq[13]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB4" SLEW="FAST" name="ddr3_dq[14]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA4" SLEW="FAST" name="ddr3_dq[15]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AC2" SLEW="FAST" name="ddr3_dq[16]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB2" SLEW="FAST" name="ddr3_dq[17]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AF2" SLEW="FAST" name="ddr3_dq[18]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AE2" SLEW="FAST" name="ddr3_dq[19]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA8" SLEW="FAST" name="ddr3_dq[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y1" SLEW="FAST" name="ddr3_dq[20]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y2" SLEW="FAST" name="ddr3_dq[21]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AC1" SLEW="FAST" name="ddr3_dq[22]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB1" SLEW="FAST" name="ddr3_dq[23]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y3" SLEW="FAST" name="ddr3_dq[24]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W3" SLEW="FAST" name="ddr3_dq[25]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W6" SLEW="FAST" name="ddr3_dq[26]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V6" SLEW="FAST" name="ddr3_dq[27]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W4" SLEW="FAST" name="ddr3_dq[28]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W5" SLEW="FAST" name="ddr3_dq[29]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y8" SLEW="FAST" name="ddr3_dq[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W1" SLEW="FAST" name="ddr3_dq[30]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V1" SLEW="FAST" name="ddr3_dq[31]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G2" SLEW="FAST" name="ddr3_dq[32]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D1" SLEW="FAST" name="ddr3_dq[33]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E1" SLEW="FAST" name="ddr3_dq[34]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E2" SLEW="FAST" name="ddr3_dq[35]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F2" SLEW="FAST" name="ddr3_dq[36]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="A2" SLEW="FAST" name="ddr3_dq[37]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="A3" SLEW="FAST" name="ddr3_dq[38]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C2" SLEW="FAST" name="ddr3_dq[39]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB5" SLEW="FAST" name="ddr3_dq[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C3" SLEW="FAST" name="ddr3_dq[40]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D3" SLEW="FAST" name="ddr3_dq[41]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="A4" SLEW="FAST" name="ddr3_dq[42]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B4" SLEW="FAST" name="ddr3_dq[43]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C4" SLEW="FAST" name="ddr3_dq[44]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D4" SLEW="FAST" name="ddr3_dq[45]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D5" SLEW="FAST" name="ddr3_dq[46]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E5" SLEW="FAST" name="ddr3_dq[47]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F4" SLEW="FAST" name="ddr3_dq[48]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G4" SLEW="FAST" name="ddr3_dq[49]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA5" SLEW="FAST" name="ddr3_dq[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K6" SLEW="FAST" name="ddr3_dq[50]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K7" SLEW="FAST" name="ddr3_dq[51]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K8" SLEW="FAST" name="ddr3_dq[52]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L8" SLEW="FAST" name="ddr3_dq[53]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J5" SLEW="FAST" name="ddr3_dq[54]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J6" SLEW="FAST" name="ddr3_dq[55]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G6" SLEW="FAST" name="ddr3_dq[56]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H6" SLEW="FAST" name="ddr3_dq[57]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F7" SLEW="FAST" name="ddr3_dq[58]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F8" SLEW="FAST" name="ddr3_dq[59]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y5" SLEW="FAST" name="ddr3_dq[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G8" SLEW="FAST" name="ddr3_dq[60]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H8" SLEW="FAST" name="ddr3_dq[61]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D6" SLEW="FAST" name="ddr3_dq[62]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E6" SLEW="FAST" name="ddr3_dq[63]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y6" SLEW="FAST" name="ddr3_dq[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y7" SLEW="FAST" name="ddr3_dq[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AF4" SLEW="FAST" name="ddr3_dq[8]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AF5" SLEW="FAST" name="ddr3_dq[9]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="W8" SLEW="FAST" name="ddr3_dqs_n[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="AE5" SLEW="FAST" name="ddr3_dqs_n[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="AE1" SLEW="FAST" name="ddr3_dqs_n[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="V2" SLEW="FAST" name="ddr3_dqs_n[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="B1" SLEW="FAST" name="ddr3_dqs_n[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="A5" SLEW="FAST" name="ddr3_dqs_n[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="H4" SLEW="FAST" name="ddr3_dqs_n[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="G7" SLEW="FAST" name="ddr3_dqs_n[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="V8" SLEW="FAST" name="ddr3_dqs_p[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="AD5" SLEW="FAST" name="ddr3_dqs_p[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="AD1" SLEW="FAST" name="ddr3_dqs_p[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="V3" SLEW="FAST" name="ddr3_dqs_p[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="C1" SLEW="FAST" name="ddr3_dqs_p[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="B5" SLEW="FAST" name="ddr3_dqs_p[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="J4" SLEW="FAST" name="ddr3_dqs_p[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="H7" SLEW="FAST" name="ddr3_dqs_p[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="R2" SLEW="FAST" name="ddr3_odt[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="P1" SLEW="FAST" name="ddr3_ras_n" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="LVCMOS15" PADName="N8" SLEW="FAST" name="ddr3_reset_n" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="R1" SLEW="FAST" name="ddr3_we_n" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="P3" SLEW="" name="sys_clk_n" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="R3" SLEW="" name="sys_clk_p" IN_TERM="" />
|
||||||
|
</PinSelection>
|
||||||
|
<System_Clock>
|
||||||
|
<Pin PADName="R3/P3(CC_P/N)" Bank="34" name="sys_clk_p/n" />
|
||||||
|
</System_Clock>
|
||||||
|
<System_Control>
|
||||||
|
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
|
||||||
|
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
|
||||||
|
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
|
||||||
|
</System_Control>
|
||||||
|
<TimingParameters>
|
||||||
|
<Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.125" tras="35" trcd="13.125" />
|
||||||
|
</TimingParameters>
|
||||||
|
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
|
||||||
|
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
|
||||||
|
<mrCasLatency name="CAS Latency" >6</mrCasLatency>
|
||||||
|
<mrMode name="Mode" >Normal</mrMode>
|
||||||
|
<mrDllReset name="DLL Reset" >No</mrDllReset>
|
||||||
|
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
|
||||||
|
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
|
||||||
|
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
|
||||||
|
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
|
||||||
|
<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
|
||||||
|
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
|
||||||
|
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
|
||||||
|
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
|
||||||
|
<emrDQS name="TDQS enable" >Enabled</emrDQS>
|
||||||
|
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
|
||||||
|
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
|
||||||
|
<mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
|
||||||
|
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
|
||||||
|
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
|
||||||
|
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
|
||||||
|
<PortInterface>AXI</PortInterface>
|
||||||
|
<AXIParameters>
|
||||||
|
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
|
||||||
|
<C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
|
||||||
|
<C0_S_AXI_DATA_WIDTH>512</C0_S_AXI_DATA_WIDTH>
|
||||||
|
<C0_S_AXI_ID_WIDTH>2</C0_S_AXI_ID_WIDTH>
|
||||||
|
<C0_S_AXI_SUPPORTS_NARROW_BURST>1</C0_S_AXI_SUPPORTS_NARROW_BURST>
|
||||||
|
</AXIParameters>
|
||||||
|
</Controller>
|
||||||
|
</Project>
|
||||||
Loading…
Reference in New Issue