From 35b97abc6d01a2f1bbf48ed9055fd84fa1d31df3 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 31 Jan 2017 16:20:13 +0200 Subject: [PATCH] axi_adc_trigger: Initial commit --- library/axi_adc_trigger/Makefile | 50 +++ library/axi_adc_trigger/axi_adc_trigger.v | 413 ++++++++++++++++++ .../axi_adc_trigger_constr.xdc | 12 + .../axi_adc_trigger/axi_adc_trigger_ip.tcl | 22 + library/axi_adc_trigger/axi_adc_trigger_reg.v | 241 ++++++++++ 5 files changed, 738 insertions(+) create mode 100644 library/axi_adc_trigger/Makefile create mode 100644 library/axi_adc_trigger/axi_adc_trigger.v create mode 100644 library/axi_adc_trigger/axi_adc_trigger_constr.xdc create mode 100644 library/axi_adc_trigger/axi_adc_trigger_ip.tcl create mode 100644 library/axi_adc_trigger/axi_adc_trigger_reg.v diff --git a/library/axi_adc_trigger/Makefile b/library/axi_adc_trigger/Makefile new file mode 100644 index 000000000..c2ab354f1 --- /dev/null +++ b/library/axi_adc_trigger/Makefile @@ -0,0 +1,50 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../common/up_axi.v +M_DEPS += ../common/up_xfer_cntrl.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += axi_adc_trigger.v +M_DEPS += axi_adc_trigger_constr.xdc +M_DEPS += axi_adc_trigger_ip.tcl +M_DEPS += axi_adc_trigger_reg.v + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: axi_adc_trigger.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +axi_adc_trigger.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) axi_adc_trigger_ip.tcl >> axi_adc_trigger_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/library/axi_adc_trigger/axi_adc_trigger.v b/library/axi_adc_trigger/axi_adc_trigger.v new file mode 100644 index 000000000..dde4990bc --- /dev/null +++ b/library/axi_adc_trigger/axi_adc_trigger.v @@ -0,0 +1,413 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adc_trigger( + + input clk, + + input [ 1:0] trigger_i, + output [ 1:0] trigger_o, + output [ 1:0] trigger_t, + + input [15:0] data_a, + input [15:0] data_b, + input data_valid_a, + input data_valid_b, + + output [15:0] data_a_trig, + output [15:0] data_b_trig, + output data_valid_a_trig, + output data_valid_b_trig, + + output [31:0] trigger_offset, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready); + + // internal signals + + wire up_clk; + wire up_rstn; + wire [13:0] up_waddr; + wire [31:0] up_wdata; + wire up_wack; + wire up_wreq; + wire up_rack; + wire [31:0] up_rdata; + wire up_rreq; + wire [13:0] up_raddr; + + wire [ 1:0] io_selection; + + wire [ 1:0] low_level; + wire [ 1:0] high_level; + wire [ 1:0] any_edge; + wire [ 1:0] rise_edge; + wire [ 1:0] fall_edge; + + wire [15:0] limit_a; + wire [ 1:0] function_a; + wire [31:0] hysteresis_a; + wire [ 3:0] trigger_l_mix_a; + + wire [15:0] limit_b; + wire [ 1:0] function_b; + wire [31:0] hysteresis_b; + wire [ 3:0] trigger_l_mix_b; + + wire [ 2:0] trigger_out_mix; + wire [31:0] delay_trigger; + + wire [15:0] data_a_cmp; + wire [15:0] data_b_cmp; + wire [15:0] limit_a_cmp; + wire [15:0] limit_b_cmp; + + wire trigger_a_fall_edge; + wire trigger_a_rise_edge; + wire trigger_b_fall_edge; + wire trigger_b_rise_edge; + wire trigger_a_any_edge; + wire trigger_b_any_edge; + wire trigger_out_a; + wire trigger_out_b; + + reg trigger_a_d1; // synchronization flip flop + reg trigger_a_d2; // synchronization flip flop + reg trigger_a_d3; + reg trigger_b_d1; // synchronization flip flop + reg trigger_b_d2; // synchronization flip flop + reg trigger_b_d3; + reg passthrough_high_a; // trigger when rising through the limit + reg passthrough_low_a; // trigger when fallingh thorugh the limit + reg low_a; // signal was under the limit, so if it goes through, assert rising + reg high_a; // signal was over the limit, so if it passes through, assert falling + reg comp_high_a; // signal is over the limit + reg comp_low_a; // signal is under the limit + reg passthrough_high_b; // trigger when rising through the limit + reg passthrough_low_b; // trigger when fallingh thorugh the limit + reg low_b; // signal was under the limit, so if it goes through, assert rising + reg high_b; // signal was over the limit, so if it passes through, assert falling + reg comp_high_b; // signal is over the limit + reg comp_low_b; // signal is under the limit + + reg trigger_pin_a; + reg trigger_pin_b; + + reg trigger_adc_a; + reg trigger_adc_b; + + reg trigger_a; + reg trigger_b; + + reg trigger_out_mixed; + + reg [15:0] data_a_r; + reg [15:0] data_b_r; + reg data_valid_a_r; + reg data_valid_b_r; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + assign trigger_offset = delay_trigger; + + assign trigger_t = io_selection; + + assign trigger_a_fall_edge = (trigger_a_d2 == 1'b0 && trigger_a_d3 == 1'b1) ? 1'b1: 1'b0; + assign trigger_a_rise_edge = (trigger_a_d2 == 1'b1 && trigger_a_d3 == 1'b0) ? 1'b1: 1'b0; + assign trigger_a_any_edge = trigger_a_rise_edge | trigger_a_fall_edge; + assign trigger_b_fall_edge = (trigger_b_d2 == 1'b0 && trigger_b_d3 == 1'b1) ? 1'b1: 1'b0; + assign trigger_b_rise_edge = (trigger_b_d2 == 1'b1 && trigger_b_d3 == 1'b0) ? 1'b1: 1'b0; + assign trigger_b_any_edge = trigger_b_rise_edge | trigger_b_fall_edge; + + assign data_a_cmp = {!data_a[15],data_a[14:0]}; + assign data_b_cmp = {!data_b[15],data_b[14:0]}; + assign limit_a_cmp = {!limit_a[15],limit_a[14:0]}; + assign limit_b_cmp = {!limit_b[15],limit_b[14:0]}; + + assign data_a_trig = {trigger_out_mixed, data_a_r[14:0]}; + assign data_b_trig = {trigger_out_mixed, data_b_r[14:0]};; + assign data_valid_a_trig = data_valid_a_r; + assign data_valid_b_trig = data_valid_b_r; + + always @(posedge clk) begin + data_a_r <= data_a; + data_valid_a_r <= data_valid_a; + data_b_r <= data_b; + data_valid_b_r <= data_valid_b; + end + + always @(*) begin + case(trigger_l_mix_a) + 4'h0: trigger_a = 1'b1; + 4'h1: trigger_a = trigger_pin_a; + 4'h2: trigger_a = trigger_adc_a; + 4'h4: trigger_a = trigger_pin_a | trigger_adc_a ; + 4'h5: trigger_a = trigger_pin_a & trigger_adc_a ; + 4'h6: trigger_a = trigger_pin_a ^ trigger_adc_a ; + 4'h7: trigger_a = !(trigger_pin_a | trigger_adc_a) ; + 4'h8: trigger_a = !(trigger_pin_a & trigger_adc_a) ; + 4'h9: trigger_a = !(trigger_pin_a ^ trigger_adc_a) ; + default: trigger_a = 1'b1; + endcase + end + + always @(*) begin + case(trigger_l_mix_b) + 4'h0: trigger_b = 1'b1; + 4'h1: trigger_b = trigger_pin_b; + 4'h2: trigger_b = trigger_adc_b; + 4'h4: trigger_b = trigger_pin_b | trigger_adc_b ; + 4'h5: trigger_b = trigger_pin_b & trigger_adc_b ; + 4'h6: trigger_b = trigger_pin_b ^ trigger_adc_b ; + 4'h7: trigger_b = !(trigger_pin_b | trigger_adc_b) ; + 4'h8: trigger_b = !(trigger_pin_b & trigger_adc_b) ; + 4'h9: trigger_b = !(trigger_pin_b ^ trigger_adc_b) ; + default: trigger_b = 1'b1; + endcase + end + + always @(*) begin + case(function_a) + 2'h0: trigger_adc_a = comp_low_a; + 2'h1: trigger_adc_a = comp_high_a; + 2'h2: trigger_adc_a = passthrough_high_a; + 2'h3: trigger_adc_a = passthrough_low_a; + default: trigger_adc_a = comp_low_a; + endcase + end + + always @(*) begin + case(function_b) + 2'h0: trigger_adc_b = comp_low_b; + 2'h1: trigger_adc_b = comp_high_b; + 2'h2: trigger_adc_b = passthrough_high_b; + 2'h3: trigger_adc_b = passthrough_low_b; + default: trigger_adc_b = comp_low_b; + endcase + end + + always @(posedge clk) begin + trigger_a_d1 <= trigger_i[0]; + trigger_a_d2 <= trigger_a_d1; + trigger_a_d3 <= trigger_a_d2; + trigger_b_d1 <= trigger_i[1]; + trigger_b_d2 <= trigger_b_d1; + trigger_b_d3 <= trigger_b_d2; + end + + always @(*) begin + trigger_pin_a = ((!trigger_a_d3 & low_level[0]) | + (trigger_a_d3 & high_level[0]) | + (trigger_a_fall_edge & fall_edge[0]) | + (trigger_a_rise_edge & rise_edge[0]) | + (trigger_a_any_edge & any_edge[0])); + end + + always @(*) begin + trigger_pin_b = ((!trigger_b_d3 & low_level[1]) | + (trigger_b_d3 & high_level[1]) | + (trigger_b_fall_edge & fall_edge[1]) | + (trigger_b_rise_edge & rise_edge[1]) | + (trigger_b_any_edge & any_edge[1])); + end + + always @(*) begin + case(trigger_out_mix) + 3'h0: trigger_out_mixed = trigger_a; + 3'h1: trigger_out_mixed = trigger_b; + 3'h2: trigger_out_mixed = trigger_a | trigger_b; + 3'h3: trigger_out_mixed = trigger_a & trigger_b; + 3'h4: trigger_out_mixed = trigger_a ^ trigger_b; + default: trigger_out_mixed = trigger_a; + endcase + end + + always @(posedge clk) begin + if (data_valid_a == 1'b1) begin + if (data_a_cmp > limit_a_cmp) begin + comp_high_a <= 1'b1; + passthrough_high_a <= low_a; + end else begin + comp_high_a <= 1'b0; + passthrough_high_a <= 1'b0; + end + if (data_a_cmp < limit_a_cmp) begin + comp_low_a <= 1'b1; + passthrough_low_a <= high_a; + end else begin + comp_low_a <= 1'b0; + passthrough_low_a <= 1'b0; + end + if (passthrough_high_a == 1'b1) begin + low_a <= 1'b0; + end else if (data_a_cmp < limit_a_cmp - hysteresis_a) begin + low_a <= 1'b1; + end + if (passthrough_low_a == 1'b1) begin + high_a <= 1'b0; + end else if (data_a_cmp > limit_a_cmp + hysteresis_a) begin + high_a <= 1'b1; + end + end + end + + always @(posedge clk) begin + if (data_valid_b == 1'b1) begin + if (data_b_cmp > limit_b_cmp) begin + comp_high_b <= 1'b1; + passthrough_high_b <= low_b; + end else begin + comp_high_b <= 1'b0; + passthrough_high_b <= 1'b0; + end + if (data_b_cmp < limit_b_cmp) begin + comp_low_b <= 1'b1; + passthrough_low_b <= high_b; + end else begin + comp_low_b <= 1'b0; + passthrough_low_b <= 1'b0; + end + if (trigger_b == 1'b1) begin + low_b <= 1'b0; + high_b <= 1'b0; + end else if (data_b_cmp < limit_b_cmp - hysteresis_b) begin + low_b <= 1'b1; + end else if (data_b_cmp > limit_b_cmp + hysteresis_b) begin + high_b <= 1'b1; + end + end + end + + axi_adc_trigger_reg adc_trigger_registers ( + + .clk(clk), + + .io_selection(io_selection), + .trigger_o(trigger_o), + + .low_level(low_level), + .high_level(high_level), + .any_edge(any_edge), + .rise_edge(rise_edge), + .fall_edge(fall_edge), + + .limit_a(limit_a), + .function_a(function_a), + .hysteresis_a(hysteresis_a), + .trigger_l_mix_a(trigger_l_mix_a), + + .limit_b(limit_b), + .function_b(function_b), + .hysteresis_b(hysteresis_b), + .trigger_l_mix_b(trigger_l_mix_b), + + .trigger_out_mix(trigger_out_mix), + .delay_trigger(delay_trigger), + + // bus interface + + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata), + .up_rack(up_rack)); + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/axi_adc_trigger/axi_adc_trigger_constr.xdc b/library/axi_adc_trigger/axi_adc_trigger_constr.xdc new file mode 100644 index 000000000..d8c0c576e --- /dev/null +++ b/library/axi_adc_trigger/axi_adc_trigger_constr.xdc @@ -0,0 +1,12 @@ +set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_state*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_toggle*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *trigger_a_d*}] +set_property shreg_extract no [get_cells -hier -filter {name =~ *trigger_b_d*}] + +set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *trigger_a_d1_reg* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *trigger_b_d1_reg* && IS_SEQUENTIAL}] + diff --git a/library/axi_adc_trigger/axi_adc_trigger_ip.tcl b/library/axi_adc_trigger/axi_adc_trigger_ip.tcl new file mode 100644 index 000000000..1cefb23be --- /dev/null +++ b/library/axi_adc_trigger/axi_adc_trigger_ip.tcl @@ -0,0 +1,22 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_adc_trigger +adi_ip_files axi_adc_trigger [list \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "axi_adc_trigger_constr.xdc" \ + "axi_adc_trigger_reg.v" \ + "axi_adc_trigger.v" ] + +adi_ip_properties axi_adc_trigger +adi_ip_constraints axi_adc_trigger [list \ + "axi_adc_trigger_constr.xdc" ] + +ipx::remove_bus_interface {clk} [ipx::current_core] +ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/library/axi_adc_trigger/axi_adc_trigger_reg.v b/library/axi_adc_trigger/axi_adc_trigger_reg.v new file mode 100644 index 000000000..62d530553 --- /dev/null +++ b/library/axi_adc_trigger/axi_adc_trigger_reg.v @@ -0,0 +1,241 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adc_trigger_reg ( + + input clk, + + output reg [ 1:0] io_selection, + output reg [ 1:0] trigger_o, + + output [ 1:0] low_level, + output [ 1:0] high_level, + output [ 1:0] any_edge, + output [ 1:0] rise_edge, + output [ 1:0] fall_edge, + + output [15:0] limit_a, + output [ 1:0] function_a, + output [31:0] hysteresis_a, + output [ 3:0] trigger_l_mix_a, + + output [15:0] limit_b, + output [ 1:0] function_b, + output [31:0] hysteresis_b, + output [ 3:0] trigger_l_mix_b, + + output [ 2:0] trigger_out_mix, + output [31:0] delay_trigger, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack); + + // internal signals + + wire up_wreq_s; + wire up_rreq_s; + wire [ 9:0] config_trigger; + + // internal registers + + reg [31:0] up_version = 32'h00010000; + reg [31:0] up_scratch = 32'h0; + reg [ 9:0] up_config_trigger = 10'h0; + reg [15:0] up_limit_a = 16'h0; + reg [ 1:0] up_function_a = 2'h0; + reg [31:0] up_hysteresis_a = 32'h0; + reg [ 3:0] up_trigger_l_mix_a = 32'h0; + reg [15:0] up_limit_b = 16'h0; + reg [ 1:0] up_function_b = 2'h0; + reg [31:0] up_hysteresis_b = 32'h0; + reg [ 3:0] up_trigger_l_mix_b = 32'h0; + reg [ 2:0] up_trigger_out_mix = 32'h0; + reg [31:0] up_delay_trigger= 32'h0; + + assign up_wreq_s = ((up_waddr[13:5] == 6'h00)) ? up_wreq : 1'b0; + assign up_rreq_s = ((up_raddr[13:5] == 6'h00)) ? up_rreq : 1'b0; + + assign low_level = config_trigger[1:0]; + assign high_level = config_trigger[3:2]; + assign any_edge = config_trigger[5:4]; + assign rise_edge = config_trigger[7:6]; + assign fall_edge = config_trigger[9:8]; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_scratch <= 'd0; + io_selection <= 'd3; + trigger_o <= 'd0; + up_config_trigger <= 'd0; + up_limit_a <= 'd0; + up_function_a <= 'd0; + up_hysteresis_a <= 'd0; + up_limit_b <= 'd0; + up_function_b <= 'd0; + up_hysteresis_b <= 'd0; + up_delay_trigger <= 'd0; + up_trigger_l_mix_a <= 'd0; + up_trigger_l_mix_b <= 'd0; + up_trigger_out_mix <= 'd0; + end else begin + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h1)) begin + up_scratch <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h2)) begin + trigger_o <= up_wdata[1:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h3)) begin + io_selection <= up_wdata[1:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h4)) begin + up_config_trigger <= up_wdata[9:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h5)) begin + up_limit_a <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h6)) begin + up_function_a <= up_wdata[1:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h7)) begin + up_hysteresis_a <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h8)) begin + up_trigger_l_mix_a <= up_wdata[3:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h9)) begin + up_limit_b <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'ha)) begin + up_function_b <= up_wdata[1:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hb)) begin + up_hysteresis_b <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hc)) begin + up_trigger_l_mix_b <= up_wdata[3:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hd)) begin + up_trigger_out_mix <= up_wdata[2:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'he)) begin + up_delay_trigger <= up_wdata; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[4:0]) + 5'h0: up_rdata <= up_version; + 5'h1: up_rdata <= up_scratch; + 5'h2: up_rdata <= {30'h0,trigger_o}; + 5'h3: up_rdata <= {30'h0,io_selection}; + 5'h4: up_rdata <= {22'h0,up_config_trigger}; + 5'h5: up_rdata <= {16'h0,up_limit_a}; + 5'h6: up_rdata <= {30'h0,up_function_a}; + 5'h7: up_rdata <= up_hysteresis_a; + 5'h8: up_rdata <= {28'h0,up_trigger_l_mix_a}; + 5'h9: up_rdata <= {16'h0,up_limit_b}; + 5'ha: up_rdata <= {30'h0,up_function_b}; + 5'hb: up_rdata <= up_hysteresis_b; + 5'hc: up_rdata <= {28'h0,up_trigger_l_mix_b}; + 5'hd: up_rdata <= {29'h0,up_trigger_out_mix}; + 5'he: up_rdata <= up_delay_trigger; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + up_xfer_cntrl #(.DATA_WIDTH(153)) i_xfer_cntrl ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_cntrl ({ up_config_trigger, // 10 + up_limit_a, // 16 + up_function_a, // 2 + up_hysteresis_a, // 32 + up_trigger_l_mix_a, // 4 + up_limit_b, // 16 + up_function_b, // 2 + up_hysteresis_b, // 32 + up_trigger_l_mix_b, // 4 + up_trigger_out_mix, // 3 + up_delay_trigger}), // 32 + + .up_xfer_done (), + .d_rst (1'b0), + .d_clk (clk), + .d_data_cntrl ({ config_trigger, // 10 + limit_a, // 16 + function_a, // 2 + hysteresis_a, // 32 + trigger_l_mix_a, // 4 + limit_b, // 16 + function_b, // 2 + hysteresis_b, // 32 + trigger_l_mix_b, // 4 + trigger_out_mix, // 3 + delay_trigger})); // 32 + +endmodule + +// *************************************************************************** +// *************************************************************************** +