From 3526145992c8914a58e6ba5d7d59e6a8cf6823a5 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Thu, 23 Apr 2015 10:19:43 +0300 Subject: [PATCH] axi_ad9144: Added CDC and reset constraints --- library/axi_ad9144/axi_ad9144_constr.xdc | 42 ++++++++++++++++++++++-- library/axi_ad9144/axi_ad9144_ip.tcl | 1 + 2 files changed, 41 insertions(+), 2 deletions(-) diff --git a/library/axi_ad9144/axi_ad9144_constr.xdc b/library/axi_ad9144/axi_ad9144_constr.xdc index c65aa103a..e43e9fea3 100644 --- a/library/axi_ad9144/axi_ad9144_constr.xdc +++ b/library/axi_ad9144/axi_ad9144_constr.xdc @@ -1,6 +1,44 @@ +set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]] +set ad9144_clk [get_clocks -of_objects [get_ports dac_clk]] -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports tx_clk]] -set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]] +set_property ASYNC_REG TRUE \ + [get_cells -hier *toggle_m1_reg*] \ + [get_cells -hier *toggle_m2_reg*] \ + [get_cells -hier *state_m1_reg*] \ + [get_cells -hier *state_m2_reg*] +set_false_path \ + -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}] +set_false_path \ + -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}] +set_max_delay -datapath_only \ + -from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \ + [get_property PERIOD $ad9144_clk] +set_false_path \ + -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}] +set_false_path \ + -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}] +set_max_delay -datapath_only \ + -from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \ + [get_property PERIOD $up_clk] +set_false_path \ + -from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}] +set_false_path \ + -from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}] +set_max_delay -datapath_only \ + -from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \ + [get_property PERIOD $up_clk] + +set_false_path \ + -to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}] diff --git a/library/axi_ad9144/axi_ad9144_ip.tcl b/library/axi_ad9144/axi_ad9144_ip.tcl index e6dce8f0f..0abb66f54 100644 --- a/library/axi_ad9144/axi_ad9144_ip.tcl +++ b/library/axi_ad9144/axi_ad9144_ip.tcl @@ -24,6 +24,7 @@ adi_ip_files axi_ad9144 [list \ "axi_ad9144_constr.xdc" ] adi_ip_properties axi_ad9144 + adi_ip_constraints axi_ad9144 [list \ "axi_ad9144_constr.xdc" ]