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adv7511:kcu105, axi_hdmi_tx, axi_spdif_tx constraints modified so they apply to ultrascale

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Adrian Costina 2015-05-05 10:06:26 +03:00
parent 319f821fab
commit 3517b6941c
4 changed files with 39 additions and 36 deletions
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64
library/axi_hdmi_tx/axi_hdmi_tx_constr.xdc
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@ -9,67 +9,67 @@ set_property ASYNC_REG TRUE \
[get_cells -hier *state_m2_reg*] [get_cells -hier *state_m2_reg*]
set_false_path \ set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
-to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}] -to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}]
set_false_path \ set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
-to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}] -to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}]
set_max_delay -datapath_only \ set_max_delay -datapath_only \
-from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \ -from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
-to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \ -to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
[get_property PERIOD $hdmi_clk] [get_property PERIOD $hdmi_clk]
set_false_path \ set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
-to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}] -to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}]
set_false_path \ set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
-to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}] -to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}]
set_max_delay -datapath_only \ set_max_delay -datapath_only \
-from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \ -from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
-to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \ -to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
[get_property PERIOD $up_clk] [get_property PERIOD $up_clk]
set_false_path \ set_false_path \
-from [get_cells -hier hdmi_fs_toggle_reg* -filter {primitive_subgroup == flop}] \ -from [get_cells -hier hdmi_fs_toggle_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
-to [get_cells -hier vdma_fs_toggle_m1_reg* -filter {primitive_subgroup == flop}] -to [get_cells -hier vdma_fs_toggle_m1_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}]
set_false_path \ set_false_path \
-from [get_cells -hier vdma_fs_ret_toggle_reg* -filter {primitive_subgroup == flop}] \ -from [get_cells -hier vdma_fs_ret_toggle_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
-to [get_cells -hier hdmi_fs_ret_toggle_m1_reg* -filter {primitive_subgroup == flop}] -to [get_cells -hier hdmi_fs_ret_toggle_m1_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}]
set_max_delay -datapath_only \ set_max_delay -datapath_only \
-from [get_cells -hier vdma_fs_waddr* -filter {primitive_subgroup == flop}] \ -from [get_cells -hier vdma_fs_waddr* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
-to [get_cells -hier hdmi_fs_waddr* -filter {primitive_subgroup == flop}] \ -to [get_cells -hier hdmi_fs_waddr* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
[get_property PERIOD $hdmi_clk] [get_property PERIOD $hdmi_clk]
set_false_path \ set_false_path \
-from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \ -from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
-to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}] -to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}]
set_false_path \ set_false_path \
-from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \ -from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
-to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}] -to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}]
set_max_delay -datapath_only \ set_max_delay -datapath_only \
-from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \ -from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
-to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \ -to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
[get_property PERIOD $up_clk] [get_property PERIOD $up_clk]
set_max_delay -datapath_only \ set_max_delay -datapath_only \
-from [get_cells -hier hdmi_raddr_g* -filter {primitive_subgroup == flop}] \ -from [get_cells -hier hdmi_raddr_g* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
-to [get_cells -hier vdma_raddr_g_m1* -filter {primitive_subgroup == flop}] \ -to [get_cells -hier vdma_raddr_g_m1* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
[get_property PERIOD $vdma_clk] [get_property PERIOD $vdma_clk]
set_max_delay -datapath_only \ set_max_delay -datapath_only \
-from [get_cells -hier vdma_tpm_oos_reg* -filter {primitive_subgroup == flop}] \ -from [get_cells -hier vdma_tpm_oos_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
-to [get_cells -hier d_acc_data_reg* -filter {primitive_subgroup == flop}] \ -to [get_cells -hier d_acc_data_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
[get_property PERIOD $up_clk] [get_property PERIOD $up_clk]
set_max_delay -datapath_only \ set_max_delay -datapath_only \
-from [get_cells -hier vdma_ovf_reg* -filter {primitive_subgroup == flop}] \ -from [get_cells -hier vdma_ovf_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
-to [get_cells -hier d_acc_data_reg* -filter {primitive_subgroup == flop}] \ -to [get_cells -hier d_acc_data_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
[get_property PERIOD $up_clk] [get_property PERIOD $up_clk]
set_max_delay -datapath_only \ set_max_delay -datapath_only \
-from [get_cells -hier vdma_unf_reg* -filter {primitive_subgroup == flop}] \ -from [get_cells -hier vdma_unf_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
-to [get_cells -hier d_acc_data_reg* -filter {primitive_subgroup == flop}] \ -to [get_cells -hier d_acc_data_reg* -filter {primitive_subgroup == flop || primitive_subgroup == SDR}] \
[get_property PERIOD $up_clk] [get_property PERIOD $up_clk]
set_false_path \ set_false_path \

8
library/axi_spdif_tx/axi_spdif_tx_constr.xdc
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@ -3,9 +3,9 @@ set_property ASYNC_REG TRUE \
[get_cells -hier cdc_sync_stage2_*_reg] [get_cells -hier cdc_sync_stage2_*_reg]
set_false_path \ set_false_path \
-from [get_cells -hier cdc_sync_stage0_*_reg -filter {PRIMITIVE_SUBGROUP == flop}] \ -from [get_cells -hier cdc_sync_stage0_*_reg -filter {PRIMITIVE_SUBGROUP == flop || primitive_subgroup == SDR}] \
-to [get_cells -hier cdc_sync_stage1_*_reg -filter {PRIMITIVE_SUBGROUP == flop}] -to [get_cells -hier cdc_sync_stage1_*_reg -filter {PRIMITIVE_SUBGROUP == flop || primitive_subgroup == SDR}]
set_false_path \ set_false_path \
-from [get_cells -hier spdif_out_reg -filter {PRIMITIVE_SUBGROUP == flop}] \ -from [get_cells -hier spdif_out_reg -filter {PRIMITIVE_SUBGROUP == flop || primitive_subgroup == SDR}] \
-to [get_cells -hier spdif_tx_o_reg -filter {PRIMITIVE_SUBGROUP == flop}] -to [get_cells -hier spdif_tx_o_reg -filter {PRIMITIVE_SUBGROUP == flop || primitive_subgroup == SDR}]

0
projects/adv7511/kcu105/system_bd.tcl Executable file → Normal file
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3
projects/adv7511/kcu105/system_project.tcl Executable file → Normal file
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@ -10,6 +10,9 @@ adi_project_files adv7511_kcu105 [list \
"$ad_hdl_dir/library/common/ad_iobuf.v" \ "$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" ] "$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" ]
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc]
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
adi_project_run adv7511_kcu105 adi_project_run adv7511_kcu105