daq2/a10gx- qsys updates
Rejeesh Kutty
parent
3351ff607e
commit
3516ec28b7
|
|
@ -0,0 +1,330 @@
|
|||
|
||||
package require -exact qsys 14.0
|
||||
|
||||
set_module_property NAME {system_bd}
|
||||
set_project_property DEVICE_FAMILY {Arria 10}
|
||||
set_project_property DEVICE {10AX115S3F45E2SGE3}
|
||||
|
||||
# clock-&-reset
|
||||
|
||||
add_instance sys_clk clock_source 15.1
|
||||
add_interface sys_clk clock sink
|
||||
add_interface sys_rst reset sink
|
||||
set_interface_property sys_clk EXPORT_OF sys_clk.clk_in
|
||||
set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset
|
||||
|
||||
# memory (int)
|
||||
|
||||
add_instance sys_int_mem altera_avalon_onchip_memory2 15.1
|
||||
set_instance_parameter_value sys_int_mem {dataWidth} {32}
|
||||
set_instance_parameter_value sys_int_mem {dualPort} {0}
|
||||
set_instance_parameter_value sys_int_mem {initMemContent} {0}
|
||||
set_instance_parameter_value sys_int_mem {memorySize} {163840.0}
|
||||
|
||||
add_connection sys_clk.clk sys_int_mem.clk1
|
||||
add_connection sys_clk.clk_reset sys_int_mem.reset1
|
||||
|
||||
# memory (tlb)
|
||||
|
||||
add_instance sys_tlb_mem altera_avalon_onchip_memory2 15.1
|
||||
set_instance_parameter_value sys_tlb_mem {dataWidth} {32}
|
||||
set_instance_parameter_value sys_tlb_mem {dualPort} {1}
|
||||
set_instance_parameter_value sys_tlb_mem {initMemContent} {1}
|
||||
set_instance_parameter_value sys_tlb_mem {memorySize} {163840.0}
|
||||
|
||||
add_connection sys_clk.clk sys_tlb_mem.clk1
|
||||
add_connection sys_clk.clk_reset sys_tlb_mem.reset1
|
||||
add_connection sys_clk.clk sys_tlb_mem.clk2
|
||||
add_connection sys_clk.clk_reset sys_tlb_mem.reset2
|
||||
|
||||
# memory (ddr)
|
||||
|
||||
add_instance sys_ddr3_cntrl altera_emif 15.1
|
||||
set_instance_parameter_value sys_ddr3_cntrl {PROTOCOL_ENUM} {PROTOCOL_DDR3}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_CONFIG_ENUM} {CONFIG_PHY_AND_HARD_CTRL}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_MEM_CLK_FREQ_MHZ} {533.333}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_DEFAULT_REF_CLK_FREQ} {0}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_REF_CLK_FREQ_MHZ} {133.333}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_DEFAULT_IO} {0}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_AC_IO_STD_ENUM} {IO_STD_SSTL_15_C1}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_AC_MODE_ENUM} {CURRENT_ST_12}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_CK_IO_STD_ENUM} {IO_STD_SSTL_15_C1}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_CK_MODE_ENUM} {CURRENT_ST_12}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_DATA_IO_STD_ENUM} {IO_STD_SSTL_15}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_DATA_OUT_MODE_ENUM} {OUT_OCT_34_CAL}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_RZQ_IO_STD_ENUM} {IO_STD_CMOS_15}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_DATA_IN_MODE_ENUM} {IN_OCT_40_CAL}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM} {IO_STD_LVDS}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_FORMAT_ENUM} {MEM_FORMAT_UDIMM}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_DQ_WIDTH} {64}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_ROW_ADDR_WIDTH} {12}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_COL_ADDR_WIDTH} {10}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_BANK_ADDR_WIDTH} {3}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_DM_EN} {1}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TCL} {13}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_WTCL} {9}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TRCD_NS} {10.285}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TRP_NS} {10.285}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {BOARD_DDR3_USER_RCLK_SLEW_RATE} {4.0}
|
||||
set_instance_parameter_value sys_ddr3_cntrl {SHORT_QSYS_INTERFACE_NAMES} {1}
|
||||
|
||||
add_connection sys_clk.clk_reset sys_ddr3_cntrl.global_reset_n
|
||||
add_interface sys_ddr3_cntrl_mem conduit end
|
||||
add_interface sys_ddr3_cntrl_oct conduit end
|
||||
add_interface sys_ddr3_cntrl_pll_ref_clk clock sink
|
||||
|
||||
set_interface_property sys_ddr3_cntrl_mem EXPORT_OF sys_ddr3_cntrl.mem
|
||||
set_interface_property sys_ddr3_cntrl_oct EXPORT_OF sys_ddr3_cntrl.oct
|
||||
set_interface_property sys_ddr3_cntrl_pll_ref_clk EXPORT_OF sys_ddr3_cntrl.pll_ref_clk
|
||||
|
||||
# cpu
|
||||
|
||||
add_instance sys_cpu altera_nios2_gen2 15.1
|
||||
set_instance_parameter_value sys_cpu {setting_support31bitdcachebypass} {0}
|
||||
set_instance_parameter_value sys_cpu {setting_activateTrace} {1}
|
||||
set_instance_parameter_value sys_cpu {mmu_autoAssignTlbPtrSz} {0}
|
||||
set_instance_parameter_value sys_cpu {mmu_TLBMissExcOffset} {4096}
|
||||
set_instance_parameter_value sys_cpu {resetSlave} {sys_ddr3_cntrl_arch.ctrl_amm_0}
|
||||
set_instance_parameter_value sys_cpu {mmu_TLBMissExcSlave} {sys_tlb_mem.s2}
|
||||
set_instance_parameter_value sys_cpu {exceptionSlave} {sys_ddr3_cntrl_arch.ctrl_amm_0}
|
||||
set_instance_parameter_value sys_cpu {breakSlave} {sys_cpu.jtag_debug_module}
|
||||
set_instance_parameter_value sys_cpu {mul_32_impl} {3}
|
||||
set_instance_parameter_value sys_cpu {shift_rot_impl} {0}
|
||||
set_instance_parameter_value sys_cpu {icache_size} {32768}
|
||||
set_instance_parameter_value sys_cpu {icache_numTCIM} {1}
|
||||
set_instance_parameter_value sys_cpu {dcache_size} {32768}
|
||||
set_instance_parameter_value sys_cpu {dcache_numTCDM} {1}
|
||||
set_instance_parameter_value sys_cpu {setting_dc_ecc_present} {0}
|
||||
set_instance_parameter_value sys_cpu {setting_itcm_ecc_present} {0}
|
||||
set_instance_parameter_value sys_cpu {setting_dtcm_ecc_present} {0}
|
||||
|
||||
add_connection sys_clk.clk sys_cpu.clk
|
||||
add_connection sys_clk.clk_reset sys_cpu.reset
|
||||
add_connection sys_cpu.debug_reset_request sys_cpu.reset
|
||||
|
||||
add_connection sys_cpu.instruction_master sys_cpu.debug_mem_slave
|
||||
add_connection sys_cpu.data_master sys_cpu.debug_mem_slave
|
||||
add_connection sys_cpu.instruction_master sys_int_mem.s1
|
||||
add_connection sys_cpu.data_master sys_int_mem.s1
|
||||
add_connection sys_cpu.tightly_coupled_instruction_master_0 sys_tlb_mem.s2
|
||||
add_connection sys_cpu.tightly_coupled_data_master_0 sys_tlb_mem.s1
|
||||
add_connection sys_cpu.instruction_master sys_ddr3_cntrl.ctrl_amm_0
|
||||
add_connection sys_cpu.data_master sys_ddr3_cntrl.ctrl_amm_0
|
||||
|
||||
# ethernet
|
||||
|
||||
add_instance sys_ethernet altera_eth_tse 15.1
|
||||
set_instance_parameter_value sys_ethernet {core_variation} {MAC_PCS}
|
||||
set_instance_parameter_value sys_ethernet {ifGMII} {MII_GMII}
|
||||
set_instance_parameter_value sys_ethernet {transceiver_type} {LVDS_IO}
|
||||
set_instance_parameter_value sys_ethernet {enable_hd_logic} {0}
|
||||
set_instance_parameter_value sys_ethernet {useMDIO} {1}
|
||||
set_instance_parameter_value sys_ethernet {eg_addr} {12}
|
||||
set_instance_parameter_value sys_ethernet {ing_addr} {12}
|
||||
set_instance_parameter_value sys_ethernet {enable_sgmii} {1}
|
||||
|
||||
add_instance sys_ethernet_dma_rx altera_msgdma 15.1
|
||||
set_instance_parameter_value sys_ethernet_dma_rx {MODE} {2}
|
||||
set_instance_parameter_value sys_ethernet_dma_rx {DATA_WIDTH} {64}
|
||||
set_instance_parameter_value sys_ethernet_dma_rx {DATA_FIFO_DEPTH} {256}
|
||||
set_instance_parameter_value sys_ethernet_dma_rx {DESCRIPTOR_FIFO_DEPTH} {512}
|
||||
set_instance_parameter_value sys_ethernet_dma_rx {RESPONSE_PORT} {0}
|
||||
set_instance_parameter_value sys_ethernet_dma_rx {MAX_BYTE} {2048}
|
||||
set_instance_parameter_value sys_ethernet_dma_rx {TRANSFER_TYPE} {Unaligned Accesses}
|
||||
set_instance_parameter_value sys_ethernet_dma_rx {BURST_ENABLE} {1}
|
||||
set_instance_parameter_value sys_ethernet_dma_rx {MAX_BURST_COUNT} {64}
|
||||
set_instance_parameter_value sys_ethernet_dma_rx {ENHANCED_FEATURES} {1}
|
||||
set_instance_parameter_value sys_ethernet_dma_rx {PACKET_ENABLE} {1}
|
||||
set_instance_parameter_value sys_ethernet_dma_rx {ERROR_ENABLE} {1}
|
||||
set_instance_parameter_value sys_ethernet_dma_rx {ERROR_WIDTH} {6}
|
||||
|
||||
add_instance sys_ethernet_dma_tx altera_msgdma 15.1
|
||||
set_instance_parameter_value sys_ethernet_dma_tx {MODE} {1}
|
||||
set_instance_parameter_value sys_ethernet_dma_tx {DATA_WIDTH} {64}
|
||||
set_instance_parameter_value sys_ethernet_dma_tx {DATA_FIFO_DEPTH} {256}
|
||||
set_instance_parameter_value sys_ethernet_dma_tx {DESCRIPTOR_FIFO_DEPTH} {512}
|
||||
set_instance_parameter_value sys_ethernet_dma_tx {MAX_BYTE} {2048}
|
||||
set_instance_parameter_value sys_ethernet_dma_tx {TRANSFER_TYPE} {Unaligned Accesses}
|
||||
set_instance_parameter_value sys_ethernet_dma_tx {BURST_ENABLE} {1}
|
||||
set_instance_parameter_value sys_ethernet_dma_tx {MAX_BURST_COUNT} {64}
|
||||
set_instance_parameter_value sys_ethernet_dma_tx {ENHANCED_FEATURES} {1}
|
||||
set_instance_parameter_value sys_ethernet_dma_tx {PACKET_ENABLE} {1}
|
||||
set_instance_parameter_value sys_ethernet_dma_tx {ERROR_ENABLE} {1}
|
||||
set_instance_parameter_value sys_ethernet_dma_tx {ERROR_WIDTH} {1}
|
||||
|
||||
add_instance sys_ethernet_reset altera_reset_bridge 15.1
|
||||
set_instance_parameter_value sys_ethernet_reset {ACTIVE_LOW_RESET} {0}
|
||||
set_instance_parameter_value sys_ethernet_reset {NUM_RESET_OUTPUTS} {1}
|
||||
|
||||
add_connection sys_clk.clk_reset sys_ethernet.reset_connection
|
||||
add_connection sys_clk.clk_reset sys_ethernet_dma_rx.reset_n
|
||||
add_connection sys_clk.clk_reset sys_ethernet_dma_tx.reset_n
|
||||
add_connection sys_clk.clk_reset sys_ethernet_reset.in_reset
|
||||
add_connection sys_clk.clk sys_ethernet.control_port_clock_connection
|
||||
add_connection sys_clk.clk sys_ethernet.receive_clock_connection
|
||||
add_connection sys_clk.clk sys_ethernet.transmit_clock_connection
|
||||
add_connection sys_clk.clk sys_ethernet_dma_rx.clock
|
||||
add_connection sys_clk.clk sys_ethernet_dma_tx.clock
|
||||
add_connection sys_clk.clk sys_ethernet_reset.clk
|
||||
add_connection sys_cpu.data_master sys_ethernet.control_port
|
||||
add_connection sys_cpu.data_master sys_ethernet_dma_rx.csr
|
||||
add_connection sys_cpu.data_master sys_ethernet_dma_rx.response
|
||||
add_connection sys_cpu.data_master sys_ethernet_dma_rx.descriptor_slave
|
||||
add_connection sys_cpu.data_master sys_ethernet_dma_tx.csr
|
||||
add_connection sys_cpu.data_master sys_ethernet_dma_tx.descriptor_slave
|
||||
add_connection sys_cpu.irq sys_ethernet_dma_rx.csr_irq
|
||||
add_connection sys_cpu.irq sys_ethernet_dma_tx.csr_irq
|
||||
add_connection sys_ethernet.receive sys_ethernet_dma_rx.st_sink
|
||||
add_connection sys_ethernet_dma_tx.st_source sys_ethernet.transmit
|
||||
add_connection sys_ethernet_dma_rx.mm_write sys_ddr3_cntrl.ctrl_amm_0
|
||||
add_connection sys_ethernet_dma_tx.mm_read sys_ddr3_cntrl.ctrl_amm_0
|
||||
add_interface sys_ethernet_reset reset source
|
||||
add_interface sys_ethernet_ref_clk clock sink
|
||||
add_interface sys_ethernet_mdio conduit end
|
||||
add_interface sys_ethernet_sgmii conduit end
|
||||
|
||||
set_interface_property sys_ethernet_mdio EXPORT_OF sys_ethernet.mac_mdio_connection
|
||||
set_interface_property sys_ethernet_ref_clk EXPORT_OF sys_ethernet.pcs_ref_clk_clock_connection
|
||||
set_interface_property sys_ethernet_reset EXPORT_OF sys_ethernet_reset.out_reset
|
||||
set_interface_property sys_ethernet_sgmii EXPORT_OF sys_ethernet.serial_connection
|
||||
|
||||
# sys-id
|
||||
|
||||
add_instance sys_id altera_avalon_sysid_qsys 15.1
|
||||
set_instance_parameter_value sys_id {id} {182193580}
|
||||
|
||||
add_connection sys_clk.clk_reset sys_id.reset
|
||||
add_connection sys_clk.clk sys_id.clk
|
||||
add_connection sys_cpu.data_master sys_id.control_slave
|
||||
|
||||
# timer-1
|
||||
|
||||
add_instance sys_timer_1 altera_avalon_timer 15.1
|
||||
set_instance_parameter_value sys_timer_1 {counterSize} {32}
|
||||
|
||||
add_connection sys_clk.clk_reset sys_timer_1.reset
|
||||
add_connection sys_clk.clk sys_timer_1.clk
|
||||
add_connection sys_cpu.data_master sys_timer_1.s1
|
||||
add_connection sys_cpu.irq sys_timer_1.irq
|
||||
|
||||
# timer-2
|
||||
|
||||
add_instance sys_timer_2 altera_avalon_timer 15.1
|
||||
set_instance_parameter_value sys_timer_2 {counterSize} {32}
|
||||
|
||||
add_connection sys_clk.clk_reset sys_timer_2.reset
|
||||
add_connection sys_clk.clk sys_timer_2.clk
|
||||
add_connection sys_cpu.data_master sys_timer_2.s1
|
||||
add_connection sys_cpu.irq sys_timer_2.irq
|
||||
|
||||
# uart
|
||||
|
||||
add_instance sys_uart altera_avalon_jtag_uart 15.1
|
||||
set_instance_parameter_value sys_uart {allowMultipleConnections} {0}
|
||||
|
||||
add_connection sys_clk.clk_reset sys_uart.reset
|
||||
add_connection sys_clk.clk sys_uart.clk
|
||||
add_connection sys_cpu.data_master sys_uart.avalon_jtag_slave
|
||||
add_connection sys_cpu.irq sys_uart.irq
|
||||
|
||||
# gpio-bd
|
||||
|
||||
add_instance sys_gpio_bd altera_avalon_pio 15.1
|
||||
set_instance_parameter_value sys_gpio_bd {direction} {InOut}
|
||||
set_instance_parameter_value sys_gpio_bd {generateIRQ} {1}
|
||||
set_instance_parameter_value sys_gpio_bd {width} {32}
|
||||
|
||||
add_connection sys_clk.clk_reset sys_gpio_bd.reset
|
||||
add_connection sys_clk.clk sys_gpio_bd.clk
|
||||
add_connection sys_cpu.data_master sys_gpio_bd.s1
|
||||
add_connection sys_cpu.irq sys_gpio_bd.irq
|
||||
add_interface sys_gpio_bd conduit end
|
||||
|
||||
set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection
|
||||
|
||||
# gpio-in
|
||||
|
||||
add_instance sys_gpio_in altera_avalon_pio 15.1
|
||||
set_instance_parameter_value sys_gpio_in {direction} {Input}
|
||||
set_instance_parameter_value sys_gpio_in {generateIRQ} {1}
|
||||
set_instance_parameter_value sys_gpio_in {width} {32}
|
||||
|
||||
add_connection sys_clk.clk_reset sys_gpio_in.reset
|
||||
add_connection sys_clk.clk sys_gpio_in.clk
|
||||
add_connection sys_cpu.data_master sys_gpio_in.s1
|
||||
add_connection sys_cpu.irq sys_gpio_in.irq
|
||||
add_interface sys_gpio_in conduit end
|
||||
|
||||
set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection
|
||||
|
||||
# gpio-out
|
||||
|
||||
add_instance sys_gpio_out altera_avalon_pio 15.1
|
||||
set_instance_parameter_value sys_gpio_out {direction} {Output}
|
||||
set_instance_parameter_value sys_gpio_out {generateIRQ} {0}
|
||||
set_instance_parameter_value sys_gpio_out {width} {32}
|
||||
|
||||
add_connection sys_clk.clk_reset sys_gpio_out.reset
|
||||
add_connection sys_clk.clk sys_gpio_out.clk
|
||||
add_connection sys_cpu.data_master sys_gpio_out.s1
|
||||
add_interface sys_gpio_out conduit end
|
||||
|
||||
set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection
|
||||
|
||||
# spi
|
||||
|
||||
add_instance sys_spi altera_avalon_spi 15.1
|
||||
set_instance_parameter_value sys_spi {clockPhase} {0}
|
||||
set_instance_parameter_value sys_spi {clockPolarity} {0}
|
||||
set_instance_parameter_value sys_spi {dataWidth} {8}
|
||||
set_instance_parameter_value sys_spi {masterSPI} {1}
|
||||
set_instance_parameter_value sys_spi {numberOfSlaves} {8}
|
||||
set_instance_parameter_value sys_spi {targetClockRate} {128000.0}
|
||||
|
||||
add_connection sys_clk.clk_reset sys_spi.reset
|
||||
add_connection sys_clk.clk sys_spi.clk
|
||||
add_connection sys_cpu.data_master sys_spi.spi_control_port
|
||||
add_connection sys_cpu.irq sys_spi.irq
|
||||
add_interface sys_spi conduit end
|
||||
|
||||
set_interface_property sys_spi EXPORT_OF sys_spi.external
|
||||
|
||||
# addresses
|
||||
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_int_mem.s1 baseAddress {0x10140000}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_cpu.debug_mem_slave baseAddress {0x10180800}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_uart.avalon_jtag_slave baseAddress {0x101814f0}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_ethernet.control_port baseAddress {0x10181000}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_ethernet_dma_rx.csr baseAddress {0x101814a0}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_ethernet_dma_rx.response baseAddress {0x101814e0}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_ethernet_dma_rx.descriptor_slave baseAddress {0x10181440}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_ethernet_dma_tx.csr baseAddress {0x10181480}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_ethernet_dma_tx.descriptor_slave baseAddress {0x10181460}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_spi.spi_control_port baseAddress {0x10181400}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_gpio_out.s1 baseAddress {0x10181500}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_gpio_in.s1 baseAddress {0x101814c0}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_gpio_bd.s1 baseAddress {0x101814d0}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_timer_2.s1 baseAddress {0x10181520}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_timer_1.s1 baseAddress {0x10181420}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_id.control_slave baseAddress {0x101814e8}
|
||||
set_connection_parameter_value sys_cpu.instruction_master/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000}
|
||||
set_connection_parameter_value sys_cpu.instruction_master/sys_cpu.debug_mem_slave baseAddress {0x10180800}
|
||||
set_connection_parameter_value sys_cpu.instruction_master/sys_int_mem.s1 baseAddress {0x10140000}
|
||||
set_connection_parameter_value sys_cpu.tightly_coupled_instruction_master_0/sys_tlb_mem.s2 baseAddress {0x10200000}
|
||||
set_connection_parameter_value sys_cpu.tightly_coupled_data_master_0/sys_tlb_mem.s1 baseAddress {0x10200000}
|
||||
set_connection_parameter_value sys_ethernet_dma_tx.mm_read/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000}
|
||||
set_connection_parameter_value sys_ethernet_dma_rx.mm_write/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000}
|
||||
|
||||
set_connection_parameter_value sys_cpu.irq/sys_ethernet_dma_rx.csr_irq irqNumber {0}
|
||||
set_connection_parameter_value sys_cpu.irq/sys_ethernet_dma_tx.csr_irq irqNumber {1}
|
||||
set_connection_parameter_value sys_cpu.irq/sys_uart.irq irqNumber {2}
|
||||
set_connection_parameter_value sys_cpu.irq/sys_timer_2.irq irqNumber {3}
|
||||
set_connection_parameter_value sys_cpu.irq/sys_timer_1.irq irqNumber {4}
|
||||
set_connection_parameter_value sys_cpu.irq/sys_gpio_in.irq irqNumber {5}
|
||||
set_connection_parameter_value sys_cpu.irq/sys_gpio_bd.irq irqNumber {6}
|
||||
set_connection_parameter_value sys_cpu.irq/sys_spi.irq irqNumber {7}
|
||||
|
||||
# interrupts
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
|
||||
source ../common/daq2_qsys.tcl
|
||||
|
||||
save_system "system_bd.qsys"
|
||||
|
||||
|
|
@ -0,0 +1,299 @@
|
|||
|
||||
# transmit-path (refclk)
|
||||
|
||||
add_instance xcvr_tx_ref_clk altera_clock_bridge 15.1
|
||||
set_instance_parameter_value xcvr_tx_ref_clk {EXPLICIT_CLOCK_RATE} {500000000.0}
|
||||
|
||||
# transmit-path (pll-core)
|
||||
|
||||
add_instance xcvr_tx_pll altera_iopll 15.1
|
||||
add_instance xcvr_tx_pll_reconfig altera_pll_reconfig 15.1
|
||||
set_instance_parameter_value xcvr_tx_pll {gui_en_reconf} {1}
|
||||
set_instance_parameter_value xcvr_tx_pll {gui_reference_clock_frequency} {500.0}
|
||||
set_instance_parameter_value xcvr_tx_pll {gui_use_locked} {0}
|
||||
set_instance_parameter_value xcvr_tx_pll {gui_output_clock_frequency0} {250.0}
|
||||
|
||||
# transmit-path (pll-atx)
|
||||
|
||||
add_instance xcvr_tx_lane_pll altera_xcvr_atx_pll_a10 15.1
|
||||
set_instance_parameter_value xcvr_tx_lane_pll {enable_pll_reconfig} {1}
|
||||
set_instance_parameter_value xcvr_tx_lane_pll {rcfg_separate_avmm_busy} {1}
|
||||
set_instance_parameter_value xcvr_tx_lane_pll {set_capability_reg_enable} {1}
|
||||
set_instance_parameter_value xcvr_tx_lane_pll {set_csr_soft_logic_enable} {1}
|
||||
set_instance_parameter_value xcvr_tx_lane_pll {set_output_clock_frequency} {5000.0}
|
||||
set_instance_parameter_value xcvr_tx_lane_pll {set_auto_reference_clock_frequency} {500.0}
|
||||
|
||||
# receive-path (refclk)
|
||||
|
||||
add_instance xcvr_rx_ref_clk altera_clock_bridge 15.1
|
||||
set_instance_parameter_value xcvr_rx_ref_clk {EXPLICIT_CLOCK_RATE} {500000000.0}
|
||||
|
||||
# receive-path (pll-core)
|
||||
|
||||
add_instance xcvr_rx_pll altera_iopll 15.1
|
||||
add_instance xcvr_rx_pll_reconfig altera_pll_reconfig 15.1
|
||||
set_instance_parameter_value xcvr_rx_pll {gui_en_reconf} {1}
|
||||
set_instance_parameter_value xcvr_rx_pll {gui_reference_clock_frequency} {500.0}
|
||||
set_instance_parameter_value xcvr_rx_pll {gui_use_locked} {0}
|
||||
set_instance_parameter_value xcvr_rx_pll {gui_output_clock_frequency0} {250.0}
|
||||
|
||||
# transceiver-control
|
||||
|
||||
add_instance axi_jesd_xcvr axi_jesd_xcvr 1.0
|
||||
set_instance_parameter_value axi_jesd_xcvr {DEVICE_TYPE} {0}
|
||||
set_instance_parameter_value axi_jesd_xcvr {TX_NUM_OF_LANES} {4}
|
||||
set_instance_parameter_value axi_jesd_xcvr {RX_NUM_OF_LANES} {4}
|
||||
|
||||
# transceiver-reset
|
||||
|
||||
add_instance xcvr_rst_cntrl altera_xcvr_reset_control 15.1
|
||||
set_instance_parameter_value xcvr_rst_cntrl {CHANNELS} {4}
|
||||
set_instance_parameter_value xcvr_rst_cntrl {SYS_CLK_IN_MHZ} {100}
|
||||
set_instance_parameter_value xcvr_rst_cntrl {TX_PLL_ENABLE} {1}
|
||||
set_instance_parameter_value xcvr_rst_cntrl {T_PLL_POWERDOWN} {1000}
|
||||
set_instance_parameter_value xcvr_rst_cntrl {TX_ENABLE} {1}
|
||||
set_instance_parameter_value xcvr_rst_cntrl {T_TX_ANALOGRESET} {70000}
|
||||
set_instance_parameter_value xcvr_rst_cntrl {T_TX_DIGITALRESET} {70000}
|
||||
set_instance_parameter_value xcvr_rst_cntrl {gui_pll_cal_busy} {1}
|
||||
set_instance_parameter_value xcvr_rst_cntrl {RX_ENABLE} {1}
|
||||
set_instance_parameter_value xcvr_rst_cntrl {T_RX_ANALOGRESET} {70000}
|
||||
set_instance_parameter_value xcvr_rst_cntrl {T_RX_DIGITALRESET} {4000}
|
||||
|
||||
# transceiver-core (+ jesd)
|
||||
|
||||
add_instance xcvr_core altera_jesd204 15.1
|
||||
set_instance_parameter_value xcvr_core {wrapper_opt} {base_phy}
|
||||
set_instance_parameter_value xcvr_core {DATA_PATH} {RX_TX}
|
||||
set_instance_parameter_value xcvr_core {lane_rate} {10000.0}
|
||||
set_instance_parameter_value xcvr_core {PCS_CONFIG} {JESD_PCS_CFG2}
|
||||
set_instance_parameter_value xcvr_core {bonded_mode} {non_bonded}
|
||||
set_instance_parameter_value xcvr_core {REFCLK_FREQ} {500.0}
|
||||
set_instance_parameter_value xcvr_core {pll_reconfig_enable} {1}
|
||||
set_instance_parameter_value xcvr_core {set_capability_reg_enable} {1}
|
||||
set_instance_parameter_value xcvr_core {set_csr_soft_logic_enable} {1}
|
||||
set_instance_parameter_value xcvr_core {L} {4}
|
||||
set_instance_parameter_value xcvr_core {M} {2}
|
||||
set_instance_parameter_value xcvr_core {GUI_EN_CFG_F} {1}
|
||||
set_instance_parameter_value xcvr_core {GUI_CFG_F} {1}
|
||||
set_instance_parameter_value xcvr_core {N} {16}
|
||||
set_instance_parameter_value xcvr_core {S} {1}
|
||||
set_instance_parameter_value xcvr_core {K} {32}
|
||||
set_instance_parameter_value xcvr_core {SCR} {1}
|
||||
set_instance_parameter_value xcvr_core {HD} {1}
|
||||
|
||||
# transceiver + jesd interfaces
|
||||
|
||||
add_connection xcvr_tx_ref_clk.out_clk xcvr_tx_pll.refclk
|
||||
add_connection xcvr_tx_ref_clk.out_clk xcvr_tx_lane_pll.pll_refclk0
|
||||
add_interface tx_ref_clk clock sink
|
||||
set_interface_property tx_ref_clk EXPORT_OF xcvr_tx_ref_clk.in_clk
|
||||
|
||||
add_connection xcvr_rx_ref_clk.out_clk xcvr_rx_pll.refclk
|
||||
add_connection xcvr_rx_ref_clk.out_clk xcvr_core.rx_pll_ref_clk
|
||||
add_interface rx_ref_clk clock sink
|
||||
set_interface_property rx_ref_clk EXPORT_OF xcvr_rx_ref_clk.in_clk
|
||||
|
||||
add_connection sys_clk.clk_reset xcvr_tx_pll.reset
|
||||
add_connection axi_jesd_xcvr.if_rst xcvr_tx_pll.reset
|
||||
add_connection xcvr_tx_pll.outclk0 xcvr_core.txlink_clk
|
||||
add_connection sys_clk.clk_reset xcvr_tx_pll_reconfig.mgmt_reset
|
||||
add_connection sys_clk.clk xcvr_tx_pll_reconfig.mgmt_clk
|
||||
add_connection sys_cpu.data_master xcvr_tx_pll_reconfig.mgmt_avalon_slave
|
||||
add_connection xcvr_tx_pll_reconfig.reconfig_from_pll xcvr_tx_pll.reconfig_from_pll
|
||||
add_connection xcvr_tx_pll.reconfig_to_pll xcvr_tx_pll_reconfig.reconfig_to_pll
|
||||
|
||||
add_connection sys_clk.clk_reset xcvr_rx_pll.reset
|
||||
add_connection axi_jesd_xcvr.if_rst xcvr_rx_pll.reset
|
||||
add_connection xcvr_rx_pll.outclk0 xcvr_core.rxlink_clk
|
||||
add_connection sys_clk.clk_reset xcvr_rx_pll_reconfig.mgmt_reset
|
||||
add_connection sys_clk.clk xcvr_rx_pll_reconfig.mgmt_clk
|
||||
add_connection sys_cpu.data_master xcvr_rx_pll_reconfig.mgmt_avalon_slave
|
||||
add_connection xcvr_rx_pll.reconfig_from_pll xcvr_rx_pll_reconfig.reconfig_from_pll
|
||||
add_connection xcvr_rx_pll_reconfig.reconfig_to_pll xcvr_rx_pll.reconfig_to_pll
|
||||
|
||||
add_connection xcvr_rst_cntrl.pll_powerdown xcvr_tx_lane_pll.pll_powerdown
|
||||
add_connection xcvr_tx_lane_pll.pll_cal_busy xcvr_rst_cntrl.pll_cal_busy
|
||||
add_connection xcvr_tx_lane_pll.pll_locked xcvr_rst_cntrl.pll_locked
|
||||
add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_core.tx_serial_clk0_ch0
|
||||
add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_core.tx_serial_clk0_ch1
|
||||
add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_core.tx_serial_clk0_ch2
|
||||
add_connection xcvr_tx_lane_pll.tx_serial_clk xcvr_core.tx_serial_clk0_ch3
|
||||
add_connection sys_clk.clk_reset xcvr_tx_lane_pll.reconfig_reset0
|
||||
add_connection sys_clk.clk xcvr_tx_lane_pll.reconfig_clk0
|
||||
add_connection sys_cpu.data_master xcvr_tx_lane_pll.reconfig_avmm0
|
||||
|
||||
add_connection sys_clk.clk_reset xcvr_rst_cntrl.reset
|
||||
add_connection sys_clk.clk xcvr_rst_cntrl.clock
|
||||
add_connection xcvr_rst_cntrl.tx_analogreset xcvr_core.tx_analogreset
|
||||
add_connection xcvr_rst_cntrl.tx_digitalreset xcvr_core.tx_digitalreset
|
||||
add_connection xcvr_rst_cntrl.tx_cal_busy xcvr_core.tx_cal_busy
|
||||
add_connection xcvr_rst_cntrl.rx_analogreset xcvr_core.rx_analogreset
|
||||
add_connection xcvr_rst_cntrl.rx_digitalreset xcvr_core.rx_digitalreset
|
||||
add_connection xcvr_rst_cntrl.rx_cal_busy xcvr_core.rx_cal_busy
|
||||
add_connection xcvr_rst_cntrl.rx_is_lockedtodata xcvr_core.rx_islockedtodata
|
||||
add_connection axi_jesd_xcvr.if_rst xcvr_rst_cntrl.reset
|
||||
add_connection xcvr_tx_pll.outclk0 axi_jesd_xcvr.if_tx_clk
|
||||
add_connection axi_jesd_xcvr.if_tx_rstn xcvr_core.txlink_rst_n
|
||||
add_connection axi_jesd_xcvr.if_tx_ready xcvr_rst_cntrl.tx_ready
|
||||
add_connection axi_jesd_xcvr.if_tx_ip_sysref xcvr_core.tx_sysref
|
||||
add_connection axi_jesd_xcvr.if_tx_ip_sync xcvr_core.sync_n
|
||||
add_connection axi_jesd_xcvr.if_tx_ip_avl xcvr_core.jesd204_tx_link
|
||||
add_connection xcvr_rx_pll.outclk0 axi_jesd_xcvr.if_rx_clk
|
||||
add_connection axi_jesd_xcvr.if_rx_rstn xcvr_core.rxlink_rst_n
|
||||
add_connection axi_jesd_xcvr.if_rx_ready xcvr_rst_cntrl.rx_ready
|
||||
add_connection axi_jesd_xcvr.if_rx_ip_sysref xcvr_core.rx_sysref
|
||||
add_connection axi_jesd_xcvr.if_rx_ip_sync xcvr_core.rx_dev_sync_n
|
||||
add_connection axi_jesd_xcvr.if_rx_ip_sof xcvr_core.rx_sof
|
||||
add_connection xcvr_core.jesd204_rx_link axi_jesd_xcvr.if_rx_ip_avl
|
||||
add_connection sys_clk.clk_reset axi_jesd_xcvr.s_axi_reset
|
||||
add_connection sys_clk.clk axi_jesd_xcvr.s_axi_clock
|
||||
add_connection sys_cpu.data_master axi_jesd_xcvr.s_axi
|
||||
add_interface tx_sysref conduit end
|
||||
add_interface tx_sync conduit end
|
||||
add_interface rx_sysref conduit end
|
||||
add_interface rx_sync conduit end
|
||||
set_interface_property tx_sysref EXPORT_OF axi_jesd_xcvr.if_tx_ext_sysref_in
|
||||
set_interface_property tx_sync EXPORT_OF axi_jesd_xcvr.if_tx_sync
|
||||
set_interface_property rx_sysref EXPORT_OF axi_jesd_xcvr.if_rx_ext_sysref_in
|
||||
set_interface_property rx_sync EXPORT_OF axi_jesd_xcvr.if_rx_sync
|
||||
|
||||
add_connection sys_clk.clk_reset xcvr_core.reconfig_reset
|
||||
add_connection sys_clk.clk xcvr_core.reconfig_clk
|
||||
add_connection sys_clk.clk_reset xcvr_core.jesd204_tx_avs_rst_n
|
||||
add_connection sys_clk.clk xcvr_core.jesd204_tx_avs_clk
|
||||
add_connection sys_clk.clk_reset xcvr_core.jesd204_rx_avs_rst_n
|
||||
add_connection sys_clk.clk xcvr_core.jesd204_rx_avs_clk
|
||||
add_connection xcvr_core.alldev_lane_aligned xcvr_core.dev_lane_aligned
|
||||
add_connection xcvr_core.tx_dev_sync_n xcvr_core.mdev_sync_n
|
||||
add_connection sys_cpu.data_master xcvr_core.reconfig_avmm
|
||||
add_connection sys_cpu.data_master xcvr_core.jesd204_tx_avs
|
||||
add_connection sys_cpu.data_master xcvr_core.jesd204_rx_avs
|
||||
add_interface tx_data conduit end
|
||||
add_interface rx_data conduit end
|
||||
set_interface_property tx_data EXPORT_OF xcvr_core.tx_serial_data
|
||||
set_interface_property rx_data EXPORT_OF xcvr_core.rx_serial_data
|
||||
|
||||
# ad9144
|
||||
|
||||
add_instance axi_ad9144_core axi_ad9144 1.0
|
||||
set_instance_parameter_value axi_ad9144_core {QUAD_OR_DUAL_N} {0}
|
||||
|
||||
add_connection xcvr_tx_pll.outclk0 axi_ad9144_core.if_tx_clk
|
||||
add_connection axi_jesd_xcvr.if_tx_data axi_ad9144_core.if_tx_data
|
||||
add_connection sys_clk.clk_reset axi_ad9144_core.s_axi_reset
|
||||
add_connection sys_clk.clk axi_ad9144_core.s_axi_clock
|
||||
add_connection sys_cpu.data_master axi_ad9144_core.s_axi
|
||||
|
||||
# ad9144-unpack
|
||||
|
||||
add_instance util_ad9144_upack util_upack 1.0
|
||||
set_instance_parameter_value util_ad9144_upack {CHANNEL_DATA_WIDTH} {64}
|
||||
set_instance_parameter_value util_ad9144_upack {NUM_OF_CHANNELS} {2}
|
||||
|
||||
add_connection xcvr_tx_pll.outclk0 util_ad9144_upack.if_dac_clk
|
||||
add_connection axi_ad9144_core.dac_ch_0 util_ad9144_upack.dac_ch_0
|
||||
add_connection axi_ad9144_core.dac_ch_1 util_ad9144_upack.dac_ch_1
|
||||
|
||||
# ad9144-dma
|
||||
|
||||
add_instance axi_ad9144_dma axi_dmac 1.0
|
||||
set_instance_parameter_value axi_ad9144_dma {DMA_DATA_WIDTH_SRC} {128}
|
||||
set_instance_parameter_value axi_ad9144_dma {DMA_DATA_WIDTH_DEST} {128}
|
||||
set_instance_parameter_value axi_ad9144_dma {DMA_2D_TRANSFER} {0}
|
||||
set_instance_parameter_value axi_ad9144_dma {DMA_TYPE_DEST} {2}
|
||||
set_instance_parameter_value axi_ad9144_dma {DMA_TYPE_SRC} {0}
|
||||
|
||||
add_connection xcvr_tx_pll.outclk0 axi_ad9144_dma.if_fifo_rd_clk
|
||||
add_connection util_ad9144_upack.if_dac_valid axi_ad9144_dma.if_fifo_rd_en
|
||||
add_connection util_ad9144_upack.if_dac_data axi_ad9144_dma.if_fifo_rd_dout
|
||||
add_connection axi_ad9144_dma.if_fifo_rd_underflow axi_ad9144_core.if_dac_dunf
|
||||
add_connection sys_clk.clk_reset axi_ad9144_dma.s_axi_reset
|
||||
add_connection sys_clk.clk axi_ad9144_dma.s_axi_clock
|
||||
add_connection sys_cpu.data_master axi_ad9144_dma.s_axi
|
||||
add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9144_dma.m_src_axi_reset
|
||||
add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9144_dma.m_src_axi_clock
|
||||
add_connection axi_ad9144_dma.m_src_axi sys_ddr3_cntrl.ctrl_amm_0
|
||||
add_connection sys_cpu.irq axi_ad9144_dma.interrupt_sender
|
||||
|
||||
# ad9680
|
||||
|
||||
add_instance axi_ad9680_core axi_ad9680 1.0
|
||||
|
||||
add_connection xcvr_rx_pll.outclk0 axi_ad9680_core.if_rx_clk
|
||||
add_connection axi_jesd_xcvr.if_rx_data axi_ad9680_core.if_rx_data
|
||||
add_connection sys_clk.clk_reset axi_ad9680_core.s_axi_reset
|
||||
add_connection sys_clk.clk axi_ad9680_core.s_axi_clock
|
||||
add_connection sys_cpu.data_master axi_ad9680_core.s_axi
|
||||
|
||||
# ad9680-pack
|
||||
|
||||
add_instance util_ad9680_cpack util_cpack 1.0
|
||||
set_instance_parameter_value util_ad9680_cpack {CHANNEL_DATA_WIDTH} {64}
|
||||
set_instance_parameter_value util_ad9680_cpack {NUM_OF_CHANNELS} {2}
|
||||
|
||||
add_connection sys_clk.clk_reset util_ad9680_cpack.if_adc_rst
|
||||
add_connection sys_ddr3_cntrl.emif_usr_reset_n util_ad9680_cpack.if_adc_rst
|
||||
add_connection xcvr_rx_pll.outclk0 util_ad9680_cpack.if_adc_clk
|
||||
add_connection axi_ad9680_core.adc_ch_0 util_ad9680_cpack.adc_ch_0
|
||||
add_connection axi_ad9680_core.adc_ch_1 util_ad9680_cpack.adc_ch_1
|
||||
|
||||
# ad9680-fifo
|
||||
|
||||
add_instance ad9680_adcfifo util_adcfifo 1.0
|
||||
set_instance_parameter_value ad9680_adcfifo {ADC_DATA_WIDTH} {128}
|
||||
set_instance_parameter_value ad9680_adcfifo {DMA_DATA_WIDTH} {128}
|
||||
set_instance_parameter_value ad9680_adcfifo {DMA_ADDRESS_WIDTH} {16}
|
||||
|
||||
add_connection sys_clk.clk_reset ad9680_adcfifo.if_adc_rst
|
||||
add_connection sys_ddr3_cntrl.emif_usr_reset_n ad9680_adcfifo.if_adc_rst
|
||||
add_connection xcvr_rx_pll.outclk0 ad9680_adcfifo.if_adc_clk
|
||||
add_connection util_ad9680_cpack.if_adc_valid ad9680_adcfifo.if_adc_wr
|
||||
add_connection util_ad9680_cpack.if_adc_data ad9680_adcfifo.if_adc_wdata
|
||||
add_connection sys_ddr3_cntrl.emif_usr_clk ad9680_adcfifo.if_dma_clk
|
||||
|
||||
# ad9680-dma
|
||||
|
||||
add_instance axi_ad9680_dma axi_dmac 1.0
|
||||
set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_SRC} {128}
|
||||
set_instance_parameter_value axi_ad9680_dma {DMA_DATA_WIDTH_DEST} {128}
|
||||
set_instance_parameter_value axi_ad9680_dma {DMA_LENGTH_WIDTH} {24}
|
||||
set_instance_parameter_value axi_ad9680_dma {DMA_2D_TRANSFER} {0}
|
||||
set_instance_parameter_value axi_ad9680_dma {SYNC_TRANSFER_START} {1}
|
||||
set_instance_parameter_value axi_ad9680_dma {CYCLIC} {0}
|
||||
set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_DEST} {0}
|
||||
set_instance_parameter_value axi_ad9680_dma {DMA_TYPE_SRC} {1}
|
||||
|
||||
add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.if_s_axis_aclk
|
||||
add_connection ad9680_adcfifo.if_dma_wr axi_ad9680_dma.if_s_axis_valid
|
||||
add_connection ad9680_adcfifo.if_dma_wdata axi_ad9680_dma.if_s_axis_data
|
||||
add_connection ad9680_adcfifo.if_dma_wready axi_ad9680_dma.if_s_axis_ready
|
||||
add_connection ad9680_adcfifo.if_dma_xfer_req axi_ad9680_dma.if_s_axis_xfer_req
|
||||
add_connection ad9680_adcfifo.if_adc_wovf axi_ad9680_core.if_adc_dovf
|
||||
add_connection sys_clk.clk_reset axi_ad9680_dma.s_axi_reset
|
||||
add_connection sys_clk.clk axi_ad9680_dma.s_axi_clock
|
||||
add_connection sys_cpu.data_master axi_ad9680_dma.s_axi
|
||||
add_connection sys_ddr3_cntrl.emif_usr_reset_n axi_ad9680_dma.m_dest_axi_reset
|
||||
add_connection sys_ddr3_cntrl.emif_usr_clk axi_ad9680_dma.m_dest_axi_clock
|
||||
add_connection axi_ad9680_dma.m_dest_axi sys_ddr3_cntrl.ctrl_amm_0
|
||||
add_connection sys_cpu.irq axi_ad9680_dma.interrupt_sender
|
||||
|
||||
# addresses
|
||||
|
||||
set_connection_parameter_value sys_cpu.data_master/xcvr_rx_pll_reconfig.mgmt_avalon_slave baseAddress {0x1003d800}
|
||||
set_connection_parameter_value sys_cpu.data_master/xcvr_tx_pll_reconfig.mgmt_avalon_slave baseAddress {0x1003d000}
|
||||
set_connection_parameter_value sys_cpu.data_master/xcvr_tx_lane_pll.reconfig_avmm0 baseAddress {0x1003c000}
|
||||
set_connection_parameter_value sys_cpu.data_master/axi_ad9680_dma.s_axi baseAddress {0x10034000}
|
||||
set_connection_parameter_value sys_cpu.data_master/axi_ad9680_core.s_axi baseAddress {0x10010000}
|
||||
set_connection_parameter_value sys_cpu.data_master/axi_ad9144_dma.s_axi baseAddress {0x10038000}
|
||||
set_connection_parameter_value sys_cpu.data_master/axi_ad9144_core.s_axi baseAddress {0x10020000}
|
||||
set_connection_parameter_value sys_cpu.data_master/xcvr_core.reconfig_avmm baseAddress {0x10030000}
|
||||
set_connection_parameter_value sys_cpu.data_master/axi_jesd_xcvr.s_axi baseAddress {0x10000000}
|
||||
set_connection_parameter_value sys_cpu.data_master/xcvr_core.jesd204_tx_avs baseAddress {0x1003e000}
|
||||
set_connection_parameter_value sys_cpu.data_master/xcvr_core.jesd204_rx_avs baseAddress {0x1003e400}
|
||||
set_connection_parameter_value axi_ad9680_dma.m_dest_axi/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000}
|
||||
set_connection_parameter_value axi_ad9144_dma.m_src_axi/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000}
|
||||
|
||||
# interrupts
|
||||
|
||||
set_connection_parameter_value sys_cpu.irq/axi_ad9680_dma.interrupt_sender irqNumber {10}
|
||||
set_connection_parameter_value sys_cpu.irq/axi_ad9144_dma.interrupt_sender irqNumber {11}
|
||||
Loading…
Reference in New Issue