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license: Update old license headers

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Istvan Csomortani 2018-03-14 14:27:27 +02:00 committed by István Csomortáni
parent ee79ba5686
commit 34994222b4
3 changed files with 88 additions and 95 deletions
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60
library/axi_ad9361/altera/axi_ad9361_alt_lvds_rx.v
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@ -1,37 +1,35 @@
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc. // Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// //
// All rights reserved. // In this HDL repository, there are many different and unique modules, consisting
// // of various HDL (Verilog or VHDL) components. The individual modules are
// Redistribution and use in source and binary forms, with or without modification, // developed independently, and may be accompanied by separate and unique license
// are permitted provided that the following conditions are met: // terms.
// - Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. // The user should read each of these license terms, and understand the
// - Redistributions in binary form must reproduce the above copyright // freedoms and responsabilities that he or she has by using this source/core.
// notice, this list of conditions and the following disclaimer in //
// the documentation and/or other materials provided with the // This core is distributed in the hope that it will be useful, but WITHOUT ANY
// distribution. // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// - Neither the name of Analog Devices, Inc. nor the names of its // A PARTICULAR PURPOSE.
// contributors may be used to endorse or promote products derived //
// from this software without specific prior written permission. // Redistribution and use of source or resulting binaries, with or without modification
// - The use of this software may or may not infringe the patent rights // of this file, are permitted under one of the following two license terms:
// of one or more patent holders. This license does not release you //
// from the requirement that you obtain separate licenses from these // 1. The GNU General Public License version 2 as published by the
// patent holders to use this software. // Free Software Foundation, which can be found in the top level directory
// - Use of the software either in source or binary form, must be run // of this repository (LICENSE_GPL2), and also online at:
// on or directly connected to an Analog Devices Inc. component. // <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
// //
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // OR
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A //
// PARTICULAR PURPOSE ARE DISCLAIMED. // 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
// //
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************

60
library/axi_ad9361/altera/axi_ad9361_alt_lvds_tx.v
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@ -1,37 +1,35 @@
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc. // Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// //
// All rights reserved. // In this HDL repository, there are many different and unique modules, consisting
// // of various HDL (Verilog or VHDL) components. The individual modules are
// Redistribution and use in source and binary forms, with or without modification, // developed independently, and may be accompanied by separate and unique license
// are permitted provided that the following conditions are met: // terms.
// - Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. // The user should read each of these license terms, and understand the
// - Redistributions in binary form must reproduce the above copyright // freedoms and responsabilities that he or she has by using this source/core.
// notice, this list of conditions and the following disclaimer in //
// the documentation and/or other materials provided with the // This core is distributed in the hope that it will be useful, but WITHOUT ANY
// distribution. // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// - Neither the name of Analog Devices, Inc. nor the names of its // A PARTICULAR PURPOSE.
// contributors may be used to endorse or promote products derived //
// from this software without specific prior written permission. // Redistribution and use of source or resulting binaries, with or without modification
// - The use of this software may or may not infringe the patent rights // of this file, are permitted under one of the following two license terms:
// of one or more patent holders. This license does not release you //
// from the requirement that you obtain separate licenses from these // 1. The GNU General Public License version 2 as published by the
// patent holders to use this software. // Free Software Foundation, which can be found in the top level directory
// - Use of the software either in source or binary form, must be run // of this repository (LICENSE_GPL2), and also online at:
// on or directly connected to an Analog Devices Inc. component. // <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
// //
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // OR
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A //
// PARTICULAR PURPOSE ARE DISCLAIMED. // 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
// //
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************

63
library/util_clkdiv/util_clkdiv_alt.v
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@ -1,47 +1,44 @@
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc. // Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// //
// All rights reserved. // In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
// //
// Redistribution and use in source and binary forms, with or without modification, // The user should read each of these license terms, and understand the
// are permitted provided that the following conditions are met: // freedoms and responsabilities that he or she has by using this source/core.
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
// //
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // This core is distributed in the hope that it will be useful, but WITHOUT ANY
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// PARTICULAR PURPOSE ARE DISCLAIMED. // A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
// //
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// Divides the input clock to SEL_0_DIV if clk_sel is 0 or SEL_1_DIV if
// clk_sel is 1. Provides a glitch free output clock
// IP uses BUFR/BUFGCE_DIV and BUFGMUX_CTRL primitives
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
`timescale 1ns/100ps `timescale 1ns/100ps
// Divides the input clock to SEL_0_DIV if clk_sel is 0 or SEL_1_DIV if
// clk_sel is 1. Provides a glitch free output clock
// IP uses BUFR/BUFGCE_DIV and BUFGMUX_CTRL primitives
module util_clkdiv_alt #( module util_clkdiv_alt #(
parameter SIM_DEVICE = "CYCLONE5", parameter SIM_DEVICE = "CYCLONE5",
parameter CLOCK_TYPE = "Global Clock") ( parameter CLOCK_TYPE = "Global Clock") (