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adi_ip.pl: Add support for creating multi busses 

This patch adds a helper function that allows to create multiple ports for
a single set of underlying signals. This is useful when the number of ports
is a configuration parameter. It sort of allows the emulation of port
arrays without having to have on set of input/output signals for each port,
instead the signals are shared by all ports.

The following snippet illustrates how this can for example be used to
generate multiple AXI-Streaming ports from a single set of signals.

<verilog>
	module #(
		parameter NUM_PORTS = 2
	) (
		input [NUM_PORTS*32-1:0] data,
		input [NUM_PORTS-1:0] valid,
		output [NUM_PORTS-1:0] ready,
	);
	...
	endmodule
</verilog>

<tcl>
	adi_add_multi_bus 8 "data" "slave" \
		"xilinx.com:interface:axis_rtl:1.0" \
		"xilinx.com:interface:axis:1.0" \
		[list \
			{ "data" "TDATA" 32} \
			{ "valid" "TVALID" 1} \
			{ "ready" "TREADY" 1} \
	  ] \
	  "NUM_PORTS > {i})"
</tcl>

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2016-09-09 14:07:16 +02:00
parent e4a4a7a1b8
commit 341a695163
1 changed files with 25 additions and 0 deletions
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25
library/scripts/adi_ip.tcl
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@ -80,6 +80,31 @@ proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
}
}
proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
for {set i 0} {$i < 8} {incr i} {
set bus_name [format "%s%d" $bus_name_prefix $i]
set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
set_property "BUS_TYPE_VLNV" $bus_type $bus
set_property "INTERFACE_MODE" $mode $bus
if {$dependency ne ""} {
set bus_dependency [string map [list "{i}" $i] $dependency]
set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
}
foreach port_map $port_maps {
lassign $port_map phys logic width
set map [ipx::add_port_map $phys $bus]
set_property "PHYSICAL_NAME" $phys $map
set_property "LOGICAL_NAME" $logic $map
set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
}
}
}
proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]