projects- ultrascale+

main
Rejeesh Kutty 2016-09-30 11:52:40 -04:00
parent 6b956066ef
commit 33f9ed33c7
1 changed files with 2 additions and 2 deletions

View File

@ -86,8 +86,8 @@ proc adi_project_create {project_name {mode 0}} {
set sys_zynq 1
}
if [regexp "_zcu102$" $project_name] {
set p_device "xczu9eg-ffvb1156-1-i-EVAL"
set p_board "not-applicable"
set p_device "xczu9eg-ffvb1156-1-i-es1"
set p_board "xilinx.com:zcu102:part0:1.2"
set sys_zynq 2
}