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axi_i2s: Set unused signals to 0 

Fixes warnings from the tools about undriven signals.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2014-09-30 11:22:14 +02:00
parent e5a9633f84
commit 32dd1d1a4a
1 changed files with 27 additions and 0 deletions
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27
library/axi_i2s_adi/axi_i2s_adi.vhd
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@ -200,6 +200,10 @@ begin
); );
end generate; end generate;
no_streaming_dma_tx_gen: if C_DMA_TYPE /= 0 or C_HAS_TX /= 1 generate
S_AXIS_TREADY <= '0';
end generate;
streaming_dma_rx_gen: if C_DMA_TYPE = 0 and C_HAS_RX = 1 generate streaming_dma_rx_gen: if C_DMA_TYPE = 0 and C_HAS_RX = 1 generate
rx_fifo : entity axi_streaming_dma_rx_fifo rx_fifo : entity axi_streaming_dma_rx_fifo
generic map( generic map(
@ -229,6 +233,15 @@ begin
M_AXIS_TDATA(7 downto 0) <= (others => '0'); M_AXIS_TDATA(7 downto 0) <= (others => '0');
end generate; end generate;
no_streaming_dma_rx_gen: if C_DMA_TYPE /= 0 or C_HAS_RX /= 1 generate
M_AXIS_TDATA <= (others => '0');
M_AXIS_TLAST <= '0';
M_AXIS_TVALID <= '0';
M_AXIS_TKEEP <= (others => '0');
end generate;
pl330_dma_tx_gen: if C_DMA_TYPE = 1 and C_HAS_TX = 1 generate pl330_dma_tx_gen: if C_DMA_TYPE = 1 and C_HAS_TX = 1 generate
tx_fifo_stb <= '1' when wr_addr = 11 and wr_stb = '1' else '0'; tx_fifo_stb <= '1' when wr_addr = 11 and wr_stb = '1' else '0';
@ -263,6 +276,12 @@ begin
); );
end generate; end generate;
no_pl330_dma_tx_gen: if C_DMA_TYPE /= 1 or C_HAS_TX /= 1 generate
DMA_REQ_TX_DAREADY <= '0';
DMA_REQ_TX_DRVALID <= '0';
DMA_REQ_TX_DRTYPE <= (others => '0');
DMA_REQ_TX_DRLAST <= '0';
end generate;
pl330_dma_rx_gen: if C_DMA_TYPE = 1 and C_HAS_RX = 1 generate pl330_dma_rx_gen: if C_DMA_TYPE = 1 and C_HAS_RX = 1 generate
rx_fifo_ack <= '1' when rd_addr = 10 and rd_ack = '1' else '0'; rx_fifo_ack <= '1' when rd_addr = 10 and rd_ack = '1' else '0';
@ -296,6 +315,14 @@ begin
drtype => DMA_REQ_RX_DRTYPE, drtype => DMA_REQ_RX_DRTYPE,
drlast => DMA_REQ_RX_DRLAST drlast => DMA_REQ_RX_DRLAST
); );
end generate;
no_pl330_dma_rx_gen: if C_DMA_TYPE /= 1 or C_HAS_RX /= 1 generate
DMA_REQ_RX_DAREADY <= '0';
DMA_REQ_RX_DRVALID <= '0';
DMA_REQ_RX_DRTYPE <= (others => '0');
DMA_REQ_RX_DRLAST <= '0';
end generate; end generate;
ctrl : entity i2s_controller ctrl : entity i2s_controller