Merge branch 'master' of https://github.com/analogdevicesinc/hdl
Adrian Costina
commit
32c2abf4e6
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@ -0,0 +1,10 @@
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*.data
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||||||
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*.xpr
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||||||
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*.log
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||||||
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component.xml
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||||||
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*.jou
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||||||
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xgui
|
||||||
|
*.runs
|
||||||
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*.srcs
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||||||
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*.sdk
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||||||
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.Xil
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@ -0,0 +1,8 @@
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||||||
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||||||
|
source $ad_hdl_dir/projects/common/ac701/ac701_system_bd.tcl
|
||||||
|
set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect
|
||||||
|
set_property -dict [list CONFIG.NUM_SI {8}] $axi_mem_interconnect
|
||||||
|
set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_interconnect
|
||||||
|
set_property -dict [list CONFIG.NUM_PORTS {10}] $sys_concat_intc
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||||||
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||||||
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||||||
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@ -0,0 +1,14 @@
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||||||
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||||||
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||||||
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||||||
|
source ../../scripts/adi_env.tcl
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||||||
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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||||||
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||||||
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adi_project_create adv7511_ac701
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||||||
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adi_project_files adv7511_ac701 [list \
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||||||
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"system_top.v" \
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||||||
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"$ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc" ]
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||||||
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||||||
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adi_project_run adv7511_ac701
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||||||
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||||||
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||||||
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@ -0,0 +1,199 @@
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||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
// Copyright 2011(c) Analog Devices, Inc.
|
||||||
|
//
|
||||||
|
// All rights reserved.
|
||||||
|
//
|
||||||
|
// Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
// are permitted provided that the following conditions are met:
|
||||||
|
// - Redistributions of source code must retain the above copyright
|
||||||
|
// notice, this list of conditions and the following disclaimer.
|
||||||
|
// - Redistributions in binary form must reproduce the above copyright
|
||||||
|
// notice, this list of conditions and the following disclaimer in
|
||||||
|
// the documentation and/or other materials provided with the
|
||||||
|
// distribution.
|
||||||
|
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||||
|
// contributors may be used to endorse or promote products derived
|
||||||
|
// from this software without specific prior written permission.
|
||||||
|
// - The use of this software may or may not infringe the patent rights
|
||||||
|
// of one or more patent holders. This license does not release you
|
||||||
|
// from the requirement that you obtain separate licenses from these
|
||||||
|
// patent holders to use this software.
|
||||||
|
// - Use of the software either in source or binary form, must be run
|
||||||
|
// on or directly connected to an Analog Devices Inc. component.
|
||||||
|
//
|
||||||
|
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||||
|
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||||
|
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
//
|
||||||
|
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||||
|
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||||
|
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||||
|
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||||
|
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||||
|
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
|
module system_top (
|
||||||
|
|
||||||
|
sys_rst,
|
||||||
|
sys_clk_p,
|
||||||
|
sys_clk_n,
|
||||||
|
|
||||||
|
uart_sin,
|
||||||
|
uart_sout,
|
||||||
|
|
||||||
|
ddr3_addr,
|
||||||
|
ddr3_ba,
|
||||||
|
ddr3_cas_n,
|
||||||
|
ddr3_ck_n,
|
||||||
|
ddr3_ck_p,
|
||||||
|
ddr3_cke,
|
||||||
|
ddr3_cs_n,
|
||||||
|
ddr3_dm,
|
||||||
|
ddr3_dq,
|
||||||
|
ddr3_dqs_n,
|
||||||
|
ddr3_dqs_p,
|
||||||
|
ddr3_odt,
|
||||||
|
ddr3_ras_n,
|
||||||
|
ddr3_reset_n,
|
||||||
|
ddr3_we_n,
|
||||||
|
|
||||||
|
phy_reset_n,
|
||||||
|
phy_mdc,
|
||||||
|
phy_mdio,
|
||||||
|
phy_tx_clk,
|
||||||
|
phy_tx_ctrl,
|
||||||
|
phy_tx_data,
|
||||||
|
phy_rx_clk,
|
||||||
|
phy_rx_ctrl,
|
||||||
|
phy_rx_data,
|
||||||
|
|
||||||
|
fan_pwm,
|
||||||
|
|
||||||
|
gpio_lcd,
|
||||||
|
gpio_led,
|
||||||
|
gpio_sw,
|
||||||
|
|
||||||
|
iic_rstn,
|
||||||
|
iic_scl,
|
||||||
|
iic_sda,
|
||||||
|
|
||||||
|
hdmi_out_clk,
|
||||||
|
hdmi_hsync,
|
||||||
|
hdmi_vsync,
|
||||||
|
hdmi_data_e,
|
||||||
|
hdmi_data,
|
||||||
|
|
||||||
|
spdif);
|
||||||
|
|
||||||
|
input sys_rst;
|
||||||
|
input sys_clk_p;
|
||||||
|
input sys_clk_n;
|
||||||
|
|
||||||
|
input uart_sin;
|
||||||
|
output uart_sout;
|
||||||
|
|
||||||
|
output [13:0] ddr3_addr;
|
||||||
|
output [ 2:0] ddr3_ba;
|
||||||
|
output ddr3_cas_n;
|
||||||
|
output [ 0:0] ddr3_ck_n;
|
||||||
|
output [ 0:0] ddr3_ck_p;
|
||||||
|
output [ 0:0] ddr3_cke;
|
||||||
|
output [ 0:0] ddr3_cs_n;
|
||||||
|
output [ 7:0] ddr3_dm;
|
||||||
|
inout [63:0] ddr3_dq;
|
||||||
|
inout [ 7:0] ddr3_dqs_n;
|
||||||
|
inout [ 7:0] ddr3_dqs_p;
|
||||||
|
output [ 0:0] ddr3_odt;
|
||||||
|
output ddr3_ras_n;
|
||||||
|
output ddr3_reset_n;
|
||||||
|
output ddr3_we_n;
|
||||||
|
|
||||||
|
output phy_reset_n;
|
||||||
|
output phy_mdc;
|
||||||
|
inout phy_mdio;
|
||||||
|
output phy_tx_clk;
|
||||||
|
output phy_tx_ctrl;
|
||||||
|
output [ 3:0] phy_tx_data;
|
||||||
|
input phy_rx_clk;
|
||||||
|
input phy_rx_ctrl;
|
||||||
|
input [ 3:0] phy_rx_data;
|
||||||
|
|
||||||
|
output fan_pwm;
|
||||||
|
|
||||||
|
inout [ 6:0] gpio_lcd;
|
||||||
|
inout [ 3:0] gpio_led;
|
||||||
|
inout [ 8:0] gpio_sw;
|
||||||
|
|
||||||
|
output iic_rstn;
|
||||||
|
inout iic_scl;
|
||||||
|
inout iic_sda;
|
||||||
|
|
||||||
|
output hdmi_out_clk;
|
||||||
|
output hdmi_hsync;
|
||||||
|
output hdmi_vsync;
|
||||||
|
output hdmi_data_e;
|
||||||
|
output [23:0] hdmi_data;
|
||||||
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|
||||||
|
output spdif;
|
||||||
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|
||||||
|
// assignments
|
||||||
|
|
||||||
|
assign mgt_clk_sel = 2'd0;
|
||||||
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|
||||||
|
// instantiations
|
||||||
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|
||||||
|
system_wrapper i_system_wrapper (
|
||||||
|
.ddr3_addr (ddr3_addr),
|
||||||
|
.ddr3_ba (ddr3_ba),
|
||||||
|
.ddr3_cas_n (ddr3_cas_n),
|
||||||
|
.ddr3_ck_n (ddr3_ck_n),
|
||||||
|
.ddr3_ck_p (ddr3_ck_p),
|
||||||
|
.ddr3_cke (ddr3_cke),
|
||||||
|
.ddr3_cs_n (ddr3_cs_n),
|
||||||
|
.ddr3_dm (ddr3_dm),
|
||||||
|
.ddr3_dq (ddr3_dq),
|
||||||
|
.ddr3_dqs_n (ddr3_dqs_n),
|
||||||
|
.ddr3_dqs_p (ddr3_dqs_p),
|
||||||
|
.ddr3_odt (ddr3_odt),
|
||||||
|
.ddr3_ras_n (ddr3_ras_n),
|
||||||
|
.ddr3_reset_n (ddr3_reset_n),
|
||||||
|
.ddr3_we_n (ddr3_we_n),
|
||||||
|
.fan_pwm (fan_pwm),
|
||||||
|
.gpio_lcd_tri_io (gpio_lcd),
|
||||||
|
.gpio_led_tri_io (gpio_led),
|
||||||
|
.gpio_sw_tri_io (gpio_sw),
|
||||||
|
.hdmi_data (hdmi_data),
|
||||||
|
.hdmi_data_e (hdmi_data_e),
|
||||||
|
.hdmi_hsync (hdmi_hsync),
|
||||||
|
.hdmi_out_clk (hdmi_out_clk),
|
||||||
|
.hdmi_vsync (hdmi_vsync),
|
||||||
|
.iic_main_scl_io (iic_scl),
|
||||||
|
.iic_main_sda_io (iic_sda),
|
||||||
|
.iic_rstn (iic_rstn),
|
||||||
|
.mdio_io (phy_mdio),
|
||||||
|
.mdio_mdc (phy_mdc),
|
||||||
|
.phy_rst_n (phy_reset_n),
|
||||||
|
.rgmii_rd (phy_rx_data),
|
||||||
|
.rgmii_rx_ctl (phy_rx_ctrl),
|
||||||
|
.rgmii_rxc (phy_rx_clk),
|
||||||
|
.rgmii_td (phy_tx_data),
|
||||||
|
.rgmii_tx_ctl (phy_tx_ctrl),
|
||||||
|
.rgmii_txc (phy_tx_clk),
|
||||||
|
.spdif (spdif),
|
||||||
|
.sys_clk_n (sys_clk_n),
|
||||||
|
.sys_clk_p (sys_clk_p),
|
||||||
|
.sys_rst (sys_rst),
|
||||||
|
.uart_sin (uart_sin),
|
||||||
|
.uart_sout (uart_sout));
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
|
@ -0,0 +1,8 @@
|
||||||
|
|
||||||
|
source $ad_hdl_dir/projects/common/kc705/kc705_system_bd.tcl
|
||||||
|
set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect
|
||||||
|
set_property -dict [list CONFIG.NUM_SI {8}] $axi_mem_interconnect
|
||||||
|
set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_interconnect
|
||||||
|
set_property -dict [list CONFIG.NUM_PORTS {8}] $sys_concat_intc
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,14 @@
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
source ../../scripts/adi_env.tcl
|
||||||
|
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||||
|
|
||||||
|
adi_project_create adv7511_kc705
|
||||||
|
adi_project_files adv7511_kc705 [list \
|
||||||
|
"system_top.v" \
|
||||||
|
"$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ]
|
||||||
|
|
||||||
|
adi_project_run adv7511_kc705
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,210 @@
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
// Copyright 2011(c) Analog Devices, Inc.
|
||||||
|
//
|
||||||
|
// All rights reserved.
|
||||||
|
//
|
||||||
|
// Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
// are permitted provided that the following conditions are met:
|
||||||
|
// - Redistributions of source code must retain the above copyright
|
||||||
|
// notice, this list of conditions and the following disclaimer.
|
||||||
|
// - Redistributions in binary form must reproduce the above copyright
|
||||||
|
// notice, this list of conditions and the following disclaimer in
|
||||||
|
// the documentation and/or other materials provided with the
|
||||||
|
// distribution.
|
||||||
|
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||||
|
// contributors may be used to endorse or promote products derived
|
||||||
|
// from this software without specific prior written permission.
|
||||||
|
// - The use of this software may or may not infringe the patent rights
|
||||||
|
// of one or more patent holders. This license does not release you
|
||||||
|
// from the requirement that you obtain separate licenses from these
|
||||||
|
// patent holders to use this software.
|
||||||
|
// - Use of the software either in source or binary form, must be run
|
||||||
|
// on or directly connected to an Analog Devices Inc. component.
|
||||||
|
//
|
||||||
|
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||||
|
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||||
|
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
//
|
||||||
|
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||||
|
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||||
|
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||||
|
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||||
|
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||||
|
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
|
module system_top (
|
||||||
|
|
||||||
|
sys_rst,
|
||||||
|
sys_clk_p,
|
||||||
|
sys_clk_n,
|
||||||
|
|
||||||
|
uart_sin,
|
||||||
|
uart_sout,
|
||||||
|
|
||||||
|
ddr3_1_n,
|
||||||
|
ddr3_1_p,
|
||||||
|
ddr3_reset_n,
|
||||||
|
ddr3_addr,
|
||||||
|
ddr3_ba,
|
||||||
|
ddr3_cas_n,
|
||||||
|
ddr3_ras_n,
|
||||||
|
ddr3_we_n,
|
||||||
|
ddr3_ck_n,
|
||||||
|
ddr3_ck_p,
|
||||||
|
ddr3_cke,
|
||||||
|
ddr3_cs_n,
|
||||||
|
ddr3_dm,
|
||||||
|
ddr3_dq,
|
||||||
|
ddr3_dqs_n,
|
||||||
|
ddr3_dqs_p,
|
||||||
|
ddr3_odt,
|
||||||
|
|
||||||
|
mdio_mdc,
|
||||||
|
mdio_mdio_io,
|
||||||
|
mii_rst_n,
|
||||||
|
mii_col,
|
||||||
|
mii_crs,
|
||||||
|
mii_rx_clk,
|
||||||
|
mii_rx_er,
|
||||||
|
mii_rx_dv,
|
||||||
|
mii_rxd,
|
||||||
|
mii_tx_clk,
|
||||||
|
mii_tx_en,
|
||||||
|
mii_txd,
|
||||||
|
|
||||||
|
fan_pwm,
|
||||||
|
|
||||||
|
gpio_lcd,
|
||||||
|
gpio_led,
|
||||||
|
gpio_sw,
|
||||||
|
|
||||||
|
iic_rstn,
|
||||||
|
iic_scl,
|
||||||
|
iic_sda,
|
||||||
|
|
||||||
|
hdmi_out_clk,
|
||||||
|
hdmi_hsync,
|
||||||
|
hdmi_vsync,
|
||||||
|
hdmi_data_e,
|
||||||
|
hdmi_data,
|
||||||
|
|
||||||
|
spdif);
|
||||||
|
|
||||||
|
input sys_rst;
|
||||||
|
input sys_clk_p;
|
||||||
|
input sys_clk_n;
|
||||||
|
|
||||||
|
input uart_sin;
|
||||||
|
output uart_sout;
|
||||||
|
|
||||||
|
output [ 2:0] ddr3_1_n;
|
||||||
|
output [ 1:0] ddr3_1_p;
|
||||||
|
output ddr3_reset_n;
|
||||||
|
output [13:0] ddr3_addr;
|
||||||
|
output [ 2:0] ddr3_ba;
|
||||||
|
output ddr3_cas_n;
|
||||||
|
output ddr3_ras_n;
|
||||||
|
output ddr3_we_n;
|
||||||
|
output [ 0:0] ddr3_ck_n;
|
||||||
|
output [ 0:0] ddr3_ck_p;
|
||||||
|
output [ 0:0] ddr3_cke;
|
||||||
|
output [ 0:0] ddr3_cs_n;
|
||||||
|
output [ 7:0] ddr3_dm;
|
||||||
|
inout [63:0] ddr3_dq;
|
||||||
|
inout [ 7:0] ddr3_dqs_n;
|
||||||
|
inout [ 7:0] ddr3_dqs_p;
|
||||||
|
output [ 0:0] ddr3_odt;
|
||||||
|
|
||||||
|
output mdio_mdc;
|
||||||
|
inout mdio_mdio_io;
|
||||||
|
output mii_rst_n;
|
||||||
|
input mii_col;
|
||||||
|
input mii_crs;
|
||||||
|
input mii_rx_clk;
|
||||||
|
input mii_rx_er;
|
||||||
|
input mii_rx_dv;
|
||||||
|
input [ 3:0] mii_rxd;
|
||||||
|
input mii_tx_clk;
|
||||||
|
output mii_tx_en;
|
||||||
|
output [ 3:0] mii_txd;
|
||||||
|
|
||||||
|
output fan_pwm;
|
||||||
|
|
||||||
|
inout [ 6:0] gpio_lcd;
|
||||||
|
inout [ 7:0] gpio_led;
|
||||||
|
inout [ 8:0] gpio_sw;
|
||||||
|
|
||||||
|
output iic_rstn;
|
||||||
|
inout iic_scl;
|
||||||
|
inout iic_sda;
|
||||||
|
|
||||||
|
output hdmi_out_clk;
|
||||||
|
output hdmi_hsync;
|
||||||
|
output hdmi_vsync;
|
||||||
|
output hdmi_data_e;
|
||||||
|
output [15:0] hdmi_data;
|
||||||
|
|
||||||
|
output spdif;
|
||||||
|
|
||||||
|
// instantiations
|
||||||
|
|
||||||
|
system_wrapper i_system_wrapper (
|
||||||
|
.ddr3_1_n (ddr3_1_n),
|
||||||
|
.ddr3_1_p (ddr3_1_p),
|
||||||
|
.ddr3_addr (ddr3_addr),
|
||||||
|
.ddr3_ba (ddr3_ba),
|
||||||
|
.ddr3_cas_n (ddr3_cas_n),
|
||||||
|
.ddr3_ck_n (ddr3_ck_n),
|
||||||
|
.ddr3_ck_p (ddr3_ck_p),
|
||||||
|
.ddr3_cke (ddr3_cke),
|
||||||
|
.ddr3_cs_n (ddr3_cs_n),
|
||||||
|
.ddr3_dm (ddr3_dm),
|
||||||
|
.ddr3_dq (ddr3_dq),
|
||||||
|
.ddr3_dqs_n (ddr3_dqs_n),
|
||||||
|
.ddr3_dqs_p (ddr3_dqs_p),
|
||||||
|
.ddr3_odt (ddr3_odt),
|
||||||
|
.ddr3_ras_n (ddr3_ras_n),
|
||||||
|
.ddr3_reset_n (ddr3_reset_n),
|
||||||
|
.ddr3_we_n (ddr3_we_n),
|
||||||
|
.fan_pwm (fan_pwm),
|
||||||
|
.gpio_lcd_tri_io (gpio_lcd),
|
||||||
|
.gpio_led_tri_io (gpio_led),
|
||||||
|
.gpio_sw_tri_io (gpio_sw),
|
||||||
|
.hdmi_data (hdmi_data),
|
||||||
|
.hdmi_data_e (hdmi_data_e),
|
||||||
|
.hdmi_hsync (hdmi_hsync),
|
||||||
|
.hdmi_out_clk (hdmi_out_clk),
|
||||||
|
.hdmi_vsync (hdmi_vsync),
|
||||||
|
.iic_main_scl_io (iic_scl),
|
||||||
|
.iic_main_sda_io (iic_sda),
|
||||||
|
.iic_rstn (iic_rstn),
|
||||||
|
.mdio_mdc (mdio_mdc),
|
||||||
|
.mdio_mdio_io (mdio_mdio_io),
|
||||||
|
.mii_col (mii_col),
|
||||||
|
.mii_crs (mii_crs),
|
||||||
|
.mii_rst_n (mii_rst_n),
|
||||||
|
.mii_rx_clk (mii_rx_clk),
|
||||||
|
.mii_rx_dv (mii_rx_dv),
|
||||||
|
.mii_rx_er (mii_rx_er),
|
||||||
|
.mii_rxd (mii_rxd),
|
||||||
|
.mii_tx_clk (mii_tx_clk),
|
||||||
|
.mii_tx_en (mii_tx_en),
|
||||||
|
.mii_txd (mii_txd),
|
||||||
|
.spdif (spdif),
|
||||||
|
.sys_clk_n (sys_clk_n),
|
||||||
|
.sys_clk_p (sys_clk_p),
|
||||||
|
.sys_rst (sys_rst),
|
||||||
|
.uart_sin (uart_sin),
|
||||||
|
.uart_sout (uart_sout));
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
|
@ -0,0 +1,463 @@
|
||||||
|
|
||||||
|
set sys_rst [create_bd_port -dir I -type rst sys_rst]
|
||||||
|
set sys_clk_p [create_bd_port -dir I sys_clk_p]
|
||||||
|
set sys_clk_n [create_bd_port -dir I sys_clk_n]
|
||||||
|
set fan_pwm [create_bd_port -dir O fan_pwm]
|
||||||
|
|
||||||
|
set ddr3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3]
|
||||||
|
|
||||||
|
set phy_rst_n [create_bd_port -dir O -type rst phy_rst_n]
|
||||||
|
set mdio [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_io:1.0 mdio]
|
||||||
|
set rgmii [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 rgmii]
|
||||||
|
|
||||||
|
set gpio_sw [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_sw]
|
||||||
|
set gpio_led [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_led]
|
||||||
|
set gpio_lcd [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_lcd]
|
||||||
|
|
||||||
|
set iic_rstn [create_bd_port -dir O iic_rstn]
|
||||||
|
set iic_main [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main]
|
||||||
|
|
||||||
|
set uart_sin [create_bd_port -dir I uart_sin]
|
||||||
|
set uart_sout [create_bd_port -dir O uart_sout]
|
||||||
|
|
||||||
|
set hdmi_out_clk [create_bd_port -dir O hdmi_out_clk]
|
||||||
|
set hdmi_hsync [create_bd_port -dir O hdmi_hsync]
|
||||||
|
set hdmi_vsync [create_bd_port -dir O hdmi_vsync]
|
||||||
|
set hdmi_data_e [create_bd_port -dir O hdmi_data_e]
|
||||||
|
set hdmi_data [create_bd_port -dir O -from 23 -to 0 hdmi_data]
|
||||||
|
|
||||||
|
# spdif audio
|
||||||
|
|
||||||
|
set spdif [create_bd_port -dir O spdif]
|
||||||
|
|
||||||
|
set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] $sys_rst
|
||||||
|
|
||||||
|
# instance: microblaze - processor
|
||||||
|
|
||||||
|
set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.2 sys_mb]
|
||||||
|
set_property -dict [list CONFIG.C_FAULT_TOLERANT {0}] $sys_mb
|
||||||
|
set_property -dict [list CONFIG.C_D_AXI {1}] $sys_mb
|
||||||
|
set_property -dict [list CONFIG.C_D_LMB {1}] $sys_mb
|
||||||
|
set_property -dict [list CONFIG.C_I_LMB {1}] $sys_mb
|
||||||
|
set_property -dict [list CONFIG.C_DEBUG_ENABLED {1}] $sys_mb
|
||||||
|
set_property -dict [list CONFIG.C_USE_ICACHE {1}] $sys_mb
|
||||||
|
set_property -dict [list CONFIG.C_ICACHE_LINE_LEN {8}] $sys_mb
|
||||||
|
set_property -dict [list CONFIG.C_ICACHE_ALWAYS_USED {1}] $sys_mb
|
||||||
|
set_property -dict [list CONFIG.C_ICACHE_FORCE_TAG_LUTRAM {1}] $sys_mb
|
||||||
|
set_property -dict [list CONFIG.C_USE_DCACHE {1}] $sys_mb
|
||||||
|
set_property -dict [list CONFIG.C_DCACHE_LINE_LEN {8}] $sys_mb
|
||||||
|
set_property -dict [list CONFIG.C_DCACHE_ALWAYS_USED {1}] $sys_mb
|
||||||
|
set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb
|
||||||
|
set_property -dict [list CONFIG.C_ICACHE_HIGHADDR {0xBFFFFFFF}] $sys_mb
|
||||||
|
set_property -dict [list CONFIG.C_ICACHE_BASEADDR {0x80000000}] $sys_mb
|
||||||
|
set_property -dict [list CONFIG.C_DCACHE_HIGHADDR {0xBFFFFFFF}] $sys_mb
|
||||||
|
set_property -dict [list CONFIG.C_DCACHE_BASEADDR {0x80000000}] $sys_mb
|
||||||
|
|
||||||
|
# instance: microblaze - local memory & bus
|
||||||
|
|
||||||
|
set sys_dlmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_dlmb]
|
||||||
|
set sys_ilmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_ilmb]
|
||||||
|
|
||||||
|
set sys_dlmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_dlmb_cntlr]
|
||||||
|
set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr
|
||||||
|
|
||||||
|
set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr]
|
||||||
|
set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr
|
||||||
|
|
||||||
|
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.1 sys_lmb_bram]
|
||||||
|
set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram
|
||||||
|
|
||||||
|
# instance: microblaze- mdm
|
||||||
|
|
||||||
|
set sys_mb_debug [create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.0 sys_mb_debug]
|
||||||
|
set_property -dict [list CONFIG.C_USE_UART {1}] $sys_mb_debug
|
||||||
|
|
||||||
|
# instance: system reset/clocks
|
||||||
|
|
||||||
|
set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
|
||||||
|
|
||||||
|
set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 sys_const_vcc]
|
||||||
|
|
||||||
|
# instance: ddr (mig)
|
||||||
|
|
||||||
|
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.0 axi_ddr_cntrl]
|
||||||
|
set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
|
||||||
|
file copy -force $ad_hdl_dir/projects/common/ac701/ac701_system_mig.prj "$axi_ddr_cntrl_dir/"
|
||||||
|
set_property -dict [list CONFIG.XML_INPUT_FILE {ac701_system_mig.prj}] $axi_ddr_cntrl
|
||||||
|
|
||||||
|
# instance: axi interconnect (lite)
|
||||||
|
|
||||||
|
set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect]
|
||||||
|
set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect
|
||||||
|
|
||||||
|
# instance: axi interconnect
|
||||||
|
|
||||||
|
set axi_mem_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_interconnect]
|
||||||
|
set_property -dict [list CONFIG.NUM_SI {8}] $axi_mem_interconnect
|
||||||
|
set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_interconnect
|
||||||
|
set_property -dict [list CONFIG.ENABLE_ADVANCED_OPTIONS {1}] $axi_mem_interconnect
|
||||||
|
set_property -dict [list CONFIG.XBAR_DATA_WIDTH {512}] $axi_mem_interconnect
|
||||||
|
|
||||||
|
# instance: default peripherals
|
||||||
|
|
||||||
|
set sys_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_ethernet_clkgen]
|
||||||
|
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_ethernet_clkgen
|
||||||
|
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125.000}] $sys_ethernet_clkgen
|
||||||
|
|
||||||
|
set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:6.0 axi_ethernet]
|
||||||
|
set_property -dict [list CONFIG.PHY_TYPE {RGMII}] $axi_ethernet
|
||||||
|
|
||||||
|
set axi_ethernet_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_dma]
|
||||||
|
set_property -dict [list CONFIG.c_include_mm2s_dre {1}] $axi_ethernet_dma
|
||||||
|
set_property -dict [list CONFIG.c_sg_use_stsapp_length {1}] $axi_ethernet_dma
|
||||||
|
set_property -dict [list CONFIG.c_include_s2mm_dre {1}] $axi_ethernet_dma
|
||||||
|
|
||||||
|
set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
|
||||||
|
|
||||||
|
set axi_uart [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart]
|
||||||
|
set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart
|
||||||
|
|
||||||
|
set axi_timer [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer]
|
||||||
|
|
||||||
|
set axi_gpio_lcd [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_lcd]
|
||||||
|
set_property -dict [list CONFIG.C_GPIO_WIDTH {7}] $axi_gpio_lcd
|
||||||
|
set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_lcd
|
||||||
|
|
||||||
|
set axi_gpio_sw_led [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_sw_led]
|
||||||
|
set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio_sw_led
|
||||||
|
set_property -dict [list CONFIG.C_GPIO_WIDTH {9}] $axi_gpio_sw_led
|
||||||
|
set_property -dict [list CONFIG.C_GPIO2_WIDTH {4}] $axi_gpio_sw_led
|
||||||
|
set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_sw_led
|
||||||
|
|
||||||
|
# instance: interrupt
|
||||||
|
|
||||||
|
set axi_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc]
|
||||||
|
set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc
|
||||||
|
|
||||||
|
set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_concat_intc]
|
||||||
|
set_property -dict [list CONFIG.NUM_PORTS {10}] $sys_concat_intc
|
||||||
|
|
||||||
|
# hdmi peripherals
|
||||||
|
|
||||||
|
set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
|
||||||
|
set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
|
||||||
|
|
||||||
|
set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.1 axi_hdmi_dma]
|
||||||
|
set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
|
||||||
|
set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
|
||||||
|
set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
|
||||||
|
|
||||||
|
# audio peripherals
|
||||||
|
|
||||||
|
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
|
||||||
|
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
|
||||||
|
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
|
||||||
|
|
||||||
|
set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
|
||||||
|
set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core
|
||||||
|
set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
|
||||||
|
set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core
|
||||||
|
set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core
|
||||||
|
|
||||||
|
set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_spdif_tx_dma]
|
||||||
|
set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma
|
||||||
|
set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_spdif_tx_dma
|
||||||
|
|
||||||
|
# connections
|
||||||
|
|
||||||
|
connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins sys_mb_debug/Debug_SYS_Rst]
|
||||||
|
connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins sys_rstgen/mb_debug_sys_rst]
|
||||||
|
|
||||||
|
connect_bd_net -net sys_rstgen_mb_reset [get_bd_pins sys_rstgen/mb_reset]
|
||||||
|
connect_bd_net -net sys_rstgen_mb_reset [get_bd_pins sys_mb/Reset]
|
||||||
|
|
||||||
|
connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_rstgen/bus_struct_reset]
|
||||||
|
connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_dlmb/SYS_Rst]
|
||||||
|
connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_ilmb/SYS_Rst]
|
||||||
|
connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_dlmb_cntlr/LMB_Rst]
|
||||||
|
connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_ilmb_cntlr/LMB_Rst]
|
||||||
|
|
||||||
|
# microblaze local memory
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb [get_bd_intf_pins sys_dlmb/LMB_Sl_0] [get_bd_intf_pins sys_dlmb_cntlr/SLMB]
|
||||||
|
connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb [get_bd_intf_pins sys_ilmb/LMB_Sl_0] [get_bd_intf_pins sys_ilmb_cntlr/SLMB]
|
||||||
|
connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb_bram [get_bd_intf_pins sys_dlmb_cntlr/BRAM_PORT] [get_bd_intf_pins sys_lmb_bram/BRAM_PORTA]
|
||||||
|
connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb_bram [get_bd_intf_pins sys_ilmb_cntlr/BRAM_PORT] [get_bd_intf_pins sys_lmb_bram/BRAM_PORTB]
|
||||||
|
connect_bd_intf_net -intf_net sys_mb_dlmb [get_bd_intf_pins sys_mb/DLMB] [get_bd_intf_pins sys_dlmb/LMB_M]
|
||||||
|
connect_bd_intf_net -intf_net sys_mb_ilmb [get_bd_intf_pins sys_mb/ILMB] [get_bd_intf_pins sys_ilmb/LMB_M]
|
||||||
|
|
||||||
|
# microblaze debug & interrupt
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net sys_mb_debug_intf [get_bd_intf_pins sys_mb_debug/MBDEBUG_0] [get_bd_intf_pins sys_mb/DEBUG]
|
||||||
|
connect_bd_intf_net -intf_net sys_mb_interrupt [get_bd_intf_pins axi_intc/interrupt] [get_bd_intf_pins sys_mb/INTERRUPT]
|
||||||
|
connect_bd_net -net sys_concat_intc_intr [get_bd_pins sys_concat_intc/dout] [get_bd_pins axi_intc/intr]
|
||||||
|
|
||||||
|
# defaults (peripherals)
|
||||||
|
|
||||||
|
connect_bd_net -net axi_ddr_cntrl_mmcm_locked [get_bd_pins axi_ddr_cntrl/mmcm_locked] [get_bd_pins sys_rstgen/dcm_locked]
|
||||||
|
|
||||||
|
set sys_100m_resetn_source [get_bd_pins sys_rstgen/peripheral_aresetn]
|
||||||
|
set sys_200m_resetn_source [get_bd_pins sys_rstgen/interconnect_aresetn]
|
||||||
|
set sys_100m_clk_source [get_bd_pins axi_ddr_cntrl/ui_clk]
|
||||||
|
set sys_200m_clk_source [get_bd_pins axi_ddr_cntrl/ui_addn_clk_0]
|
||||||
|
|
||||||
|
connect_bd_net -net sys_100m_resetn $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_200m_resetn $sys_200m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_clk $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_200m_clk $sys_200m_clk_source
|
||||||
|
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/ACLK] $sys_100m_clk_source
|
||||||
|
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins sys_mb_debug/S_AXI_ARESETN]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ddr_cntrl/aresetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ethernet/s_axi_lite_resetn] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_uart/s_axi_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_timer/s_axi_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_intc/s_axi_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_gpio_lcd/s_axi_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_gpio_sw_led/s_axi_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_main/s_axi_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ethernet_dma/axi_resetn]
|
||||||
|
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins sys_rstgen/slowest_sync_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins sys_mb/Clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins sys_mb_debug/S_AXI_ACLK]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins sys_dlmb/LMB_Clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ilmb/LMB_Clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins sys_dlmb_cntlr/LMB_Clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ilmb_cntlr/LMB_Clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet/s_axi_lite_clk] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet/axis_clk] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_dma/m_axi_sg_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_dma/m_axi_mm2s_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_dma/m_axi_s2mm_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_dma/s_axi_lite_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_uart/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_timer/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_intc/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_gpio_lcd/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_gpio_sw_led/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_main/s_axi_aclk]
|
||||||
|
|
||||||
|
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ethernet/ref_clk] $sys_200m_clk_source
|
||||||
|
|
||||||
|
# defaults (interconnect - processor)
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_s00 [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DP]
|
||||||
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m00 [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins sys_mb_debug/S_AXI]
|
||||||
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m01 [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_ethernet/s_axi]
|
||||||
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m02 [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins axi_uart/s_axi]
|
||||||
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m03 [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_timer/s_axi]
|
||||||
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m04 [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_intc/s_axi]
|
||||||
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m05 [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins axi_gpio_lcd/s_axi]
|
||||||
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m06 [get_bd_intf_pins axi_cpu_interconnect/M06_AXI] [get_bd_intf_pins axi_gpio_sw_led/s_axi]
|
||||||
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07 [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_iic_main/s_axi]
|
||||||
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13 [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_ethernet_dma/S_AXI_LITE]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M01_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M02_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M03_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M04_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M05_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/S00_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M01_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M02_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M03_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M04_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M05_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source
|
||||||
|
|
||||||
|
# defaults (interconnect - memory)
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net axi_mem_interconnect_m00 [get_bd_intf_pins axi_mem_interconnect/M00_AXI] [get_bd_intf_pins axi_ddr_cntrl/S_AXI]
|
||||||
|
connect_bd_intf_net -intf_net axi_mem_interconnect_s00 [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DC]
|
||||||
|
connect_bd_intf_net -intf_net axi_mem_interconnect_s01 [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins sys_mb/M_AXI_IC]
|
||||||
|
connect_bd_intf_net -intf_net axi_mem_interconnect_s05 [get_bd_intf_pins axi_mem_interconnect/S05_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_SG]
|
||||||
|
connect_bd_intf_net -intf_net axi_mem_interconnect_s06 [get_bd_intf_pins axi_mem_interconnect/S06_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_MM2S]
|
||||||
|
connect_bd_intf_net -intf_net axi_mem_interconnect_s07 [get_bd_intf_pins axi_mem_interconnect/S07_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_S2MM]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S01_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S05_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S06_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S07_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/M00_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S00_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S01_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S05_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S06_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S07_ACLK] $sys_100m_clk_source
|
||||||
|
|
||||||
|
# ethernet & ethernet dma
|
||||||
|
|
||||||
|
connect_bd_net -net sys_200m_clk [get_bd_pins sys_ethernet_clkgen/clk_in1]
|
||||||
|
connect_bd_net -net sys_ethernet_clkgen_clk [get_bd_pins sys_ethernet_clkgen/clk_out1] [get_bd_pins axi_ethernet/gtx_clk]
|
||||||
|
|
||||||
|
connect_bd_net -net axi_ethernet_dma_txd_rstn [get_bd_pins axi_ethernet/axi_txd_arstn] [get_bd_pins axi_ethernet_dma/mm2s_prmry_reset_out_n]
|
||||||
|
connect_bd_net -net axi_ethernet_dma_txc_rstn [get_bd_pins axi_ethernet/axi_txc_arstn] [get_bd_pins axi_ethernet_dma/mm2s_cntrl_reset_out_n]
|
||||||
|
connect_bd_net -net axi_ethernet_dma_rxd_rstn [get_bd_pins axi_ethernet/axi_rxd_arstn] [get_bd_pins axi_ethernet_dma/s2mm_prmry_reset_out_n]
|
||||||
|
connect_bd_net -net axi_ethernet_dma_rxs_rstn [get_bd_pins axi_ethernet/axi_rxs_arstn] [get_bd_pins axi_ethernet_dma/s2mm_sts_reset_out_n]
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net axi_ethernet_dma_txd [get_bd_intf_pins axi_ethernet/s_axis_txd] [get_bd_intf_pins axi_ethernet_dma/M_AXIS_MM2S]
|
||||||
|
connect_bd_intf_net -intf_net axi_ethernet_dma_txc [get_bd_intf_pins axi_ethernet/s_axis_txc] [get_bd_intf_pins axi_ethernet_dma/M_AXIS_CNTRL]
|
||||||
|
connect_bd_intf_net -intf_net axi_ethernet_dma_rxd [get_bd_intf_pins axi_ethernet/m_axis_rxd] [get_bd_intf_pins axi_ethernet_dma/S_AXIS_S2MM]
|
||||||
|
connect_bd_intf_net -intf_net axi_ethernet_dma_rxs [get_bd_intf_pins axi_ethernet/m_axis_rxs] [get_bd_intf_pins axi_ethernet_dma/S_AXIS_STS]
|
||||||
|
|
||||||
|
# defaults (interrupts)
|
||||||
|
|
||||||
|
connect_bd_net -net sys_concat_intc_intr_00 [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_timer/interrupt]
|
||||||
|
connect_bd_net -net sys_concat_intc_intr_01 [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_ethernet/interrupt]
|
||||||
|
connect_bd_net -net sys_concat_intc_intr_02 [get_bd_pins sys_concat_intc/In2] [get_bd_pins axi_uart/interrupt]
|
||||||
|
connect_bd_net -net sys_concat_intc_intr_03 [get_bd_pins sys_concat_intc/In3] [get_bd_pins axi_gpio_lcd/ip2intc_irpt]
|
||||||
|
connect_bd_net -net sys_concat_intc_intr_04 [get_bd_pins sys_concat_intc/In4] [get_bd_pins axi_gpio_sw_led/ip2intc_irpt]
|
||||||
|
connect_bd_net -net sys_concat_intc_intr_05 [get_bd_pins sys_concat_intc/In5] [get_bd_pins axi_iic_main/iic2intc_irpt]
|
||||||
|
connect_bd_net -net sys_concat_intc_intr_08 [get_bd_pins sys_concat_intc/In8] [get_bd_pins axi_ethernet_dma/mm2s_introut]
|
||||||
|
connect_bd_net -net sys_concat_intc_intr_09 [get_bd_pins sys_concat_intc/In9] [get_bd_pins axi_ethernet_dma/s2mm_introut]
|
||||||
|
|
||||||
|
# defaults (external interface)
|
||||||
|
|
||||||
|
connect_bd_net -net sys_const_vcc_vcc [get_bd_pins sys_const_vcc/const] [get_bd_ports fan_pwm]
|
||||||
|
connect_bd_net -net sys_rst_s [get_bd_ports sys_rst]
|
||||||
|
connect_bd_net -net sys_rst_s [get_bd_pins sys_rstgen/ext_reset_in]
|
||||||
|
connect_bd_net -net sys_rst_s [get_bd_pins axi_ddr_cntrl/sys_rst]
|
||||||
|
|
||||||
|
connect_bd_net -net sys_clk_p_s [get_bd_ports sys_clk_p] [get_bd_pins axi_ddr_cntrl/sys_clk_p]
|
||||||
|
connect_bd_net -net sys_clk_n_s [get_bd_ports sys_clk_n] [get_bd_pins axi_ddr_cntrl/sys_clk_n]
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net axi_ddr_cntrl_ddr3 [get_bd_intf_ports ddr3] [get_bd_intf_pins axi_ddr_cntrl/DDR3]
|
||||||
|
connect_bd_intf_net -intf_net axi_ethernet_mdio [get_bd_intf_ports mdio] [get_bd_intf_pins axi_ethernet/mdio]
|
||||||
|
connect_bd_intf_net -intf_net axi_ethernet_rgmii [get_bd_intf_ports rgmii] [get_bd_intf_pins axi_ethernet/rgmii]
|
||||||
|
connect_bd_net -net axi_ethernet_phy_rst_n [get_bd_ports phy_rst_n] [get_bd_pins axi_ethernet/phy_rst_n]
|
||||||
|
|
||||||
|
connect_bd_net -net axi_uart_sin [get_bd_ports uart_sin] [get_bd_pins axi_uart/rx]
|
||||||
|
connect_bd_net -net axi_uart_sout [get_bd_ports uart_sout] [get_bd_pins axi_uart/tx]
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net axi_gpio_lcd_gpio [get_bd_intf_ports gpio_lcd] [get_bd_intf_pins axi_gpio_lcd/gpio]
|
||||||
|
connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio [get_bd_intf_ports gpio_sw] [get_bd_intf_pins axi_gpio_sw_led/gpio]
|
||||||
|
connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio2 [get_bd_intf_ports gpio_led] [get_bd_intf_pins axi_gpio_sw_led/gpio2]
|
||||||
|
|
||||||
|
connect_bd_net -net axi_iic_main_rstn [get_bd_ports iic_rstn] [get_bd_pins axi_iic_main/gpo]
|
||||||
|
connect_bd_intf_net -intf_net axi_iic_main_iic [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_main/iic]
|
||||||
|
|
||||||
|
# hdmi peripherals
|
||||||
|
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_dma/axi_resetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_core/s_axi_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/drp_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk]
|
||||||
|
connect_bd_net -net sys_200m_clk [get_bd_pins axi_hdmi_clkgen/clk]
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08 [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi]
|
||||||
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09 [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE]
|
||||||
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10 [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net axi_mem_interconnect_s02 [get_bd_intf_pins axi_mem_interconnect/S02_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S02_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S02_ACLK] $sys_100m_clk_source
|
||||||
|
|
||||||
|
connect_bd_net -net sys_concat_intc_intr_06 [get_bd_pins sys_concat_intc/In6] [get_bd_pins axi_hdmi_dma/mm2s_introut]
|
||||||
|
|
||||||
|
connect_bd_net -net axi_hdmi_core_hdmi_out_clk [get_bd_ports hdmi_out_clk] [get_bd_pins axi_hdmi_core/hdmi_out_clk]
|
||||||
|
connect_bd_net -net axi_hdmi_core_hdmi_hsync [get_bd_ports hdmi_hsync] [get_bd_pins axi_hdmi_core/hdmi_24_hsync]
|
||||||
|
connect_bd_net -net axi_hdmi_core_hdmi_vsync [get_bd_ports hdmi_vsync] [get_bd_pins axi_hdmi_core/hdmi_24_vsync]
|
||||||
|
connect_bd_net -net axi_hdmi_core_hdmi_data_e [get_bd_ports hdmi_data_e] [get_bd_pins axi_hdmi_core/hdmi_24_data_e]
|
||||||
|
connect_bd_net -net axi_hdmi_core_hdmi_data [get_bd_ports hdmi_data] [get_bd_pins axi_hdmi_core/hdmi_24_data]
|
||||||
|
|
||||||
|
connect_bd_net -net axi_hdmi_clkgen_clk [get_bd_pins axi_hdmi_clkgen/clk_0] [get_bd_pins axi_hdmi_core/hdmi_clk]
|
||||||
|
connect_bd_net -net axi_hdmi_core_valid [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tvalid] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tvalid]
|
||||||
|
connect_bd_net -net axi_hdmi_core_data [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tdata] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tdata]
|
||||||
|
connect_bd_net -net axi_hdmi_core_keep [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tkeep] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tkeep]
|
||||||
|
connect_bd_net -net axi_hdmi_core_last [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tlast] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tlast]
|
||||||
|
connect_bd_net -net axi_hdmi_core_ready [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tready] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tready]
|
||||||
|
connect_bd_net -net axi_hdmi_core_fsync [get_bd_pins axi_hdmi_dma/mm2s_fsync] [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync]
|
||||||
|
connect_bd_net -net axi_hdmi_core_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret]
|
||||||
|
|
||||||
|
# spdif audio
|
||||||
|
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/S_AXIS_ARESETN]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_dma/axi_resetn]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/s_axi_lite_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXIS_ACLK]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/m_axi_mm2s_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/m_axi_sg_aclk]
|
||||||
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11 [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi]
|
||||||
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12 [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_spdif_tx_dma/S_AXI_LITE]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
|
||||||
|
|
||||||
|
connect_bd_intf_net -intf_net axi_mem_interconnect_s03 [get_bd_intf_pins axi_mem_interconnect/S03_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_SG]
|
||||||
|
connect_bd_intf_net -intf_net axi_mem_interconnect_s04 [get_bd_intf_pins axi_mem_interconnect/S04_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_MM2S]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S03_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S04_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S03_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S04_ACLK] $sys_100m_clk_source
|
||||||
|
|
||||||
|
connect_bd_net -net axi_spdif_tx_dma_mm2s_valid [get_bd_pins axi_spdif_tx_core/S_AXIS_TVALID] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tvalid]
|
||||||
|
connect_bd_net -net axi_spdif_tx_dma_mm2s_data [get_bd_pins axi_spdif_tx_core/S_AXIS_TDATA] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tdata]
|
||||||
|
connect_bd_net -net axi_spdif_tx_dma_mm2s_last [get_bd_pins axi_spdif_tx_core/S_AXIS_TLAST] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tlast]
|
||||||
|
connect_bd_net -net axi_spdif_tx_dma_mm2s_ready [get_bd_pins axi_spdif_tx_core/S_AXIS_TREADY] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tready]
|
||||||
|
|
||||||
|
connect_bd_net -net sys_concat_intc_intr_07 [get_bd_pins sys_concat_intc/In7] [get_bd_pins axi_spdif_tx_dma/mm2s_introut]
|
||||||
|
|
||||||
|
connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1]
|
||||||
|
connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk]
|
||||||
|
connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o]
|
||||||
|
|
||||||
|
# address mapping
|
||||||
|
|
||||||
|
create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem] SEG_data_dlmb_cntlr
|
||||||
|
create_bd_addr_seg -range 0x00001000 -offset 0x41400000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs sys_mb_debug/S_AXI/Reg] SEG_data_mb_debug
|
||||||
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_data_ddr_cntrl
|
||||||
|
create_bd_addr_seg -range 0x00040000 -offset 0x40E00000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ethernet/eth_buf/S_AXI/REG] SEG_data_ethernetlite
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x41E10000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ethernet_dma/S_AXI_LITE/Reg] SEG_data_ethernet_dma
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x40010000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_gpio_lcd/s_axi/Reg] SEG_data_gpio_lcd
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x40020000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_gpio_sw_led/s_axi/Reg] SEG_data_gpio_sw_led
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_intc/s_axi/Reg] SEG_data_intc
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x41C00000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_timer/s_axi/Reg] SEG_data_timer
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x40600000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_uart/s_axi/Reg] SEG_data_uart
|
||||||
|
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x41600000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_iic_main/s_axi/Reg] SEG_data_iic
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x79000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite] SEG_data_hdmi_clkgen
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg] SEG_data_hdmi_dma
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite] SEG_data_hdmi_core
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0] SEG_data_spdif_tx_core
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x41E00000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_spdif_tx_dma/S_AXI_LITE/Reg] SEG_data_spdif_tx_dma
|
||||||
|
|
||||||
|
create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_instr_ilmb_cntlr
|
||||||
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_instr_ddr_cntrl
|
||||||
|
|
||||||
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||||
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||||
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||||
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||||
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||||
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma/Data_S2MM] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||||
|
|
||||||
|
create_bd_addr_seg -range 0x00001000 -offset 0x00000000 [get_bd_addr_spaces axi_ethernet/eth_buf/S_AXI_2TEMAC] [get_bd_addr_segs axi_ethernet/eth_mac/s_axi/Reg] SEG_eth_mac_reg
|
||||||
|
|
||||||
|
|
@ -0,0 +1,120 @@
|
||||||
|
|
||||||
|
# constraints
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS15} [get_ports sys_rst]
|
||||||
|
|
||||||
|
# clocks
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN R3 IOSTANDARD DIFF_SSTL15} [get_ports sys_clk_p]
|
||||||
|
set_property -dict {PACKAGE_PIN P3 IOSTANDARD DIFF_SSTL15} [get_ports sys_clk_n]
|
||||||
|
|
||||||
|
create_clock -name sys_clk -period 5.00 [get_ports sys_clk_p]
|
||||||
|
|
||||||
|
# ethernet
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS18} [get_ports phy_reset_n]
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS18} [get_ports phy_mdc]
|
||||||
|
set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS18} [get_ports phy_mdio]
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS18} [get_ports phy_tx_clk]
|
||||||
|
set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS18} [get_ports phy_tx_ctrl]
|
||||||
|
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS18} [get_ports phy_tx_data[3]]
|
||||||
|
set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS18} [get_ports phy_tx_data[2]]
|
||||||
|
set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS18} [get_ports phy_tx_data[1]]
|
||||||
|
set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS18} [get_ports phy_tx_data[0]]
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS18} [get_ports phy_rx_clk]
|
||||||
|
set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS18} [get_ports phy_rx_ctrl]
|
||||||
|
set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS18} [get_ports phy_rx_data[3]]
|
||||||
|
set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS18} [get_ports phy_rx_data[2]]
|
||||||
|
set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS18} [get_ports phy_rx_data[1]]
|
||||||
|
set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS18} [get_ports phy_rx_data[0]]
|
||||||
|
|
||||||
|
# uart
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS18} [get_ports uart_sin]
|
||||||
|
set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS18} [get_ports uart_sout]
|
||||||
|
|
||||||
|
# fan
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN J26 IOSTANDARD LVCMOS25} [get_ports fan_pwm]
|
||||||
|
|
||||||
|
# lcd
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[6]] ; ## lcd_e
|
||||||
|
set_property -dict {PACKAGE_PIN L23 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[5]] ; ## lcd_rs
|
||||||
|
set_property -dict {PACKAGE_PIN L24 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[4]] ; ## lcd_rw
|
||||||
|
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[3]] ; ## lcd_db[7]
|
||||||
|
set_property -dict {PACKAGE_PIN M25 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[2]] ; ## lcd_db[6]
|
||||||
|
set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[1]] ; ## lcd_db[5]
|
||||||
|
set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS15} [get_ports gpio_lcd[0]] ; ## lcd_db[4]
|
||||||
|
set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS15} [get_ports gpio_sw[0]] ; ## GPIO_DIP_SW0
|
||||||
|
set_property -dict {PACKAGE_PIN P8 IOSTANDARD LVCMOS15} [get_ports gpio_sw[1]] ; ## GPIO_DIP_SW1
|
||||||
|
set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS15} [get_ports gpio_sw[2]] ; ## GPIO_DIP_SW2
|
||||||
|
set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS15} [get_ports gpio_sw[3]] ; ## GPIO_DIP_SW3
|
||||||
|
set_property -dict {PACKAGE_PIN P6 IOSTANDARD LVCMOS15} [get_ports gpio_sw[4]] ; ## GPIO_SW_N
|
||||||
|
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS15} [get_ports gpio_sw[5]] ; ## GPIO_SW_E
|
||||||
|
set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS15} [get_ports gpio_sw[6]] ; ## GPIO_SW_S
|
||||||
|
set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS15} [get_ports gpio_sw[7]] ; ## GPIO_SW_W
|
||||||
|
set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS15} [get_ports gpio_sw[8]] ; ## GPIO_SW_C
|
||||||
|
set_property -dict {PACKAGE_PIN M26 IOSTANDARD LVCMOS15} [get_ports gpio_led[0]] ; ## GPIO_LED_0_LS
|
||||||
|
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS15} [get_ports gpio_led[1]] ; ## GPIO_LED_1_LS
|
||||||
|
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS15} [get_ports gpio_led[2]] ; ## GPIO_LED_2_LS
|
||||||
|
set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS15} [get_ports gpio_led[3]] ; ## GPIO_LED_3_LS
|
||||||
|
|
||||||
|
# iic
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS15} [get_ports iic_rstn]
|
||||||
|
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS15 DRIVE 8 SLEW SLOW} [get_ports iic_scl]
|
||||||
|
set_property -dict {PACKAGE_PIN K25 IOSTANDARD LVCMOS15 DRIVE 8 SLEW SLOW} [get_ports iic_sda]
|
||||||
|
|
||||||
|
# hdmi
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS18} [get_ports hdmi_out_clk]
|
||||||
|
set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS18} [get_ports hdmi_hsync]
|
||||||
|
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS18} [get_ports hdmi_vsync]
|
||||||
|
set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS18} [get_ports hdmi_data_e]
|
||||||
|
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[0]]
|
||||||
|
set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[1]]
|
||||||
|
set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS18} [get_ports hdmi_data[2]]
|
||||||
|
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS18} [get_ports hdmi_data[3]]
|
||||||
|
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS18} [get_ports hdmi_data[4]]
|
||||||
|
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[5]]
|
||||||
|
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[6]]
|
||||||
|
set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS18} [get_ports hdmi_data[7]]
|
||||||
|
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[8]]
|
||||||
|
set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[9]]
|
||||||
|
set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS18} [get_ports hdmi_data[10]]
|
||||||
|
set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[11]]
|
||||||
|
set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS18} [get_ports hdmi_data[12]]
|
||||||
|
set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[13]]
|
||||||
|
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS18} [get_ports hdmi_data[14]]
|
||||||
|
set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[15]]
|
||||||
|
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[16]]
|
||||||
|
set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[17]]
|
||||||
|
set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[18]]
|
||||||
|
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[19]]
|
||||||
|
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[20]]
|
||||||
|
set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS18} [get_ports hdmi_data[21]]
|
||||||
|
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[22]]
|
||||||
|
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS18} [get_ports hdmi_data[23]]
|
||||||
|
|
||||||
|
# spdif
|
||||||
|
|
||||||
|
set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS18} [get_ports spdif]
|
||||||
|
|
||||||
|
# clocks
|
||||||
|
|
||||||
|
create_clock -name cpu_clk -period 10.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/ui_clk]
|
||||||
|
create_clock -name m200_clk -period 5.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/ui_addn_clk_0]
|
||||||
|
create_clock -name m125_clk -period 8.00 [get_pins i_system_wrapper/system_i/sys_ethernet_clkgen/clk_out_1]
|
||||||
|
create_clock -name hdmi_clk -period 6.73 [get_pins i_system_wrapper/system_i/axi_hdmi_clkgen/clk_0]
|
||||||
|
create_clock -name spdif_clk -period 50.00 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out1]
|
||||||
|
|
||||||
|
set_clock_groups -asynchronous -group {cpu_clk}
|
||||||
|
set_clock_groups -asynchronous -group {m200_clk}
|
||||||
|
set_clock_groups -asynchronous -group {m125_clk}
|
||||||
|
set_clock_groups -asynchronous -group {hdmi_clk}
|
||||||
|
set_clock_groups -asynchronous -group {spdif_clk}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,201 @@
|
||||||
|
<?xml version='1.0' encoding='UTF-8'?>
|
||||||
|
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
|
||||||
|
<Project NoOfControllers="1" >
|
||||||
|
<ModuleName>system_axi_ddr_cntrl_0</ModuleName>
|
||||||
|
<dci_inouts_inputs>1</dci_inouts_inputs>
|
||||||
|
<dci_inputs>1</dci_inputs>
|
||||||
|
<Debug_En>OFF</Debug_En>
|
||||||
|
<DataDepth_En>1024</DataDepth_En>
|
||||||
|
<LowPower_En>OFF</LowPower_En>
|
||||||
|
<XADC_En>Disabled</XADC_En>
|
||||||
|
<TargetFPGA>xc7a200t-fbg676/-2</TargetFPGA>
|
||||||
|
<Version>2.0</Version>
|
||||||
|
<SystemClock>Differential</SystemClock>
|
||||||
|
<ReferenceClock>Use System Clock</ReferenceClock>
|
||||||
|
<SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
|
||||||
|
<BankSelectionFlag>FALSE</BankSelectionFlag>
|
||||||
|
<InternalVref>0</InternalVref>
|
||||||
|
<dci_hr_inouts_inputs>40 Ohms</dci_hr_inouts_inputs>
|
||||||
|
<dci_cascade>0</dci_cascade>
|
||||||
|
<Controller number="0" >
|
||||||
|
<MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6</MemoryDevice>
|
||||||
|
<TimePeriod>2500</TimePeriod>
|
||||||
|
<VccAuxIO>1.8V</VccAuxIO>
|
||||||
|
<PHYRatio>4:1</PHYRatio>
|
||||||
|
<InputClkFreq>200</InputClkFreq>
|
||||||
|
<UIExtraClocks>1</UIExtraClocks>
|
||||||
|
<MMCMClkOut0> 4.000</MMCMClkOut0>
|
||||||
|
<MMCMClkOut1>1</MMCMClkOut1>
|
||||||
|
<MMCMClkOut2>1</MMCMClkOut2>
|
||||||
|
<MMCMClkOut3>1</MMCMClkOut3>
|
||||||
|
<MMCMClkOut4>1</MMCMClkOut4>
|
||||||
|
<DataWidth>64</DataWidth>
|
||||||
|
<DeepMemory>1</DeepMemory>
|
||||||
|
<DataMask>1</DataMask>
|
||||||
|
<ECC>Disabled</ECC>
|
||||||
|
<Ordering>Normal</Ordering>
|
||||||
|
<CustomPart>FALSE</CustomPart>
|
||||||
|
<NewPartName></NewPartName>
|
||||||
|
<RowAddress>14</RowAddress>
|
||||||
|
<ColAddress>10</ColAddress>
|
||||||
|
<BankAddress>3</BankAddress>
|
||||||
|
<MemoryVoltage>1.5V</MemoryVoltage>
|
||||||
|
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
|
||||||
|
<PinSelection>
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M4" SLEW="FAST" name="ddr3_addr[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N7" SLEW="FAST" name="ddr3_addr[10]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L5" SLEW="FAST" name="ddr3_addr[11]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L7" SLEW="FAST" name="ddr3_addr[12]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N6" SLEW="FAST" name="ddr3_addr[13]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J3" SLEW="FAST" name="ddr3_addr[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J1" SLEW="FAST" name="ddr3_addr[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L4" SLEW="FAST" name="ddr3_addr[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K5" SLEW="FAST" name="ddr3_addr[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M7" SLEW="FAST" name="ddr3_addr[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K1" SLEW="FAST" name="ddr3_addr[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M6" SLEW="FAST" name="ddr3_addr[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H1" SLEW="FAST" name="ddr3_addr[8]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K3" SLEW="FAST" name="ddr3_addr[9]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="N1" SLEW="FAST" name="ddr3_ba[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="M1" SLEW="FAST" name="ddr3_ba[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H2" SLEW="FAST" name="ddr3_ba[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T4" SLEW="FAST" name="ddr3_cas_n" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="L2" SLEW="FAST" name="ddr3_ck_n[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="M2" SLEW="FAST" name="ddr3_ck_p[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="P4" SLEW="FAST" name="ddr3_cke[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="T3" SLEW="FAST" name="ddr3_cs_n[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AC6" SLEW="FAST" name="ddr3_dm[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AC4" SLEW="FAST" name="ddr3_dm[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA3" SLEW="FAST" name="ddr3_dm[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="U7" SLEW="FAST" name="ddr3_dm[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G1" SLEW="FAST" name="ddr3_dm[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F3" SLEW="FAST" name="ddr3_dm[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G5" SLEW="FAST" name="ddr3_dm[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H9" SLEW="FAST" name="ddr3_dm[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB6" SLEW="FAST" name="ddr3_dq[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AF3" SLEW="FAST" name="ddr3_dq[10]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AE3" SLEW="FAST" name="ddr3_dq[11]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AD3" SLEW="FAST" name="ddr3_dq[12]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AC3" SLEW="FAST" name="ddr3_dq[13]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB4" SLEW="FAST" name="ddr3_dq[14]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA4" SLEW="FAST" name="ddr3_dq[15]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AC2" SLEW="FAST" name="ddr3_dq[16]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB2" SLEW="FAST" name="ddr3_dq[17]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AF2" SLEW="FAST" name="ddr3_dq[18]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AE2" SLEW="FAST" name="ddr3_dq[19]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA8" SLEW="FAST" name="ddr3_dq[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y1" SLEW="FAST" name="ddr3_dq[20]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y2" SLEW="FAST" name="ddr3_dq[21]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AC1" SLEW="FAST" name="ddr3_dq[22]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB1" SLEW="FAST" name="ddr3_dq[23]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y3" SLEW="FAST" name="ddr3_dq[24]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W3" SLEW="FAST" name="ddr3_dq[25]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W6" SLEW="FAST" name="ddr3_dq[26]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V6" SLEW="FAST" name="ddr3_dq[27]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W4" SLEW="FAST" name="ddr3_dq[28]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W5" SLEW="FAST" name="ddr3_dq[29]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y8" SLEW="FAST" name="ddr3_dq[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="W1" SLEW="FAST" name="ddr3_dq[30]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="V1" SLEW="FAST" name="ddr3_dq[31]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G2" SLEW="FAST" name="ddr3_dq[32]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D1" SLEW="FAST" name="ddr3_dq[33]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E1" SLEW="FAST" name="ddr3_dq[34]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E2" SLEW="FAST" name="ddr3_dq[35]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F2" SLEW="FAST" name="ddr3_dq[36]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="A2" SLEW="FAST" name="ddr3_dq[37]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="A3" SLEW="FAST" name="ddr3_dq[38]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C2" SLEW="FAST" name="ddr3_dq[39]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AB5" SLEW="FAST" name="ddr3_dq[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C3" SLEW="FAST" name="ddr3_dq[40]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D3" SLEW="FAST" name="ddr3_dq[41]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="A4" SLEW="FAST" name="ddr3_dq[42]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B4" SLEW="FAST" name="ddr3_dq[43]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C4" SLEW="FAST" name="ddr3_dq[44]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D4" SLEW="FAST" name="ddr3_dq[45]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D5" SLEW="FAST" name="ddr3_dq[46]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E5" SLEW="FAST" name="ddr3_dq[47]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F4" SLEW="FAST" name="ddr3_dq[48]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G4" SLEW="FAST" name="ddr3_dq[49]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AA5" SLEW="FAST" name="ddr3_dq[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K6" SLEW="FAST" name="ddr3_dq[50]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K7" SLEW="FAST" name="ddr3_dq[51]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="K8" SLEW="FAST" name="ddr3_dq[52]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="L8" SLEW="FAST" name="ddr3_dq[53]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J5" SLEW="FAST" name="ddr3_dq[54]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="J6" SLEW="FAST" name="ddr3_dq[55]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G6" SLEW="FAST" name="ddr3_dq[56]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H6" SLEW="FAST" name="ddr3_dq[57]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F7" SLEW="FAST" name="ddr3_dq[58]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F8" SLEW="FAST" name="ddr3_dq[59]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y5" SLEW="FAST" name="ddr3_dq[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G8" SLEW="FAST" name="ddr3_dq[60]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H8" SLEW="FAST" name="ddr3_dq[61]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D6" SLEW="FAST" name="ddr3_dq[62]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E6" SLEW="FAST" name="ddr3_dq[63]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y6" SLEW="FAST" name="ddr3_dq[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="Y7" SLEW="FAST" name="ddr3_dq[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AF4" SLEW="FAST" name="ddr3_dq[8]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="AF5" SLEW="FAST" name="ddr3_dq[9]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="W8" SLEW="FAST" name="ddr3_dqs_n[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="AE5" SLEW="FAST" name="ddr3_dqs_n[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="AE1" SLEW="FAST" name="ddr3_dqs_n[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="V2" SLEW="FAST" name="ddr3_dqs_n[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="B1" SLEW="FAST" name="ddr3_dqs_n[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="A5" SLEW="FAST" name="ddr3_dqs_n[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="H4" SLEW="FAST" name="ddr3_dqs_n[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="G7" SLEW="FAST" name="ddr3_dqs_n[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="V8" SLEW="FAST" name="ddr3_dqs_p[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="AD5" SLEW="FAST" name="ddr3_dqs_p[1]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="AD1" SLEW="FAST" name="ddr3_dqs_p[2]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="V3" SLEW="FAST" name="ddr3_dqs_p[3]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="C1" SLEW="FAST" name="ddr3_dqs_p[4]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="B5" SLEW="FAST" name="ddr3_dqs_p[5]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="J4" SLEW="FAST" name="ddr3_dqs_p[6]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="H7" SLEW="FAST" name="ddr3_dqs_p[7]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="R2" SLEW="FAST" name="ddr3_odt[0]" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="P1" SLEW="FAST" name="ddr3_ras_n" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="LVCMOS15" PADName="N8" SLEW="FAST" name="ddr3_reset_n" IN_TERM="" />
|
||||||
|
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="R1" SLEW="FAST" name="ddr3_we_n" IN_TERM="" />
|
||||||
|
</PinSelection>
|
||||||
|
<System_Clock>
|
||||||
|
<Pin PADName="R3/P3(CC_P/N)" Bank="34" name="sys_clk_p/n" />
|
||||||
|
</System_Clock>
|
||||||
|
<System_Control>
|
||||||
|
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
|
||||||
|
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
|
||||||
|
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
|
||||||
|
</System_Control>
|
||||||
|
<TimingParameters>
|
||||||
|
<Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.125" tras="35" trcd="13.125" />
|
||||||
|
</TimingParameters>
|
||||||
|
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
|
||||||
|
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
|
||||||
|
<mrCasLatency name="CAS Latency" >6</mrCasLatency>
|
||||||
|
<mrMode name="Mode" >Normal</mrMode>
|
||||||
|
<mrDllReset name="DLL Reset" >No</mrDllReset>
|
||||||
|
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
|
||||||
|
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
|
||||||
|
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
|
||||||
|
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
|
||||||
|
<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
|
||||||
|
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
|
||||||
|
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
|
||||||
|
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
|
||||||
|
<emrDQS name="TDQS enable" >Enabled</emrDQS>
|
||||||
|
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
|
||||||
|
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
|
||||||
|
<mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
|
||||||
|
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
|
||||||
|
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
|
||||||
|
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
|
||||||
|
<PortInterface>AXI</PortInterface>
|
||||||
|
<AXIParameters>
|
||||||
|
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
|
||||||
|
<C0_S_AXI_ADDR_WIDTH>32</C0_S_AXI_ADDR_WIDTH>
|
||||||
|
<C0_S_AXI_DATA_WIDTH>512</C0_S_AXI_DATA_WIDTH>
|
||||||
|
<C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
|
||||||
|
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
|
||||||
|
</AXIParameters>
|
||||||
|
</Controller>
|
||||||
|
|
||||||
|
</Project>
|
||||||
|
|
@ -8,8 +8,8 @@ set ddr3_1_p [create_bd_port -dir O -from 1 -to 0 ddr3_1_p]
|
||||||
set ddr3_1_n [create_bd_port -dir O -from 2 -to 0 ddr3_1_n]
|
set ddr3_1_n [create_bd_port -dir O -from 2 -to 0 ddr3_1_n]
|
||||||
set ddr3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3]
|
set ddr3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3]
|
||||||
|
|
||||||
set mii [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mii_rtl:1.0 mii]
|
|
||||||
set mdio [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio]
|
set mdio [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 mdio]
|
||||||
|
set mii [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mii_rtl:1.0 mii]
|
||||||
|
|
||||||
set gpio_sw [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_sw]
|
set gpio_sw [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_sw]
|
||||||
set gpio_led [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_led]
|
set gpio_led [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_led]
|
||||||
|
|
@ -35,119 +35,109 @@ set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] $sys_rst
|
||||||
|
|
||||||
# instance: microblaze - processor
|
# instance: microblaze - processor
|
||||||
|
|
||||||
set microblaze_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.2 microblaze_1]
|
set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.2 sys_mb]
|
||||||
set_property -dict [list CONFIG.C_FAULT_TOLERANT {0}] $microblaze_1
|
set_property -dict [list CONFIG.C_FAULT_TOLERANT {0}] $sys_mb
|
||||||
set_property -dict [list CONFIG.C_D_AXI {1}] $microblaze_1
|
set_property -dict [list CONFIG.C_D_AXI {1}] $sys_mb
|
||||||
set_property -dict [list CONFIG.C_D_LMB {1}] $microblaze_1
|
set_property -dict [list CONFIG.C_D_LMB {1}] $sys_mb
|
||||||
set_property -dict [list CONFIG.C_I_LMB {1}] $microblaze_1
|
set_property -dict [list CONFIG.C_I_LMB {1}] $sys_mb
|
||||||
set_property -dict [list CONFIG.C_DEBUG_ENABLED {1}] $microblaze_1
|
set_property -dict [list CONFIG.C_DEBUG_ENABLED {1}] $sys_mb
|
||||||
set_property -dict [list CONFIG.C_USE_ICACHE {1}] $microblaze_1
|
set_property -dict [list CONFIG.C_USE_ICACHE {1}] $sys_mb
|
||||||
set_property -dict [list CONFIG.C_ICACHE_LINE_LEN {8}] $microblaze_1
|
set_property -dict [list CONFIG.C_ICACHE_LINE_LEN {8}] $sys_mb
|
||||||
set_property -dict [list CONFIG.C_ICACHE_ALWAYS_USED {1}] $microblaze_1
|
set_property -dict [list CONFIG.C_ICACHE_ALWAYS_USED {1}] $sys_mb
|
||||||
set_property -dict [list CONFIG.C_ICACHE_FORCE_TAG_LUTRAM {1}] $microblaze_1
|
set_property -dict [list CONFIG.C_ICACHE_FORCE_TAG_LUTRAM {1}] $sys_mb
|
||||||
set_property -dict [list CONFIG.C_USE_DCACHE {1}] $microblaze_1
|
set_property -dict [list CONFIG.C_USE_DCACHE {1}] $sys_mb
|
||||||
set_property -dict [list CONFIG.C_DCACHE_LINE_LEN {8}] $microblaze_1
|
set_property -dict [list CONFIG.C_DCACHE_LINE_LEN {8}] $sys_mb
|
||||||
set_property -dict [list CONFIG.C_DCACHE_ALWAYS_USED {1}] $microblaze_1
|
set_property -dict [list CONFIG.C_DCACHE_ALWAYS_USED {1}] $sys_mb
|
||||||
set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $microblaze_1
|
set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb
|
||||||
set_property -dict [list CONFIG.C_ICACHE_HIGHADDR {0xBFFFFFFF}] $microblaze_1
|
set_property -dict [list CONFIG.C_ICACHE_HIGHADDR {0xBFFFFFFF}] $sys_mb
|
||||||
set_property -dict [list CONFIG.C_ICACHE_BASEADDR {0x80000000}] $microblaze_1
|
set_property -dict [list CONFIG.C_ICACHE_BASEADDR {0x80000000}] $sys_mb
|
||||||
set_property -dict [list CONFIG.C_DCACHE_HIGHADDR {0xBFFFFFFF}] $microblaze_1
|
set_property -dict [list CONFIG.C_DCACHE_HIGHADDR {0xBFFFFFFF}] $sys_mb
|
||||||
set_property -dict [list CONFIG.C_DCACHE_BASEADDR {0x80000000}] $microblaze_1
|
set_property -dict [list CONFIG.C_DCACHE_BASEADDR {0x80000000}] $sys_mb
|
||||||
|
|
||||||
# instance: microblaze - local memory & bus
|
# instance: microblaze - local memory & bus
|
||||||
|
|
||||||
set dlmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb]
|
set sys_dlmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_dlmb]
|
||||||
set ilmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb]
|
set sys_ilmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_ilmb]
|
||||||
|
|
||||||
set dlmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_cntlr]
|
set sys_dlmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_dlmb_cntlr]
|
||||||
set_property -dict [list CONFIG.C_ECC {0}] $dlmb_cntlr
|
set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr
|
||||||
|
|
||||||
set ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_cntlr]
|
set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr]
|
||||||
set_property -dict [list CONFIG.C_ECC {0}] $ilmb_cntlr
|
set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr
|
||||||
|
|
||||||
set lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.1 lmb_bram]
|
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.1 sys_lmb_bram]
|
||||||
set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $lmb_bram
|
set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram
|
||||||
|
|
||||||
# instance: microblaze- mdm
|
# instance: microblaze- mdm
|
||||||
|
|
||||||
set mb_debug [create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.0 mb_debug]
|
set sys_mb_debug [create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.0 sys_mb_debug]
|
||||||
set_property -dict [list CONFIG.C_USE_UART {1}] $mb_debug
|
set_property -dict [list CONFIG.C_USE_UART {1}] $sys_mb_debug
|
||||||
|
|
||||||
# instance: system reset/clocks
|
# instance: system reset/clocks
|
||||||
|
|
||||||
set proc_sys_reset_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1]
|
set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
|
||||||
|
|
||||||
set proc_sys_clock_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 proc_sys_clock_1]
|
set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 sys_const_vcc]
|
||||||
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $proc_sys_clock_1
|
|
||||||
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {100}] $proc_sys_clock_1
|
|
||||||
set_property -dict [list CONFIG.PRIM_SOURCE {No_buffer}] $proc_sys_clock_1
|
|
||||||
set_property -dict [list CONFIG.USE_RESET {false}] $proc_sys_clock_1
|
|
||||||
|
|
||||||
set proc_const_vcc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 proc_const_vcc_1]
|
|
||||||
|
|
||||||
# instance: ddr (mig)
|
# instance: ddr (mig)
|
||||||
|
|
||||||
set axi_ddr_cntrl_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.0 axi_ddr_cntrl_1]
|
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.0 axi_ddr_cntrl]
|
||||||
set axi_ddr_cntrl_1_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl_1]]]
|
set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
|
||||||
file copy -force $ad_hdl_dir/projects/common/kc705/kc705_system_mig.prj "$axi_ddr_cntrl_1_dir/"
|
file copy -force $ad_hdl_dir/projects/common/kc705/kc705_system_mig.prj "$axi_ddr_cntrl_dir/"
|
||||||
set_property -dict [list CONFIG.XML_INPUT_FILE {kc705_system_mig.prj}] $axi_ddr_cntrl_1
|
set_property -dict [list CONFIG.XML_INPUT_FILE {kc705_system_mig.prj}] $axi_ddr_cntrl
|
||||||
set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {Custom}] $axi_ddr_cntrl_1
|
|
||||||
|
|
||||||
set ddr3_const_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 ddr3_const_0]
|
set sys_const_ddr3_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 sys_const_ddr3_0]
|
||||||
set_property -dict [list CONFIG.CONST_WIDTH {3}] $ddr3_const_0
|
set_property -dict [list CONFIG.CONST_WIDTH {3}] $sys_const_ddr3_0
|
||||||
set_property -dict [list CONFIG.CONST_VAL {0}] $ddr3_const_0
|
set_property -dict [list CONFIG.CONST_VAL {0}] $sys_const_ddr3_0
|
||||||
|
|
||||||
set ddr3_const_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 ddr3_const_1]
|
set sys_const_ddr3_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 sys_const_ddr3_1]
|
||||||
set_property -dict [list CONFIG.CONST_WIDTH {2}] $ddr3_const_1
|
set_property -dict [list CONFIG.CONST_WIDTH {2}] $sys_const_ddr3_1
|
||||||
set_property -dict [list CONFIG.CONST_VAL {1}] $ddr3_const_1
|
set_property -dict [list CONFIG.CONST_VAL {1}] $sys_const_ddr3_1
|
||||||
|
|
||||||
# instance: axi interconnect (lite)
|
# instance: axi interconnect (lite)
|
||||||
|
|
||||||
set axi_interconnect_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_1]
|
set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect]
|
||||||
set_property -dict [list CONFIG.NUM_MI {13}] $axi_interconnect_1
|
set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect
|
||||||
|
|
||||||
# instance: axi interconnect
|
# instance: axi interconnect
|
||||||
|
|
||||||
set axi_interconnect_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_2]
|
set axi_mem_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_interconnect]
|
||||||
set_property -dict [list CONFIG.NUM_SI {5}] $axi_interconnect_2
|
set_property -dict [list CONFIG.NUM_SI {8}] $axi_mem_interconnect
|
||||||
set_property -dict [list CONFIG.NUM_MI {1}] $axi_interconnect_2
|
set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_interconnect
|
||||||
set_property -dict [list CONFIG.ENABLE_ADVANCED_OPTIONS {1}] $axi_interconnect_2
|
set_property -dict [list CONFIG.ENABLE_ADVANCED_OPTIONS {1}] $axi_mem_interconnect
|
||||||
set_property -dict [list CONFIG.XBAR_DATA_WIDTH {512}] $axi_interconnect_2
|
set_property -dict [list CONFIG.XBAR_DATA_WIDTH {512}] $axi_mem_interconnect
|
||||||
|
|
||||||
# instance: default peripherals
|
# instance: default peripherals
|
||||||
|
|
||||||
set axi_ethernetlite_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernetlite:2.0 axi_ethernetlite_1]
|
set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernetlite:2.0 axi_ethernet]
|
||||||
set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_ethernetlite_1
|
set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_ethernet
|
||||||
set_property -dict [list CONFIG.MII_BOARD_INTERFACE {mii}] $axi_ethernetlite_1
|
set_property -dict [list CONFIG.MII_BOARD_INTERFACE {mii}] $axi_ethernet
|
||||||
set_property -dict [list CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc}] $axi_ethernetlite_1
|
set_property -dict [list CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc}] $axi_ethernet
|
||||||
|
|
||||||
set axi_iic_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_1]
|
set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
|
||||||
|
|
||||||
set axi_uart_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart_1]
|
set axi_uart [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart]
|
||||||
set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart_1
|
set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart
|
||||||
|
|
||||||
set axi_timer_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_1]
|
set axi_timer [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer]
|
||||||
|
|
||||||
set axi_gpio_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1]
|
set axi_gpio_lcd [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_lcd]
|
||||||
set_property -dict [list CONFIG.C_GPIO_WIDTH {7}] $axi_gpio_1
|
set_property -dict [list CONFIG.C_GPIO_WIDTH {7}] $axi_gpio_lcd
|
||||||
set_property -dict [list CONFIG.C_ALL_OUTPUTS {1}] $axi_gpio_1
|
set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_lcd
|
||||||
set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_1
|
|
||||||
|
|
||||||
set axi_gpio_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2]
|
set axi_gpio_sw_led [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_sw_led]
|
||||||
set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio_2
|
set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio_sw_led
|
||||||
set_property -dict [list CONFIG.C_GPIO_WIDTH {9}] $axi_gpio_2
|
set_property -dict [list CONFIG.C_GPIO_WIDTH {9}] $axi_gpio_sw_led
|
||||||
set_property -dict [list CONFIG.C_GPIO2_WIDTH {8}] $axi_gpio_2
|
set_property -dict [list CONFIG.C_GPIO2_WIDTH {8}] $axi_gpio_sw_led
|
||||||
set_property -dict [list CONFIG.C_ALL_INPUTS {1}] $axi_gpio_2
|
set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_sw_led
|
||||||
set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_2
|
|
||||||
set_property -dict [list CONFIG.C_ALL_OUTPUTS_2 {1}] $axi_gpio_2
|
|
||||||
|
|
||||||
# instance: interrupt
|
# instance: interrupt
|
||||||
|
|
||||||
set axi_intc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_1]
|
set axi_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc]
|
||||||
set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc_1
|
set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc
|
||||||
|
|
||||||
set concat_intc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 concat_intc_1]
|
set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_concat_intc]
|
||||||
set_property -dict [list CONFIG.NUM_PORTS {8}] $concat_intc_1
|
set_property -dict [list CONFIG.NUM_PORTS {8}] $sys_concat_intc
|
||||||
|
|
||||||
# hdmi peripherals
|
# hdmi peripherals
|
||||||
|
|
||||||
|
|
@ -177,175 +167,191 @@ set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_spdif_tx_dm
|
||||||
|
|
||||||
# connections
|
# connections
|
||||||
|
|
||||||
connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mb_debug/Debug_SYS_Rst]
|
connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins sys_mb_debug/Debug_SYS_Rst]
|
||||||
connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins proc_sys_reset_1/mb_debug_sys_rst]
|
connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins sys_rstgen/mb_debug_sys_rst]
|
||||||
|
|
||||||
connect_bd_net -net proc_sys_reset_1_mb_reset [get_bd_pins proc_sys_reset_1/mb_reset]
|
connect_bd_net -net sys_rstgen_mb_reset [get_bd_pins sys_rstgen/mb_reset]
|
||||||
connect_bd_net -net proc_sys_reset_1_mb_reset [get_bd_pins microblaze_1/Reset]
|
connect_bd_net -net sys_rstgen_mb_reset [get_bd_pins sys_mb/Reset]
|
||||||
|
|
||||||
connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins proc_sys_reset_1/bus_struct_reset]
|
connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_rstgen/bus_struct_reset]
|
||||||
connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins dlmb/SYS_Rst]
|
connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_dlmb/SYS_Rst]
|
||||||
connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins ilmb/SYS_Rst]
|
connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_ilmb/SYS_Rst]
|
||||||
connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins dlmb_cntlr/LMB_Rst]
|
connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_dlmb_cntlr/LMB_Rst]
|
||||||
connect_bd_net -net proc_sys_reset_1_bus_struct_reset [get_bd_pins ilmb_cntlr/LMB_Rst]
|
connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_ilmb_cntlr/LMB_Rst]
|
||||||
|
|
||||||
# microblaze local memory
|
# microblaze local memory
|
||||||
|
|
||||||
connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb [get_bd_intf_pins dlmb/LMB_Sl_0] [get_bd_intf_pins dlmb_cntlr/SLMB]
|
connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb [get_bd_intf_pins sys_dlmb/LMB_Sl_0] [get_bd_intf_pins sys_dlmb_cntlr/SLMB]
|
||||||
connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb [get_bd_intf_pins ilmb/LMB_Sl_0] [get_bd_intf_pins ilmb_cntlr/SLMB]
|
connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb [get_bd_intf_pins sys_ilmb/LMB_Sl_0] [get_bd_intf_pins sys_ilmb_cntlr/SLMB]
|
||||||
connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb_bram [get_bd_intf_pins dlmb_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA]
|
connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb_bram [get_bd_intf_pins sys_dlmb_cntlr/BRAM_PORT] [get_bd_intf_pins sys_lmb_bram/BRAM_PORTA]
|
||||||
connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb_bram [get_bd_intf_pins ilmb_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB]
|
connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb_bram [get_bd_intf_pins sys_ilmb_cntlr/BRAM_PORT] [get_bd_intf_pins sys_lmb_bram/BRAM_PORTB]
|
||||||
connect_bd_intf_net -intf_net microblaze_1_dlmb [get_bd_intf_pins microblaze_1/DLMB] [get_bd_intf_pins dlmb/LMB_M]
|
connect_bd_intf_net -intf_net sys_mb_dlmb [get_bd_intf_pins sys_mb/DLMB] [get_bd_intf_pins sys_dlmb/LMB_M]
|
||||||
connect_bd_intf_net -intf_net microblaze_1_ilmb [get_bd_intf_pins microblaze_1/ILMB] [get_bd_intf_pins ilmb/LMB_M]
|
connect_bd_intf_net -intf_net sys_mb_ilmb [get_bd_intf_pins sys_mb/ILMB] [get_bd_intf_pins sys_ilmb/LMB_M]
|
||||||
|
|
||||||
# microblaze debug & interrupt
|
# microblaze debug & interrupt
|
||||||
|
|
||||||
connect_bd_intf_net -intf_net microblaze_1_debug [get_bd_intf_pins mb_debug/MBDEBUG_0] [get_bd_intf_pins microblaze_1/DEBUG]
|
connect_bd_intf_net -intf_net sys_mb_debug_intf [get_bd_intf_pins sys_mb_debug/MBDEBUG_0] [get_bd_intf_pins sys_mb/DEBUG]
|
||||||
connect_bd_net -net concat_intc_1_intr [get_bd_pins concat_intc_1/dout] [get_bd_pins axi_intc_1/intr]
|
connect_bd_intf_net -intf_net sys_mb_interrupt [get_bd_intf_pins axi_intc/interrupt] [get_bd_intf_pins sys_mb/INTERRUPT]
|
||||||
connect_bd_intf_net -intf_net microblaze_1_interrupt [get_bd_intf_pins axi_intc_1/interrupt] [get_bd_intf_pins microblaze_1/INTERRUPT]
|
connect_bd_net -net sys_concat_intc_intr [get_bd_pins sys_concat_intc/dout] [get_bd_pins axi_intc/intr]
|
||||||
|
|
||||||
# defaults (peripherals)
|
# defaults (peripherals)
|
||||||
|
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net axi_ddr_cntrl_mmcm_locked [get_bd_pins axi_ddr_cntrl/mmcm_locked] [get_bd_pins sys_rstgen/dcm_locked]
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
|
||||||
|
|
||||||
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins proc_sys_reset_1/peripheral_aresetn]
|
set sys_100m_resetn_source [get_bd_pins sys_rstgen/peripheral_aresetn]
|
||||||
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins mb_debug/S_AXI_ARESETN]
|
set sys_200m_resetn_source [get_bd_pins sys_rstgen/interconnect_aresetn]
|
||||||
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_ddr_cntrl_1/aresetn]
|
set sys_100m_clk_source [get_bd_pins axi_ddr_cntrl/ui_addn_clk_0]
|
||||||
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_ethernetlite_1/s_axi_aresetn]
|
set sys_200m_clk_source [get_bd_pins axi_ddr_cntrl/ui_clk]
|
||||||
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_uart_1/s_axi_aresetn]
|
|
||||||
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_timer_1/s_axi_aresetn]
|
|
||||||
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_intc_1/s_axi_aresetn]
|
|
||||||
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_gpio_1/s_axi_aresetn]
|
|
||||||
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_gpio_2/s_axi_aresetn]
|
|
||||||
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_iic_1/s_axi_aresetn]
|
|
||||||
|
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins proc_sys_clock_1/clk_out1] [get_bd_pins axi_interconnect_1/ACLK]
|
connect_bd_net -net sys_100m_resetn $sys_100m_resetn_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins proc_sys_reset_1/slowest_sync_clk]
|
connect_bd_net -net sys_200m_resetn $sys_200m_resetn_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins microblaze_1/Clk]
|
connect_bd_net -net sys_100m_clk $sys_100m_clk_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins mb_debug/S_AXI_ACLK]
|
connect_bd_net -net sys_200m_clk $sys_200m_clk_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins dlmb/LMB_Clk]
|
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins ilmb/LMB_Clk]
|
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins dlmb_cntlr/LMB_Clk]
|
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins ilmb_cntlr/LMB_Clk]
|
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_ethernetlite_1/s_axi_aclk]
|
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_uart_1/s_axi_aclk]
|
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_timer_1/s_axi_aclk]
|
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_intc_1/s_axi_aclk]
|
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_gpio_1/s_axi_aclk]
|
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_gpio_2/s_axi_aclk]
|
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_iic_1/s_axi_aclk]
|
|
||||||
|
|
||||||
connect_bd_net -net axi_ddr_cntrl_1_200mhz [get_bd_pins axi_ddr_cntrl_1/ui_clk] [get_bd_pins axi_interconnect_2/ACLK]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net axi_ddr_cntrl_1_200mhz [get_bd_pins proc_sys_clock_1/clk_in1]
|
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_200m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/ACLK] $sys_200m_clk_source
|
||||||
|
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins sys_mb_debug/S_AXI_ARESETN]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ddr_cntrl/aresetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ethernet/s_axi_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_uart/s_axi_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_timer/s_axi_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_intc/s_axi_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_gpio_lcd/s_axi_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_gpio_sw_led/s_axi_aresetn]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_main/s_axi_aresetn]
|
||||||
|
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins sys_rstgen/slowest_sync_clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins sys_mb/Clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins sys_mb_debug/S_AXI_ACLK]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins sys_dlmb/LMB_Clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ilmb/LMB_Clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins sys_dlmb_cntlr/LMB_Clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ilmb_cntlr/LMB_Clk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_uart/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_timer/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_intc/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_gpio_lcd/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_gpio_sw_led/s_axi_aclk]
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_main/s_axi_aclk]
|
||||||
|
|
||||||
# defaults (interconnect - processor)
|
# defaults (interconnect - processor)
|
||||||
|
|
||||||
connect_bd_intf_net -intf_net axi_interconnect_1_s00 [get_bd_intf_pins axi_interconnect_1/S00_AXI] [get_bd_intf_pins microblaze_1/M_AXI_DP]
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_s00 [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DP]
|
||||||
connect_bd_intf_net -intf_net axi_interconnect_1_m00 [get_bd_intf_pins axi_interconnect_1/M00_AXI] [get_bd_intf_pins mb_debug/S_AXI]
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m00 [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins sys_mb_debug/S_AXI]
|
||||||
connect_bd_intf_net -intf_net axi_interconnect_1_m01 [get_bd_intf_pins axi_interconnect_1/M01_AXI] [get_bd_intf_pins axi_ethernetlite_1/s_axi]
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m01 [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_ethernet/s_axi]
|
||||||
connect_bd_intf_net -intf_net axi_interconnect_1_m02 [get_bd_intf_pins axi_interconnect_1/M02_AXI] [get_bd_intf_pins axi_uart_1/s_axi]
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m02 [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins axi_uart/s_axi]
|
||||||
connect_bd_intf_net -intf_net axi_interconnect_1_m03 [get_bd_intf_pins axi_interconnect_1/M03_AXI] [get_bd_intf_pins axi_timer_1/s_axi]
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m03 [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_timer/s_axi]
|
||||||
connect_bd_intf_net -intf_net axi_interconnect_1_m04 [get_bd_intf_pins axi_interconnect_1/M04_AXI] [get_bd_intf_pins axi_intc_1/s_axi]
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m04 [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_intc/s_axi]
|
||||||
connect_bd_intf_net -intf_net axi_interconnect_1_m05 [get_bd_intf_pins axi_interconnect_1/M05_AXI] [get_bd_intf_pins axi_gpio_1/s_axi]
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m05 [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins axi_gpio_lcd/s_axi]
|
||||||
connect_bd_intf_net -intf_net axi_interconnect_1_m06 [get_bd_intf_pins axi_interconnect_1/M06_AXI] [get_bd_intf_pins axi_gpio_2/s_axi]
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m06 [get_bd_intf_pins axi_cpu_interconnect/M06_AXI] [get_bd_intf_pins axi_gpio_sw_led/s_axi]
|
||||||
connect_bd_intf_net -intf_net axi_interconnect_1_m07 [get_bd_intf_pins axi_interconnect_1/M07_AXI] [get_bd_intf_pins axi_iic_1/s_axi]
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07 [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_iic_main/s_axi]
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/S00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M01_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M01_ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M02_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M02_ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M03_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M03_ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M04_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M04_ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M05_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M05_ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M06_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M07_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/S00_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M00_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/S00_ACLK] $sys_100m_clk_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M01_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sys_100m_clk_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M02_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M01_ACLK] $sys_100m_clk_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M03_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M02_ACLK] $sys_100m_clk_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M04_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M03_ACLK] $sys_100m_clk_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M05_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M04_ACLK] $sys_100m_clk_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M06_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M05_ACLK] $sys_100m_clk_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M07_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source
|
||||||
|
|
||||||
# defaults (interconnect - memory)
|
# defaults (interconnect - memory)
|
||||||
|
|
||||||
connect_bd_intf_net -intf_net axi_interconnect_2_m00 [get_bd_intf_pins axi_interconnect_2/M00_AXI] [get_bd_intf_pins axi_ddr_cntrl_1/S_AXI]
|
connect_bd_intf_net -intf_net axi_mem_interconnect_m00 [get_bd_intf_pins axi_mem_interconnect/M00_AXI] [get_bd_intf_pins axi_ddr_cntrl/S_AXI]
|
||||||
connect_bd_intf_net -intf_net axi_interconnect_2_s00 [get_bd_intf_pins axi_interconnect_2/S00_AXI] [get_bd_intf_pins microblaze_1/M_AXI_DC]
|
connect_bd_intf_net -intf_net axi_mem_interconnect_s00 [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DC]
|
||||||
connect_bd_intf_net -intf_net axi_interconnect_2_s01 [get_bd_intf_pins axi_interconnect_2/S01_AXI] [get_bd_intf_pins microblaze_1/M_AXI_IC]
|
connect_bd_intf_net -intf_net axi_mem_interconnect_s01 [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins sys_mb/M_AXI_IC]
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/M00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_200m_resetn_source
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S00_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S01_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S01_ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net axi_ddr_cntrl_1_200mhz [get_bd_pins axi_interconnect_2/M00_ACLK] [get_bd_pins axi_ddr_cntrl_1/ui_clk]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S05_ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S00_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S06_ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S01_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S07_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/M00_ACLK] $sys_200m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S00_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S01_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S05_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S06_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S07_ACLK] $sys_100m_clk_source
|
||||||
|
|
||||||
# defaults (interrupts)
|
# defaults (interrupts)
|
||||||
|
|
||||||
connect_bd_net -net concat_intc_1_intr_00 [get_bd_pins concat_intc_1/In0] [get_bd_pins axi_timer_1/interrupt]
|
connect_bd_net -net sys_concat_intc_intr_00 [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_timer/interrupt]
|
||||||
connect_bd_net -net concat_intc_1_intr_01 [get_bd_pins concat_intc_1/In1] [get_bd_pins axi_ethernetlite_1/ip2intc_irpt]
|
connect_bd_net -net sys_concat_intc_intr_01 [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_ethernet/ip2intc_irpt]
|
||||||
connect_bd_net -net concat_intc_1_intr_02 [get_bd_pins concat_intc_1/In2] [get_bd_pins axi_uart_1/interrupt]
|
connect_bd_net -net sys_concat_intc_intr_02 [get_bd_pins sys_concat_intc/In2] [get_bd_pins axi_uart/interrupt]
|
||||||
connect_bd_net -net concat_intc_1_intr_03 [get_bd_pins concat_intc_1/In3] [get_bd_pins axi_gpio_1/ip2intc_irpt]
|
connect_bd_net -net sys_concat_intc_intr_03 [get_bd_pins sys_concat_intc/In3] [get_bd_pins axi_gpio_lcd/ip2intc_irpt]
|
||||||
connect_bd_net -net concat_intc_1_intr_04 [get_bd_pins concat_intc_1/In4] [get_bd_pins axi_gpio_2/ip2intc_irpt]
|
connect_bd_net -net sys_concat_intc_intr_04 [get_bd_pins sys_concat_intc/In4] [get_bd_pins axi_gpio_sw_led/ip2intc_irpt]
|
||||||
connect_bd_net -net concat_intc_1_intr_05 [get_bd_pins concat_intc_1/In5] [get_bd_pins axi_iic_1/iic2intc_irpt]
|
connect_bd_net -net sys_concat_intc_intr_05 [get_bd_pins sys_concat_intc/In5] [get_bd_pins axi_iic_main/iic2intc_irpt]
|
||||||
|
|
||||||
# defaults (external interface)
|
# defaults (external interface)
|
||||||
|
|
||||||
connect_bd_net -net fan_pwm_s [get_bd_ports fan_pwm] [get_bd_pins proc_const_vcc_1/const]
|
connect_bd_net -net sys_const_vcc_vcc [get_bd_pins sys_const_vcc/const] [get_bd_ports fan_pwm]
|
||||||
connect_bd_net -net sys_rst_s [get_bd_ports sys_rst]
|
connect_bd_net -net sys_rst_s [get_bd_ports sys_rst]
|
||||||
connect_bd_net -net sys_rst_s [get_bd_pins proc_sys_reset_1/ext_reset_in]
|
connect_bd_net -net sys_rst_s [get_bd_pins sys_rstgen/ext_reset_in]
|
||||||
connect_bd_net -net sys_rst_s [get_bd_pins axi_ddr_cntrl_1/sys_rst]
|
connect_bd_net -net sys_rst_s [get_bd_pins axi_ddr_cntrl/sys_rst]
|
||||||
|
|
||||||
connect_bd_net -net sys_clk_p_s [get_bd_ports sys_clk_p] [get_bd_pins axi_ddr_cntrl_1/sys_clk_p]
|
connect_bd_net -net sys_clk_p_s [get_bd_ports sys_clk_p] [get_bd_pins axi_ddr_cntrl/sys_clk_p]
|
||||||
connect_bd_net -net sys_clk_n_s [get_bd_ports sys_clk_n] [get_bd_pins axi_ddr_cntrl_1/sys_clk_n]
|
connect_bd_net -net sys_clk_n_s [get_bd_ports sys_clk_n] [get_bd_pins axi_ddr_cntrl/sys_clk_n]
|
||||||
|
|
||||||
connect_bd_net -net ddr3_const_0_const [get_bd_ports ddr3_1_n] [get_bd_pins ddr3_const_0/const]
|
connect_bd_net -net sys_const_ddr3_0_const [get_bd_ports ddr3_1_n] [get_bd_pins sys_const_ddr3_0/const]
|
||||||
connect_bd_net -net ddr3_const_1_const [get_bd_ports ddr3_1_p] [get_bd_pins ddr3_const_1/const]
|
connect_bd_net -net sys_const_ddr3_1_const [get_bd_ports ddr3_1_p] [get_bd_pins sys_const_ddr3_1/const]
|
||||||
connect_bd_intf_net -intf_net axi_ddr_cntrl_1_ddr3 [get_bd_intf_ports ddr3] [get_bd_intf_pins axi_ddr_cntrl_1/DDR3]
|
connect_bd_intf_net -intf_net axi_ddr_cntrl_ddr3 [get_bd_intf_ports ddr3] [get_bd_intf_pins axi_ddr_cntrl/DDR3]
|
||||||
connect_bd_intf_net -intf_net axi_ethernetlite_1_mii [get_bd_intf_ports mii] [get_bd_intf_pins axi_ethernetlite_1/mii]
|
connect_bd_intf_net -intf_net axi_ethernet_mdio [get_bd_intf_ports mdio] [get_bd_intf_pins axi_ethernet/mdio]
|
||||||
connect_bd_intf_net -intf_net axi_ethernetlite_1_mdio [get_bd_intf_ports mdio] [get_bd_intf_pins axi_ethernetlite_1/mdio]
|
connect_bd_intf_net -intf_net axi_ethernet_mii [get_bd_intf_ports mii] [get_bd_intf_pins axi_ethernet/mii]
|
||||||
|
|
||||||
connect_bd_net -net axi_uart_1_sin [get_bd_ports uart_sin] [get_bd_pins axi_uart_1/rx]
|
connect_bd_net -net axi_uart_sin [get_bd_ports uart_sin] [get_bd_pins axi_uart/rx]
|
||||||
connect_bd_net -net axi_uart_1_sout [get_bd_ports uart_sout] [get_bd_pins axi_uart_1/tx]
|
connect_bd_net -net axi_uart_sout [get_bd_ports uart_sout] [get_bd_pins axi_uart/tx]
|
||||||
|
|
||||||
connect_bd_intf_net -intf_net axi_gpio_1_gpio [get_bd_intf_ports gpio_lcd] [get_bd_intf_pins axi_gpio_1/gpio]
|
connect_bd_intf_net -intf_net axi_gpio_lcd_gpio [get_bd_intf_ports gpio_lcd] [get_bd_intf_pins axi_gpio_lcd/gpio]
|
||||||
connect_bd_intf_net -intf_net axi_gpio_2_gpio [get_bd_intf_ports gpio_sw] [get_bd_intf_pins axi_gpio_2/gpio]
|
connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio [get_bd_intf_ports gpio_sw] [get_bd_intf_pins axi_gpio_sw_led/gpio]
|
||||||
connect_bd_intf_net -intf_net axi_gpio_2_gpio2 [get_bd_intf_ports gpio_led] [get_bd_intf_pins axi_gpio_2/gpio2]
|
connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio2 [get_bd_intf_ports gpio_led] [get_bd_intf_pins axi_gpio_sw_led/gpio2]
|
||||||
|
|
||||||
connect_bd_net -net axi_iic_1_rstn [get_bd_ports iic_rstn] [get_bd_pins axi_iic_1/gpo]
|
connect_bd_net -net axi_iic_main_rstn [get_bd_ports iic_rstn] [get_bd_pins axi_iic_main/gpo]
|
||||||
connect_bd_intf_net -intf_net axi_iic_1_iic [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_1/iic]
|
connect_bd_intf_net -intf_net axi_iic_main_iic [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_main/iic]
|
||||||
|
|
||||||
# hdmi peripherals
|
# hdmi peripherals
|
||||||
|
|
||||||
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn]
|
||||||
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_hdmi_dma/axi_resetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_dma/axi_resetn]
|
||||||
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_hdmi_core/s_axi_aresetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_core/s_axi_aresetn]
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_clkgen/s_axi_aclk]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/s_axi_aclk]
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_clkgen/drp_clk]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/drp_clk]
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk]
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk]
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk]
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_core/s_axi_aclk]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/s_axi_aclk]
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk]
|
||||||
connect_bd_net -net axi_ddr_cntrl_1_200mhz [get_bd_pins axi_hdmi_clkgen/clk]
|
connect_bd_net -net sys_200m_clk [get_bd_pins axi_hdmi_clkgen/clk]
|
||||||
|
|
||||||
connect_bd_intf_net -intf_net axi_interconnect_1_m08 [get_bd_intf_pins axi_interconnect_1/M08_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi]
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08 [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi]
|
||||||
connect_bd_intf_net -intf_net axi_interconnect_1_m09 [get_bd_intf_pins axi_interconnect_1/M09_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE]
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09 [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE]
|
||||||
connect_bd_intf_net -intf_net axi_interconnect_1_m10 [get_bd_intf_pins axi_interconnect_1/M10_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi]
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10 [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi]
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M08_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M09_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M10_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M08_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M09_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M10_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
|
||||||
|
|
||||||
connect_bd_intf_net -intf_net axi_interconnect_2_s02 [get_bd_intf_pins axi_interconnect_2/S02_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S]
|
connect_bd_intf_net -intf_net axi_mem_interconnect_s02 [get_bd_intf_pins axi_mem_interconnect/S02_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S]
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S02_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S02_ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S02_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S02_ACLK] $sys_100m_clk_source
|
||||||
|
|
||||||
connect_bd_net -net concat_intc_1_intr_06 [get_bd_pins concat_intc_1/In6] [get_bd_pins axi_hdmi_dma/mm2s_introut]
|
connect_bd_net -net sys_concat_intc_intr_06 [get_bd_pins sys_concat_intc/In6] [get_bd_pins axi_hdmi_dma/mm2s_introut]
|
||||||
|
|
||||||
connect_bd_net -net axi_hdmi_core_hdmi_out_clk [get_bd_ports hdmi_out_clk] [get_bd_pins axi_hdmi_core/hdmi_out_clk]
|
connect_bd_net -net axi_hdmi_core_hdmi_out_clk [get_bd_ports hdmi_out_clk] [get_bd_pins axi_hdmi_core/hdmi_out_clk]
|
||||||
connect_bd_net -net axi_hdmi_core_hdmi_hsync [get_bd_ports hdmi_hsync] [get_bd_pins axi_hdmi_core/hdmi_16_hsync]
|
connect_bd_net -net axi_hdmi_core_hdmi_hsync [get_bd_ports hdmi_hsync] [get_bd_pins axi_hdmi_core/hdmi_16_hsync]
|
||||||
|
|
@ -364,61 +370,64 @@ connect_bd_net -net axi_hdmi_core_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_f
|
||||||
|
|
||||||
# spdif audio
|
# spdif audio
|
||||||
|
|
||||||
connect_bd_intf_net -intf_net axi_interconnect_1_m11 [get_bd_intf_pins axi_interconnect_1/M11_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN]
|
||||||
connect_bd_intf_net -intf_net axi_interconnect_1_m12 [get_bd_intf_pins axi_interconnect_1/M12_AXI] [get_bd_intf_pins axi_spdif_tx_dma/S_AXI_LITE]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/S_AXIS_ARESETN]
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M11_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_dma/axi_resetn]
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_1/M12_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK]
|
||||||
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/s_axi_lite_aclk]
|
||||||
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_spdif_tx_core/S_AXIS_ARESETN]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXIS_ACLK]
|
||||||
connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_spdif_tx_dma/axi_resetn]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/m_axi_mm2s_aclk]
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M11_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/m_axi_sg_aclk]
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_1/M12_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1]
|
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK]
|
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_spdif_tx_dma/s_axi_lite_aclk]
|
|
||||||
|
|
||||||
connect_bd_intf_net -intf_net axi_interconnect_2_s03 [get_bd_intf_pins axi_interconnect_2/S03_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_SG]
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11 [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi]
|
||||||
connect_bd_intf_net -intf_net axi_interconnect_2_s04 [get_bd_intf_pins axi_interconnect_2/S04_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_MM2S]
|
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12 [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_spdif_tx_dma/S_AXI_LITE]
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S03_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi_interconnect_2/S04_ARESETN] [get_bd_pins proc_sys_reset_1/interconnect_aresetn]
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S03_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_interconnect_2/S04_ACLK] [get_bd_pins proc_sys_clock_1/clk_out1]
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_spdif_tx_core/S_AXIS_ACLK]
|
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_spdif_tx_dma/m_axi_mm2s_aclk]
|
|
||||||
connect_bd_net -net proc_sys_clk_1_100mhz [get_bd_pins axi_spdif_tx_dma/m_axi_sg_aclk]
|
|
||||||
|
|
||||||
connect_bd_intf_net -intf_net axi_spdif_tx_dma_m_axis_mm2s [get_bd_intf_pins axi_spdif_tx_core/S_AXIS] [get_bd_intf_pins axi_spdif_tx_dma/M_AXIS_MM2S]
|
connect_bd_intf_net -intf_net axi_mem_interconnect_s03 [get_bd_intf_pins axi_mem_interconnect/S03_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_SG]
|
||||||
|
connect_bd_intf_net -intf_net axi_mem_interconnect_s04 [get_bd_intf_pins axi_mem_interconnect/S04_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_MM2S]
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S03_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S04_ARESETN] $sys_100m_resetn_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S03_ACLK] $sys_100m_clk_source
|
||||||
|
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S04_ACLK] $sys_100m_clk_source
|
||||||
|
|
||||||
connect_bd_net -net concat_intc_1_intr_07 [get_bd_pins concat_intc_1/In7] [get_bd_pins axi_spdif_tx_dma/mm2s_introut]
|
connect_bd_net -net axi_spdif_tx_dma_mm2s_valid [get_bd_pins axi_spdif_tx_core/S_AXIS_TVALID] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tvalid]
|
||||||
|
connect_bd_net -net axi_spdif_tx_dma_mm2s_data [get_bd_pins axi_spdif_tx_core/S_AXIS_TDATA] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tdata]
|
||||||
|
connect_bd_net -net axi_spdif_tx_dma_mm2s_last [get_bd_pins axi_spdif_tx_core/S_AXIS_TLAST] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tlast]
|
||||||
|
connect_bd_net -net axi_spdif_tx_dma_mm2s_ready [get_bd_pins axi_spdif_tx_core/S_AXIS_TREADY] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tready]
|
||||||
|
|
||||||
connect_bd_net -net axi_ddr_cntrl_1_200mhz [get_bd_pins sys_audio_clkgen/clk_in1]
|
connect_bd_net -net sys_concat_intc_intr_07 [get_bd_pins sys_concat_intc/In7] [get_bd_pins axi_spdif_tx_dma/mm2s_introut]
|
||||||
|
|
||||||
|
connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1]
|
||||||
connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk]
|
connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk]
|
||||||
connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o]
|
connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o]
|
||||||
|
|
||||||
# address mapping
|
# address mapping
|
||||||
|
|
||||||
create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs dlmb_cntlr/SLMB/Mem] SEG_data_dlmb_cntlr
|
create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem] SEG_data_dlmb_cntlr
|
||||||
create_bd_addr_seg -range 0x00001000 -offset 0x41400000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs mb_debug/S_AXI/Reg] SEG_data_mb_debug
|
create_bd_addr_seg -range 0x00001000 -offset 0x41400000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs sys_mb_debug/S_AXI/Reg] SEG_data_mb_debug
|
||||||
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_data_ddr_cntrl_1
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_data_ddr_cntrl
|
||||||
create_bd_addr_seg -range 0x00002000 -offset 0x40E00000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_ethernetlite_1/s_axi/Reg] SEG_data_ethernetlite_1
|
create_bd_addr_seg -range 0x00002000 -offset 0x40E00000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ethernet/s_axi/Reg] SEG_data_ethernetlite
|
||||||
create_bd_addr_seg -range 0x00010000 -offset 0x40010000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_gpio_1/s_axi/Reg] SEG_data_gpio_1
|
create_bd_addr_seg -range 0x00010000 -offset 0x40010000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_gpio_lcd/s_axi/Reg] SEG_data_gpio_lcd
|
||||||
create_bd_addr_seg -range 0x00010000 -offset 0x40020000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_gpio_2/s_axi/Reg] SEG_data_gpio_2
|
create_bd_addr_seg -range 0x00010000 -offset 0x40020000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_gpio_sw_led/s_axi/Reg] SEG_data_gpio_sw_led
|
||||||
create_bd_addr_seg -range 0x00010000 -offset 0x41600000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_iic_1/s_axi/Reg] SEG_data_iic_1
|
create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_intc/s_axi/Reg] SEG_data_intc
|
||||||
create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_intc_1/s_axi/Reg] SEG_data_intc_1
|
create_bd_addr_seg -range 0x00010000 -offset 0x41C00000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_timer/s_axi/Reg] SEG_data_timer
|
||||||
create_bd_addr_seg -range 0x00010000 -offset 0x41C00000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_timer_1/s_axi/Reg] SEG_data_timer_1
|
create_bd_addr_seg -range 0x00010000 -offset 0x40600000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_uart/s_axi/Reg] SEG_data_uart
|
||||||
create_bd_addr_seg -range 0x00010000 -offset 0x40600000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_uart_1/s_axi/Reg] SEG_data_uart_1
|
|
||||||
|
|
||||||
create_bd_addr_seg -range 0x00010000 -offset 0x79000000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite] SEG_data_hdmi_clkgen
|
create_bd_addr_seg -range 0x00010000 -offset 0x41600000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_iic_main/s_axi/Reg] SEG_data_iic
|
||||||
create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg] SEG_data_hdmi_dma
|
create_bd_addr_seg -range 0x00010000 -offset 0x79000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite] SEG_data_hdmi_clkgen
|
||||||
create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite] SEG_data_hdmi_core
|
create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg] SEG_data_hdmi_dma
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite] SEG_data_hdmi_core
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0] SEG_data_spdif_tx_core
|
||||||
|
create_bd_addr_seg -range 0x00010000 -offset 0x41E00000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_spdif_tx_dma/S_AXI_LITE/Reg] SEG_data_spdif_tx_dma
|
||||||
|
|
||||||
create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0] SEG_data_spdif_tx_core
|
create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_instr_ilmb_cntlr
|
||||||
create_bd_addr_seg -range 0x00010000 -offset 0x41E00000 [get_bd_addr_spaces microblaze_1/Data] [get_bd_addr_segs axi_spdif_tx_dma/S_AXI_LITE/Reg] SEG_data_spdif_tx_dma
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_instr_ddr_cntrl
|
||||||
|
|
||||||
create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces microblaze_1/Instruction] [get_bd_addr_segs ilmb_cntlr/SLMB/Mem] SEG_instr_ilmb_cntlr
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||||
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_1/Instruction] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_instr_ddr_cntrl_1
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||||
|
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||||
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_mem_ddr_cntrl_1
|
|
||||||
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_axi_ddr_cntrl_1
|
|
||||||
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl_1/memmap/memaddr] SEG_axi_ddr_cntrl_1
|
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -126,10 +126,10 @@ set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS25} [get_ports spdif]
|
||||||
|
|
||||||
# clocks
|
# clocks
|
||||||
|
|
||||||
create_clock -name cpu_clk -period 10.00 [get_nets i_system_wrapper/system_i/proc_sys_clk_1_100mhz]
|
create_clock -name cpu_clk -period 10.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/ui_addn_clk_0]
|
||||||
create_clock -name m200_clk -period 5.00 [get_nets i_system_wrapper/system_i/axi_ddr_cntrl_1_200mhz]
|
create_clock -name m200_clk -period 5.00 [get_pins i_system_wrapper/system_i/axi_ddr_cntrl/ui_clk]
|
||||||
create_clock -name hdmi_clk -period 6.73 [get_nets i_system_wrapper/system_i/axi_hdmi_clkgen/inst/i_mmcm_drp/mmcm_clk_0_s]
|
create_clock -name hdmi_clk -period 6.73 [get_pins i_system_wrapper/system_i/axi_hdmi_clkgen/clk_0]
|
||||||
create_clock -name spdif_clk -period 50.00 [get_nets i_system_wrapper/system_i/sys_audio_clkgen_clk]
|
create_clock -name spdif_clk -period 50.00 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out1]
|
||||||
|
|
||||||
set_clock_groups -asynchronous -group {cpu_clk}
|
set_clock_groups -asynchronous -group {cpu_clk}
|
||||||
set_clock_groups -asynchronous -group {m200_clk}
|
set_clock_groups -asynchronous -group {m200_clk}
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,7 @@
|
||||||
<?xml version='1.0' encoding='UTF-8'?>
|
<?xml version='1.0' encoding='UTF-8'?>
|
||||||
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
|
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
|
||||||
<Project NoOfControllers="1" >
|
<Project NoOfControllers="1" >
|
||||||
<ModuleName>system_axi_ddr_cntrl_1_0</ModuleName>
|
<ModuleName>system_axi_ddr_cntrl_0</ModuleName>
|
||||||
<dci_inouts_inputs>1</dci_inouts_inputs>
|
<dci_inouts_inputs>1</dci_inouts_inputs>
|
||||||
<dci_inputs>1</dci_inputs>
|
<dci_inputs>1</dci_inputs>
|
||||||
<Debug_En>OFF</Debug_En>
|
<Debug_En>OFF</Debug_En>
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue