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ad_fmclidar1_ebz: Add a dummy ADC channel with TIA channel info 

Software has to know which TIA channel was used for a particular capture.
Define an additional dummy ADC channel which will provide this
information. Currently this channel is always enabled.
main
Istvan Csomortani 2019-05-09 15:54:25 +01:00 committed by István Csomortáni
parent d096b8f6f4
commit 3290838743
3 changed files with 81 additions and 3 deletions
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15
projects/ad_fmclidar1_ebz/common/ad_fmclidar1_ebz_bd.tcl
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@ -35,7 +35,7 @@ adi_axi_jesd204_rx_create ad9694_jesd $NUM_OF_LANES
adi_tpl_jesd204_rx_create ad9694_tpl_core $NUM_OF_LANES $NUM_OF_CHANNELS $SAMPLES_PER_FRAME $SAMPLE_WIDTH
ad_ip_instance util_cpack2 util_ad9694_cpack [list \
NUM_OF_CHANNELS $NUM_OF_CHANNELS \
NUM_OF_CHANNELS [expr $NUM_OF_CHANNELS + 1] \
SAMPLES_PER_CHANNEL [expr $CHANNEL_DATA_WIDTH / $SAMPLE_WIDTH] \
SAMPLE_DATA_WIDTH $SAMPLE_WIDTH \
]
@ -96,6 +96,11 @@ ad_ip_instance axi_laser_driver axi_laser_driver_0 [list \
create_bd_cell -type module -reference util_axis_syncgen util_axis_syncgen_0
set_property -dict [list CONFIG.ASYNC_SYNC {0}] [get_bd_cells util_axis_syncgen_0]
# software needs to know the used TIA channel selection for each transfer, so
# we create an addition dummy ADC channel whit this information
create_bd_cell -type module -reference util_tia_chsel util_tia_chsel_0
set_property -dict [list CONFIG.DATA_WIDTH {32}] [get_bd_cells util_tia_chsel_0]
# reference clocks & resets
create_bd_port -dir I -type clk rx_ref_clk
@ -168,6 +173,14 @@ ad_connect util_axis_syncgen_0/s_axis_ready VCC
ad_connect util_axis_syncgen_0/ext_sync axi_laser_driver_0/driver_pulse
ad_connect util_axis_syncgen_0/s_axis_sync ad9694_dma/s_axis_user
# connect the dummy ADC channel to cpack -- channel is always active
ad_connect rx_device_clk util_tia_chsel_0/clk
ad_connect util_ad9694_cpack/fifo_wr_data_$NUM_OF_CHANNELS util_tia_chsel_0/adc_data_tia_chsel
ad_connect axi_laser_driver_0/driver_pulse util_tia_chsel_0/adc_tia_chsel_en
ad_connect util_ad9694_cpack/enable_$NUM_OF_CHANNELS VCC
ad_connect axi_laser_driver_0/tia_chsel util_tia_chsel_0/tia_chsel
# interconnect (cpu)
ad_cpu_interconnect 0x44A50000 axi_ad9694_xcvr

62
projects/ad_fmclidar1_ebz/common/util_tia_chsel.v Normal file
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@ -0,0 +1,62 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_tia_chsel #(
parameter DATA_WIDTH = 32) (
input clk,
input adc_tia_chsel_en,
output [DATA_WIDTH-1:0] adc_data_tia_chsel,
input [ 1:0] tia_chsel);
(* keep = "TRUE" *)reg [DATA_WIDTH-1:0] adc_data_tia_chsel_int;
genvar i;
generate
for (i=0; i<DATA_WIDTH/16; i=i+1) begin
always @(posedge clk) begin
if (adc_tia_chsel_en)
adc_data_tia_chsel_int[i*16+:16] <= {14'h0, tia_chsel};
end
end
endgenerate
assign adc_data_tia_chsel = adc_data_tia_chsel_int;
endmodule

7
projects/ad_fmclidar1_ebz/zc706/system_bd.tcl
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@ -11,13 +11,16 @@ set ADC_RESOLUTION 8 ; # N & NP
set CHANNEL_DATA_WIDTH [expr 32 * $NUM_OF_LANES / $NUM_OF_CHANNELS]
set ADC_DATA_WIDTH [expr $CHANNEL_DATA_WIDTH * $NUM_OF_CHANNELS]
set DMA_DATA_WIDTH [expr $ADC_DATA_WIDTH < 128 ? $ADC_DATA_WIDTH : 128]
# we have to calculate with an additional dummy channel for TIA
set DMA_DATA_WIDTH [expr $ADC_DATA_WIDTH > 127 ? 256 : \
$ADC_DATA_WIDTH > 63 ? 128 : 64]
set SAMPLE_WIDTH [expr $ADC_RESOLUTION > 8 ? 16 : 8]
# add RTL sources which will be instantiated in system_bd directly
adi_project_files ad_fmclidar1_ebz_zc706 [list \
"$ad_hdl_dir/library/util_cdc/sync_bits.v" \
"$ad_hdl_dir/library/common/util_axis_syncgen.v" ]
"../common/util_tia_chsel.v" \
"../common/util_axis_syncgen.v" ]
# source all the block designs
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl