zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Remove unused DMA underflow signal from ADC DMA interface 

The ADC DMA will never underflow and unsurprisingly the adc_dunf signal is
never used anywhere. It is very unlikely it will ever be used, so remove
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-05-05 19:17:45 +02:00 committed by Lars-Peter Clausen
parent bd251a5fd5
commit 324da5f112
39 changed files with 4 additions and 77 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
library/axi_ad6676/axi_ad6676.v
View File

@ -59,7 +59,6 @@ module axi_ad6676 #(
output adc_enable_1,
output [31:0] adc_data_1,
input adc_dovf,
input adc_dunf,
// axi interface
@ -231,7 +230,6 @@ module axi_ad6676 #(
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sref_sync (),

1
library/axi_ad6676/axi_ad6676_ip.tcl
View File

@ -27,7 +27,6 @@ adi_ip_properties axi_ad6676
set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

2
library/axi_ad9250/axi_ad9250.v
View File

@ -59,7 +59,6 @@ module axi_ad9250 #(
output adc_enable_b,
output [31:0] adc_data_b,
input adc_dovf,
input adc_dunf,
// axi interface
@ -225,7 +224,6 @@ module axi_ad9250 #(
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sref_sync (),

1
library/axi_ad9250/axi_ad9250_hw.tcl
View File

@ -80,5 +80,4 @@ set_interface_property adc_ch_1 associatedClock if_rx_clk
set_interface_property adc_ch_1 associatedReset none
ad_alt_intf signal adc_dovf input 1 ovf
ad_alt_intf signal adc_dunf input 1 unf

1
library/axi_ad9250/axi_ad9250_ip.tcl
View File

@ -28,7 +28,6 @@ adi_ip_properties axi_ad9250
set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

2
library/axi_ad9265/axi_ad9265.v
View File

@ -63,7 +63,6 @@ module axi_ad9265 #(
output adc_enable,
output [15:0] adc_data,
input adc_dovf,
input adc_dunf,
// axi interface
@ -242,7 +241,6 @@ module axi_ad9265 #(
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sref_sync (),

1
library/axi_ad9265/axi_ad9265_ip.tcl
View File

@ -29,7 +29,6 @@ adi_ip_files axi_ad9265 [list \
adi_ip_properties axi_ad9265
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

2
library/axi_ad9361/axi_ad9361.v
View File

@ -133,7 +133,6 @@ module axi_ad9361 #(
output adc_valid_q1,
output [15:0] adc_data_q1,
input adc_dovf,
input adc_dunf,
output adc_r1_mode,
output dac_enable_i0,
@ -602,7 +601,6 @@ module axi_ad9361 #(
.adc_valid_q1 (adc_valid_q1_s),
.adc_data_q1 (adc_data_q1_s),
.adc_dovf (adc_dovf),
.adc_dunf (adc_dunf),
.up_adc_gpio_in (up_adc_gpio_in),
.up_adc_gpio_out (up_adc_gpio_out),
.up_pps_rcounter (up_pps_rcounter_s),

1
library/axi_ad9361/axi_ad9361_hw.tcl
View File

@ -114,7 +114,6 @@ set_interface_property adc_ch_3 associatedClock if_clk
set_interface_property adc_ch_3 associatedReset none
ad_alt_intf signal adc_dovf input 1 ovf
ad_alt_intf signal adc_dunf input 1 unf
ad_alt_intf signal adc_r1_mode output 1 r1_mode
add_interface dac_ch_0 conduit end

2
library/axi_ad9361/axi_ad9361_rx.v
View File

@ -89,7 +89,6 @@ module axi_ad9361_rx #(
output adc_valid_q1,
output [15:0] adc_data_q1,
input adc_dovf,
input adc_dunf,
// gpio
@ -349,7 +348,6 @@ module axi_ad9361_rx #(
.adc_status (adc_status),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sref_sync (),

4
library/axi_ad9371/axi_ad9371.v
View File

@ -81,7 +81,6 @@ module axi_ad9371 #(
output adc_valid_q1,
output [ 15:0] adc_data_q1,
input adc_dovf,
input adc_dunf,
output adc_os_enable_i0,
output adc_os_valid_i0,
@ -90,7 +89,6 @@ module axi_ad9371 #(
output adc_os_valid_q0,
output [ 31:0] adc_os_data_q0,
input adc_os_dovf,
input adc_os_dunf,
output dac_enable_i0,
output dac_valid_i0,
@ -220,7 +218,6 @@ module axi_ad9371 #(
.adc_valid_q1 (adc_valid_q1),
.adc_data_q1 (adc_data_q1),
.adc_dovf (adc_dovf),
.adc_dunf (adc_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
@ -249,7 +246,6 @@ module axi_ad9371 #(
.adc_os_valid_q0 (adc_os_valid_q0),
.adc_os_data_q0 (adc_os_data_q0),
.adc_os_dovf (adc_os_dovf),
.adc_os_dunf (adc_os_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),

2
library/axi_ad9371/axi_ad9371_hw.tcl
View File

@ -138,7 +138,6 @@ set_interface_property adc_ch_3 associatedClock if_adc_clk
set_interface_property adc_ch_3 associatedReset none
ad_alt_intf signal adc_dovf input 1 ovf
ad_alt_intf signal adc_dunf input 1 unf
# adc-os-channel interface
@ -159,7 +158,6 @@ set_interface_property adc_os_ch_1 associatedClock if_adc_os_clk
set_interface_property adc_os_ch_1 associatedReset none
ad_alt_intf signal adc_os_dovf input 1 ovf
ad_alt_intf signal adc_os_dunf input 1 unf
# dac-channel interface

1
library/axi_ad9371/axi_ad9371_ip.tcl
View File

@ -37,7 +37,6 @@ adi_ip_files axi_ad9371 [list \
adi_ip_properties axi_ad9371
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dac_tx_ready* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *adc_rx_valid* -of_objects [ipx::current_core]]

2
library/axi_ad9371/axi_ad9371_rx.v
View File

@ -61,7 +61,6 @@ module axi_ad9371_rx #(
output adc_valid_q1,
output [ 15:0] adc_data_q1,
input adc_dovf,
input adc_dunf,
// processor interface
@ -271,7 +270,6 @@ module axi_ad9371_rx #(
.adc_status (1'b1),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sref_sync (),

2
library/axi_ad9371/axi_ad9371_rx_os.v
View File

@ -56,7 +56,6 @@ module axi_ad9371_rx_os #(
output adc_os_valid_q0,
output [ 31:0] adc_os_data_q0,
input adc_os_dovf,
input adc_os_dunf,
// processor interface
@ -188,7 +187,6 @@ module axi_ad9371_rx_os #(
.adc_status (1'b1),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_os_dovf),
.adc_status_unf (adc_os_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sref_sync (),

1
library/axi_ad9434/axi_ad9434_core.v
View File

@ -165,7 +165,6 @@ module axi_ad9434_core #(
.adc_status (adc_status),
.adc_sync_status (1'd0),
.adc_status_ovf (dma_dovf),
.adc_status_unf (1'b0),
.adc_clk_ratio (32'd4),
.adc_start_code (),
.adc_sref_sync (),

2
library/axi_ad9467/axi_ad9467.v
View File

@ -61,7 +61,6 @@ module axi_ad9467#(
output adc_enable,
output [15:0] adc_data,
input adc_dovf,
input adc_dunf,
// axi interface
@ -229,7 +228,6 @@ module axi_ad9467#(
.adc_status (1'b1),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'b1),
.adc_start_code (),
.adc_sref_sync (),

1
library/axi_ad9467/axi_ad9467_ip.tcl
View File

@ -29,7 +29,6 @@ adi_ip_files axi_ad9467 [list \
adi_ip_properties axi_ad9467
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

2
library/axi_ad9625/axi_ad9625.v
View File

@ -56,7 +56,6 @@ module axi_ad9625 #(
output adc_enable,
output [255:0] adc_data,
input adc_dovf,
input adc_dunf,
output [ 15:0] adc_sref,
input [ 3:0] adc_raddr_in,
output [ 3:0] adc_raddr_out,
@ -197,7 +196,6 @@ module axi_ad9625 #(
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd16),
.adc_start_code (),
.adc_sync (),

1
library/axi_ad9625/axi_ad9625_ip.tcl
View File

@ -28,7 +28,6 @@ adi_ip_files axi_ad9625 [list \
adi_ip_properties axi_ad9625
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]

2
library/axi_ad9671/axi_ad9671.v
View File

@ -56,7 +56,6 @@ module axi_ad9671 #(
output [ 7:0] adc_enable,
output [127:0] adc_data,
input adc_dovf,
input adc_dunf,
input adc_sync_in,
output adc_sync_out,
input [ 3:0] adc_raddr_in,
@ -231,7 +230,6 @@ module axi_ad9671 #(
.adc_status (adc_status_s),
.adc_sync_status (adc_sync_status_s),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (adc_start_code),
.adc_sref_sync (),

1
library/axi_ad9671/axi_ad9671_hw.tcl
View File

@ -87,5 +87,4 @@ set_interface_property adc_ch associatedClock if_rx_clk
set_interface_property adc_ch associatedReset none
ad_alt_intf signal adc_dovf input 1 ovf
ad_alt_intf signal adc_dunf input 1 unf

1
library/axi_ad9671/axi_ad9671_ip.tcl
View File

@ -29,7 +29,6 @@ adi_ip_properties axi_ad9671
set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *sync_in* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]]

2
library/axi_ad9680/axi_ad9680.v
View File

@ -58,7 +58,6 @@ module axi_ad9680 #(
output adc_valid_1,
output [63:0] adc_data_1,
input adc_dovf,
input adc_dunf,
// axi interface
@ -230,7 +229,6 @@ module axi_ad9680 #(
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd4),
.adc_start_code (),
.adc_sref_sync (),

1
library/axi_ad9680/axi_ad9680_hw.tcl
View File

@ -79,5 +79,4 @@ set_interface_property adc_ch_1 associatedClock if_rx_clk
set_interface_property adc_ch_1 associatedReset none
ad_alt_intf signal adc_dovf input 1 ovf
ad_alt_intf signal adc_dunf input 1 unf

1
library/axi_ad9680/axi_ad9680_ip.tcl
View File

@ -28,7 +28,6 @@ adi_ip_properties axi_ad9680
set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

2
library/axi_ad9684/axi_ad9684.v
View File

@ -62,7 +62,6 @@ module axi_ad9684 #(
output adc_enable_1,
output [31:0] adc_data_1,
input adc_dovf,
input adc_dunf,
// delay clock ports
@ -222,7 +221,6 @@ module axi_ad9684 #(
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'b1),
.adc_start_code (),
.adc_sref_sync(),

1
library/axi_ad9684/axi_ad9684_hw.tcl
View File

@ -87,7 +87,6 @@ set_interface_property adc_ch_1 associatedClock if_adc_clk
set_interface_property adc_ch_1 associatedReset none
ad_alt_intf signal adc_dovf input 1 ovf
ad_alt_intf signal adc_dunf input 1 unf
# SERDES instances and configurations

1
library/axi_ad9684/axi_ad9684_ip.tcl
View File

@ -32,7 +32,6 @@ adi_ip_files axi_ad9684 [list \
adi_ip_properties axi_ad9684
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
ipx::infer_bus_interface adc_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]

2
library/axi_ad9963/axi_ad9963.v
View File

@ -88,7 +88,6 @@ module axi_ad9963 #(
output adc_valid_q,
output [15:0] adc_data_q,
input adc_dovf,
input adc_dunf,
output dac_enable_i,
output dac_valid_i,
@ -234,7 +233,6 @@ module axi_ad9963 #(
.adc_valid_q (adc_valid_q),
.adc_data_q (adc_data_q),
.adc_dovf (adc_dovf),
.adc_dunf (adc_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),

2
library/axi_ad9963/axi_ad9963_rx.v
View File

@ -73,7 +73,6 @@ module axi_ad9963_rx #(
output adc_valid_q,
output [15:0] adc_data_q,
input adc_dovf,
input adc_dunf,
output up_adc_ce,
@ -226,7 +225,6 @@ module axi_ad9963_rx #(
.adc_status (adc_status),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sref_sync (),

4
library/axi_adrv9009/axi_adrv9009.v
View File

@ -81,7 +81,6 @@ module axi_adrv9009 #(
output adc_valid_q1,
output [ 15:0] adc_data_q1,
input adc_dovf,
input adc_dunf,
output adc_os_enable_i0,
output adc_os_valid_i0,
@ -90,7 +89,6 @@ module axi_adrv9009 #(
output adc_os_valid_q0,
output [ 31:0] adc_os_data_q0,
input adc_os_dovf,
input adc_os_dunf,
output dac_enable_i0,
output dac_valid_i0,
@ -220,7 +218,6 @@ module axi_adrv9009 #(
.adc_valid_q1 (adc_valid_q1),
.adc_data_q1 (adc_data_q1),
.adc_dovf (adc_dovf),
.adc_dunf (adc_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
@ -249,7 +246,6 @@ module axi_adrv9009 #(
.adc_os_valid_q0 (adc_os_valid_q0),
.adc_os_data_q0 (adc_os_data_q0),
.adc_os_dovf (adc_os_dovf),
.adc_os_dunf (adc_os_dunf),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),

2
library/axi_adrv9009/axi_adrv9009_hw.tcl
View File

@ -138,7 +138,6 @@ set_interface_property adc_ch_3 associatedClock if_adc_clk
set_interface_property adc_ch_3 associatedReset none
ad_alt_intf signal adc_dovf input 1 ovf
ad_alt_intf signal adc_dunf input 1 unf
# adc-os-channel interface
@ -159,7 +158,6 @@ set_interface_property adc_os_ch_1 associatedClock if_adc_os_clk
set_interface_property adc_os_ch_1 associatedReset none
ad_alt_intf signal adc_os_dovf input 1 ovf
ad_alt_intf signal adc_os_dunf input 1 unf
# dac-channel interface

2
library/axi_adrv9009/axi_adrv9009_rx.v
View File

@ -61,7 +61,6 @@ module axi_adrv9009_rx #(
output adc_valid_q1,
output [ 15:0] adc_data_q1,
input adc_dovf,
input adc_dunf,
// processor interface
@ -271,7 +270,6 @@ module axi_adrv9009_rx #(
.adc_status (1'b1),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sref_sync (),

2
library/axi_adrv9009/axi_adrv9009_rx_os.v
View File

@ -56,7 +56,6 @@ module axi_adrv9009_rx_os #(
output adc_os_valid_q0,
output [ 31:0] adc_os_data_q0,
input adc_os_dovf,
input adc_os_dunf,
// processor interface
@ -188,7 +187,6 @@ module axi_adrv9009_rx_os #(
.adc_status (1'b1),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_os_dovf),
.adc_status_unf (adc_os_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sref_sync (),

1
library/axi_generic_adc/axi_generic_adc.v
View File

@ -127,7 +127,6 @@ up_adc_common #(.ID(ID)) i_up_adc_common (
.adc_status ('h00),
.adc_sync_status (1'b1),
.adc_status_ovf (adc_dovf),
.adc_status_unf (1'b0),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sref_sync (),

1
library/axi_mc_current_monitor/axi_mc_current_monitor.v
View File

@ -344,7 +344,6 @@ up_adc_common i_up_adc_common(
.adc_status(1'b1),
.adc_sync_status(1'b1),
.adc_status_ovf(1'b0),
.adc_status_unf(1'b0),
.adc_clk_ratio(32'd1),
.adc_start_code(),
.adc_sref_sync(),

1
library/axi_mc_speed/axi_mc_speed.v
View File

@ -188,7 +188,6 @@ up_adc_common i_up_adc_common(
.adc_status(1'b1),
.adc_sync_status(1'b1),
.adc_status_ovf(1'b0),
.adc_status_unf(1'b0),
.adc_clk_ratio(32'd1),
.adc_start_code(),
.adc_sref_sync(),

19
library/common/up_adc_common.v
View File

@ -61,7 +61,6 @@ module up_adc_common #(
input adc_status,
input adc_sync_status,
input adc_status_ovf,
input adc_status_unf,
input [31:0] adc_clk_ratio,
output [31:0] adc_start_code,
output adc_sref_sync,
@ -127,7 +126,6 @@ module up_adc_common #(
reg up_adc_ddr_edgesel = 'd0;
reg up_adc_pin_mode = 'd0;
reg up_status_ovf = 'd0;
reg up_status_unf = 'd0;
reg [ 7:0] up_usr_chanmax_int = 'd0;
reg [31:0] up_adc_start_code = 'd0;
reg [31:0] up_adc_gpio_out_int = 'd0;
@ -142,7 +140,6 @@ module up_adc_common #(
wire up_status_s;
wire up_sync_status_s;
wire up_status_ovf_s;
wire up_status_unf_s;
wire up_cntrl_xfer_done_s;
wire [31:0] up_adc_clk_count_s;
wire up_drp_status_s;
@ -277,18 +274,12 @@ module up_adc_common #(
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_status_ovf <= 'd0;
up_status_unf <= 'd0;
end else begin
if (up_status_ovf_s == 1'b1) begin
up_status_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_status_ovf <= up_status_ovf & ~up_wdata[2];
end
if (up_status_unf_s == 1'b1) begin
up_status_unf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_status_unf <= up_status_unf & ~up_wdata[1];
end
end
end
@ -393,7 +384,7 @@ module up_adc_common #(
8'h1d: up_rdata_int <= {14'd0, up_drp_locked, up_drp_status_s, 16'b0};
8'h1e: up_rdata_int <= up_drp_wdata;
8'h1f: up_rdata_int <= up_drp_rdata_hold_s;
8'h22: up_rdata_int <= {29'd0, up_status_ovf, up_status_unf, 1'b0};
8'h22: up_rdata_int <= {29'd0, up_status_ovf, 2'b0};
8'h23: up_rdata_int <= 32'd8;
8'h28: up_rdata_int <= {24'd0, up_usr_chanmax_in};
8'h29: up_rdata_int <= up_adc_start_code;
@ -436,19 +427,17 @@ module up_adc_common #(
adc_ddr_edgesel,
adc_pin_mode}));
up_xfer_status #(.DATA_WIDTH(4)) i_xfer_status (
up_xfer_status #(.DATA_WIDTH(3)) i_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_sync_status_s,
up_status_s,
up_status_ovf_s,
up_status_unf_s}),
up_status_ovf_s}),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_status ({ adc_sync_status,
adc_status,
adc_status_ovf,
adc_status_unf}));
adc_status_ovf}));
// adc clock monitor