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axi_xcvrlb: added new parameters to IP 

added PLL locked reg to axi regmap; IP now recognizez xcvr type
automatically
main
Arpadi 2019-08-06 11:56:09 +03:00 committed by sarpadi
parent 9180d4dd39
commit 3235c9189c
3 changed files with 41 additions and 8 deletions
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25
library/xilinx/axi_xcvrlb/axi_xcvrlb.v
View File

@ -39,7 +39,10 @@ module axi_xcvrlb #(
// parameters
parameter NUM_OF_LANES = 1) (
parameter CPLL_FBDIV = 1,
parameter CPLL_FBDIV_4_5 = 5,
parameter NUM_OF_LANES = 1,
parameter XCVR_TYPE = 2) (
// transceiver interface
@ -79,6 +82,7 @@ module axi_xcvrlb #(
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg [31:0] up_status = 'd0;
reg [31:0] up_pll_locked = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
@ -92,6 +96,7 @@ module axi_xcvrlb #(
wire up_rreq_s;
wire [ 7:0] up_raddr_s;
wire [31:0] up_status_s;
wire [31:0] up_pll_locked_s;
// parameters
@ -102,6 +107,7 @@ module axi_xcvrlb #(
assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk;
assign up_status_s[31:NUM_OF_LANES] = 'd0;
assign up_pll_locked_s[31:NUM_OF_LANES] = 'd0;
// register access
@ -111,6 +117,7 @@ module axi_xcvrlb #(
up_scratch <= 'd0;
up_resetn <= 'd0;
up_status <= 'd0;
up_pll_locked <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h02)) begin
@ -124,6 +131,11 @@ module axi_xcvrlb #(
end else begin
up_status <= up_status_s | up_status;
end
if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h06)) begin
up_pll_locked <= up_pll_locked_s | (up_pll_locked & ~up_wdata_s);
end else begin
up_pll_locked <= up_pll_locked_s | up_pll_locked;
end
end
end
@ -139,6 +151,7 @@ module axi_xcvrlb #(
10'h002: up_rdata <= up_scratch;
10'h004: up_rdata <= {31'd0, up_resetn};
10'h005: up_rdata <= up_status;
10'h006: up_rdata <= up_pll_locked;
default: up_rdata <= 32'd0;
endcase
end else begin
@ -152,7 +165,11 @@ module axi_xcvrlb #(
genvar n;
generate
for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lanes
axi_xcvrlb_1 i_xcvrlb_1 (
axi_xcvrlb_1 #(
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV_4_5(CPLL_FBDIV_4_5),
.CPLL_FBDIV(CPLL_FBDIV))
i_xcvrlb_1 (
.ref_clk (ref_clk),
.rx_p (rx_p[n]),
.rx_n (rx_n[n]),
@ -161,7 +178,9 @@ module axi_xcvrlb #(
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_resetn (up_resetn),
.up_status (up_status_s[n]));
.up_status (up_status_s[n]),
.up_pll_locked (up_pll_locked_s[n])
);
end
endgenerate

19
library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
View File

@ -35,7 +35,14 @@
`timescale 1ns/1ps
module axi_xcvrlb_1 (
module axi_xcvrlb_1 #(
// parameters
parameter CPLL_FBDIV = 1,
parameter CPLL_FBDIV_4_5 = 5,
parameter XCVR_TYPE = 2
)(
// transceiver interface
@ -50,7 +57,8 @@ module axi_xcvrlb_1 (
input up_rstn,
input up_clk,
input up_resetn,
output up_status);
output up_status,
output up_pll_locked);
// internal registers
@ -189,6 +197,7 @@ module axi_xcvrlb_1 (
assign up_rst_s = up_rst_cnt[3];
assign up_user_ready_s = up_user_ready_cnt[6];
assign up_pll_locked_s = up_rx_pll_locked_s & up_tx_pll_locked_s;
assign up_pll_locked = up_pll_locked_s;
assign up_rst_done_s = up_rx_rst_done_s & up_tx_rst_done_s;
always @(negedge up_rstn or posedge up_clk) begin
@ -241,9 +250,9 @@ module axi_xcvrlb_1 (
.d_data_status ({rx_pn_err_s, rx_pn_oos_s}));
util_adxcvr_xch #(
.XCVR_TYPE (2),
.CPLL_FBDIV (2),
.CPLL_FBDIV_4_5 (5),
.XCVR_TYPE (XCVR_TYPE),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5),
.TX_OUT_DIV (1),
.TX_CLK25_DIV (10),
.RX_OUT_DIV (1),

5
library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl
View File

@ -14,6 +14,9 @@ adi_ip_files axi_xcvrlb [list \
adi_ip_properties_lite axi_xcvrlb
adi_init_bd_tcl
adi_ip_bd axi_xcvrlb "bd/bd.tcl"
ipx::remove_all_bus_interface [ipx::current_core]
set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
@ -55,5 +58,7 @@ ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::
set_property range {1024} [ipx::get_address_blocks axi_lite \
-of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
adi_add_auto_fpga_spec_params
ipx::save_core [ipx::current_core]