From 321b82398b7d6335da6b5e37a351e253e2751b51 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Mon, 25 Nov 2019 10:04:51 +0200 Subject: [PATCH] Add cn0506_rmii/zed support on revB --- projects/cn0506_rmii/Makefile | 6 + projects/cn0506_rmii/zed/Makefile | 21 ++ projects/cn0506_rmii/zed/README.rst | 3 + projects/cn0506_rmii/zed/system_bd.tcl | 59 ++++ projects/cn0506_rmii/zed/system_constr.xdc | 48 ++++ projects/cn0506_rmii/zed/system_project.tcl | 14 + projects/cn0506_rmii/zed/system_top.v | 286 ++++++++++++++++++++ 7 files changed, 437 insertions(+) create mode 100644 projects/cn0506_rmii/Makefile create mode 100644 projects/cn0506_rmii/zed/Makefile create mode 100644 projects/cn0506_rmii/zed/README.rst create mode 100644 projects/cn0506_rmii/zed/system_bd.tcl create mode 100644 projects/cn0506_rmii/zed/system_constr.xdc create mode 100644 projects/cn0506_rmii/zed/system_project.tcl create mode 100644 projects/cn0506_rmii/zed/system_top.v diff --git a/projects/cn0506_rmii/Makefile b/projects/cn0506_rmii/Makefile new file mode 100644 index 000000000..4af18d6e7 --- /dev/null +++ b/projects/cn0506_rmii/Makefile @@ -0,0 +1,6 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/cn0506_rmii/zed/Makefile b/projects/cn0506_rmii/zed/Makefile new file mode 100644 index 000000000..b0c2b59bd --- /dev/null +++ b/projects/cn0506_rmii/zed/Makefile @@ -0,0 +1,21 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := cn0506_rmii_zed + +M_DEPS += ../../common/zed/zed_system_constr.xdc +M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_iobuf.v + +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hdmi_tx +LIB_DEPS += axi_i2s_adi +LIB_DEPS += axi_spdif_tx +LIB_DEPS += axi_sysid +LIB_DEPS += sysid_rom +LIB_DEPS += util_i2c_mixer + +include ../../scripts/project-xilinx.mk diff --git a/projects/cn0506_rmii/zed/README.rst b/projects/cn0506_rmii/zed/README.rst new file mode 100644 index 000000000..b37fb6ca4 --- /dev/null +++ b/projects/cn0506_rmii/zed/README.rst @@ -0,0 +1,3 @@ +- VADJ 1.8V to 3.3V +- RMII mode, using a MII-to-RMII converter. Connected to PS7's Ethernet 0(PHY 0) and Ethernet 1(PHY 1) + diff --git a/projects/cn0506_rmii/zed/system_bd.tcl b/projects/cn0506_rmii/zed/system_bd.tcl new file mode 100644 index 000000000..70cbc6f91 --- /dev/null +++ b/projects/cn0506_rmii/zed/system_bd.tcl @@ -0,0 +1,59 @@ + +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl + +ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_ENET0_IO EMIO +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_IO EMIO +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {100 Mbps} +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_GRP_MDIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {100 Mbps} + +create_bd_port -dir O reset_a +create_bd_port -dir O reset_b +create_bd_port -dir I ref_clk_50_a +create_bd_port -dir I ref_clk_50_b +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rmii_rtl:1.0 RMII_PHY_M_0 +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rmii_rtl:1.0 RMII_PHY_M_1 +make_bd_intf_pins_external [get_bd_intf_pins sys_ps7/MDIO_ETHERNET_0] +make_bd_intf_pins_external [get_bd_intf_pins sys_ps7/MDIO_ETHERNET_1] + +ad_ip_instance mii_to_rmii mii_to_rmii_0 +ad_ip_parameter mii_to_rmii_0 CONFIG.C_MODE 1 +ad_ip_parameter mii_to_rmii_0 CONFIG.C_SPEED_100 1 +ad_ip_parameter mii_to_rmii_0 CONFIG.C_FIXED_SPEED 0 + +ad_connect mii_to_rmii_0/GMII sys_ps7/GMII_ETHERNET_0 +ad_connect mii_to_rmii_0/ref_clk ref_clk_50_a + +ad_connect mii_to_rmii_0/RMII_PHY_M RMII_PHY_M_0 + +ad_ip_instance mii_to_rmii mii_to_rmii_1 +ad_ip_parameter mii_to_rmii_1 CONFIG.C_MODE 1 +ad_ip_parameter mii_to_rmii_1 CONFIG.C_SPEED_100 1 +ad_ip_parameter mii_to_rmii_1 CONFIG.C_FIXED_SPEED 0 + +ad_connect mii_to_rmii_1/GMII sys_ps7/GMII_ETHERNET_1 +ad_connect mii_to_rmii_1/ref_clk ref_clk_50_b + +ad_connect mii_to_rmii_1/RMII_PHY_M RMII_PHY_M_1 + +ad_ip_instance proc_sys_reset proc_sys_reset_eth0 +ad_connect proc_sys_reset_eth0/slowest_sync_clk ref_clk_50_a +ad_connect proc_sys_reset_eth0/ext_reset_in sys_rstgen/peripheral_aresetn +ad_connect proc_sys_reset_eth0/peripheral_reset reset_a +ad_connect proc_sys_reset_eth0/peripheral_aresetn mii_to_rmii_0/rst_n + +ad_ip_instance proc_sys_reset proc_sys_reset_eth1 +ad_connect proc_sys_reset_eth1/slowest_sync_clk ref_clk_50_b +ad_connect proc_sys_reset_eth1/ext_reset_in sys_rstgen/peripheral_aresetn +ad_connect proc_sys_reset_eth1/peripheral_reset reset_b +ad_connect proc_sys_reset_eth1/peripheral_aresetn mii_to_rmii_1/rst_n + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 +set sys_cstring "sys rom custom string placeholder" +sysid_gen_sys_init_file $sys_cstring + diff --git a/projects/cn0506_rmii/zed/system_constr.xdc b/projects/cn0506_rmii/zed/system_constr.xdc new file mode 100644 index 000000000..3684cd751 --- /dev/null +++ b/projects/cn0506_rmii/zed/system_constr.xdc @@ -0,0 +1,48 @@ + +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports rmii_rx_ref_clk_a] ; ## D08 FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports rmii_rx_er_a] ; ## D09 FMC_LPC_LA01_CC_N +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25 PULLUP true} [get_ports rmii_rx_dv_a] ; ## H14 FMC_LPC_LA07_N +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 PULLUP true} [get_ports mac_if_sel_0_a] ; ## G06 FMC_HPC1_LA00_CC_P +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports {rmii_rxd_a[0]}] ; ## H07 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports {rmii_rxd_a[1]}] ; ## H08 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports rmii_tx_en_a] ; ## H13 FMC_LPC_LA07_P +set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {rmii_txd_a[0]}] ; ## D14 FMC_LPC_LA09_P +set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {rmii_txd_a[1]}] ; ## D15 FMC_LPC_LA09_N + +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25 PULLUP true} [get_ports mdio_fmc_a] ; ## H16 FMC_LPC_LA11_P +set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports mdc_fmc_a] ; ## H17 FMC_LPC_LA11_N + +set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports reset_a] ; ## H19 FMC_LPC_LA15_P +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports link_st_a] ; ## H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports led_0_a] ; ## G12 FMC_LPC_LA08_P +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports led_ar_c_c2m] ; ## G15 FMC_LPC_LA12_P +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports led_ar_a_c2m] ; ## G16 FMC_LPC_LA12_N +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports led_al_c_c2m] ; ## D17 FMC_LPC_LA13_P +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports led_al_a_c2m] ; ## D18 FMC_LPC_LA13_N + +set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports rmii_rx_ref_clk_b] ; ## D20 FMC_LPC_LA17_CC_P +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports rmii_rx_er_b] ; ## D21 FMC_LPC_LA17_CC_N +set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS25 PULLUP true} [get_ports rmii_rx_dv_b] ; ## H29 FMC_HPC1_LA24_N +set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25 PULLUP true} [get_ports mac_if_sel_0_b] ; ## C22 FMC_HPC1_LA18_CC_P +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports {rmii_rxd_b[0]}] ; ## H22 FMC_LPC_LA19_P +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS25} [get_ports {rmii_rxd_b[1]}] ; ## H23 FMC_LPC_LA19_N +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports rmii_tx_en_b] ; ## H28 FMC_LPC_LA24_P +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {rmii_txd_b[0]}] ; ## H25 FMC_LPC_LA21_P +set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {rmii_txd_b[1]}] ; ## H26 FMC_LPC_LA21_N + +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25 PULLUP true} [get_ports mdio_fmc_b] ; ## H31 FMC_LPC_LA28_P +set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS25} [get_ports mdc_fmc_b] ; ## H32 FMC_LPC_LA28_N + +set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS25} [get_ports reset_b] ; ## H20 FMC_LPC_LA15_N +set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports link_st_b] ; ## G27 FMC_LPC_LA25_P +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports led_0_b] ; ## D23 FMC_LPC_LA23_P +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports led_bl_c_c2m] ; ## D26 FMC_LPC_LA26_P +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports led_bl_a_c2m] ; ## D27 FMC_LPC_LA26_N +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports led_br_c_c2m] ; ## G18 FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports led_br_a_c2m] ; ## G19 FMC_LPC_LA16_N + +create_clock -name rmii_rx_clk_0 -period 20 [get_pins i_system_wrapper/system_i/mii_to_rmii_0/U0/rmii2mac_rx_clk_bi_reg/Q] +create_clock -name rmii_rx_clk_1 -period 20 [get_pins i_system_wrapper/system_i/mii_to_rmii_1/U0/rmii2mac_rx_clk_bi_reg/Q] +create_clock -name rmii_tx_clk_0 -period 20 [get_pins i_system_wrapper/system_i/mii_to_rmii_0/U0/rmii2mac_tx_clk_bi_reg/Q] +create_clock -name rmii_tx_clk_1 -period 20 [get_pins i_system_wrapper/system_i/mii_to_rmii_1/U0/rmii2mac_tx_clk_bi_reg/Q] + diff --git a/projects/cn0506_rmii/zed/system_project.tcl b/projects/cn0506_rmii/zed/system_project.tcl new file mode 100644 index 000000000..194eb83f2 --- /dev/null +++ b/projects/cn0506_rmii/zed/system_project.tcl @@ -0,0 +1,14 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project cn0506_rmii_zed +adi_project_files cn0506_rmii_zed [list \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] + +adi_project_run cn0506_rmii_zed + diff --git a/projects/cn0506_rmii/zed/system_top.v b/projects/cn0506_rmii/zed/system_top.v new file mode 100644 index 000000000..34eb0ff82 --- /dev/null +++ b/projects/cn0506_rmii/zed/system_top.v @@ -0,0 +1,286 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + output spdif, + + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + // mii interface + + output reset_a, + output mdc_fmc_a, + inout mdio_fmc_a, + input rmii_rx_ref_clk_a, + input [ 1:0] rmii_rxd_a, + input rmii_rx_dv_a, + input rmii_rx_er_a, + output [ 1:0] rmii_txd_a, + output rmii_tx_en_a, + input link_st_a, + input led_0_a, + output mac_if_sel_0_a, + + output reset_b, + output mdc_fmc_b, + inout mdio_fmc_b, + input rmii_rx_ref_clk_b, + input [ 1:0] rmii_rxd_b, + input rmii_rx_dv_b, + input rmii_rx_er_b, + output [ 1:0] rmii_txd_b, + output rmii_tx_en_b, + input link_st_b, + input led_0_b, + output mac_if_sel_0_b, + + // LEDs + + output led_ar_c_c2m, + output led_ar_a_c2m, + output led_al_c_c2m, + output led_al_a_c2m, + + output led_br_c_c2m, + output led_br_a_c2m, + output led_bl_c_c2m, + output led_bl_a_c2m +); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + wire sys_reset_a; + wire sys_reset_b; + wire gpio_reset_a; + wire gpio_reset_b; + + // assignments + + assign mac_if_sel_0_a = 1'b1; + assign mac_if_sel_0_b = 1'b1; + + // port a - right led (activity/status) yellow only + + assign led_ar_c_c2m = led_0_a; + assign led_ar_a_c2m = 1'b0; + + // port a - left led (speed mode) hard-coded to 100M=yellow no feedback from mac + + assign led_al_c_c2m = 1'b1; + assign led_al_a_c2m = 1'b0; + + // port b - right led (activity/status) yellow only + + assign led_br_c_c2m = led_0_b; + assign led_br_a_c2m = 1'b0; + + // port b - left led (speed mode) hard-coded to 100M=yellow no feedback from mac + + assign led_bl_c_c2m = 1'b1; + assign led_bl_a_c2m = 1'b0; + + assign gpio_i[63:36] = gpio_o[63:36]; + assign gpio_i[33:32] = gpio_o[33:32]; + + assign gpio_reset_a = gpio_o[37]; + assign gpio_reset_b = gpio_o[36]; + + assign reset_a = sys_reset_a | gpio_reset_a; + assign reset_b = sys_reset_b | gpio_reset_b; + + assign gpio_i[35] = link_st_a; + assign gpio_i[34] = link_st_b; + + // instantiations + + ad_iobuf #(.DATA_WIDTH(32)) i_iobuf_bd ( + .dio_t (gpio_t[31:0]), + .dio_i (gpio_o[31:0]), + .dio_o (gpio_i[31:0]), + .dio_p (gpio_bd)); + + ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_scl ( + .dio_t ({iic_mux_scl_t_s,iic_mux_scl_t_s}), + .dio_i (iic_mux_scl_o_s), + .dio_o (iic_mux_scl_i_s), + .dio_p (iic_mux_scl)); + + ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_sda ( + .dio_t ({iic_mux_sda_t_s,iic_mux_sda_t_s}), + .dio_i (iic_mux_sda_o_s), + .dio_o (iic_mux_sda_i_s), + .dio_p (iic_mux_sda)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif), + .spi0_clk_i (1'b0), + .spi0_clk_o (), + .spi0_csn_0_o (), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (1'b0), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .reset_a (sys_reset_a), + .reset_b (sys_reset_b), + .ref_clk_50_a (rmii_rx_ref_clk_a), + .ref_clk_50_b (rmii_rx_ref_clk_b), + .MDIO_ETHERNET_0_0_mdc(mdc_fmc_a), + .MDIO_ETHERNET_0_0_mdio_io(mdio_fmc_a), + .RMII_PHY_M_0_crs_dv (rmii_rx_dv_a), + .RMII_PHY_M_0_rx_er (rmii_rx_er_a), + .RMII_PHY_M_0_rxd (rmii_rxd_a), + .RMII_PHY_M_0_tx_en (rmii_tx_en_a), + .RMII_PHY_M_0_txd (rmii_txd_a), + .MDIO_ETHERNET_1_0_mdc(mdc_fmc_b), + .MDIO_ETHERNET_1_0_mdio_io(mdio_fmc_b), + .RMII_PHY_M_1_crs_dv (rmii_rx_dv_b), + .RMII_PHY_M_1_rx_er (rmii_rx_er_b), + .RMII_PHY_M_1_rxd (rmii_rxd_b), + .RMII_PHY_M_1_tx_en (rmii_tx_en_b), + .RMII_PHY_M_1_txd (rmii_txd_b) + ); + +endmodule + +// *************************************************************************** +// ***************************************************************************