From 3211964c2e0b7c43c8594f5b45b5d28eada853d8 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 10 Nov 2014 13:41:01 -0500 Subject: [PATCH] ad6676evb: added --- projects/ad6676evb/common/ad6676evb_bd.tcl | 339 ++++++++++++++++++++ projects/ad6676evb/vc707/system_bd.tcl | 4 + projects/ad6676evb/vc707/system_constr.xdc | 40 +++ projects/ad6676evb/vc707/system_project.tcl | 15 + projects/ad6676evb/vc707/system_top.v | 309 ++++++++++++++++++ projects/ad6676evb/zc706/system_bd.tcl | 5 + projects/ad6676evb/zc706/system_constr.xdc | 35 ++ projects/ad6676evb/zc706/system_project.tcl | 19 ++ projects/ad6676evb/zc706/system_top.v | 332 +++++++++++++++++++ 9 files changed, 1098 insertions(+) create mode 100644 projects/ad6676evb/common/ad6676evb_bd.tcl create mode 100644 projects/ad6676evb/vc707/system_bd.tcl create mode 100644 projects/ad6676evb/vc707/system_constr.xdc create mode 100644 projects/ad6676evb/vc707/system_project.tcl create mode 100644 projects/ad6676evb/vc707/system_top.v create mode 100644 projects/ad6676evb/zc706/system_bd.tcl create mode 100644 projects/ad6676evb/zc706/system_constr.xdc create mode 100644 projects/ad6676evb/zc706/system_project.tcl create mode 100644 projects/ad6676evb/zc706/system_top.v diff --git a/projects/ad6676evb/common/ad6676evb_bd.tcl b/projects/ad6676evb/common/ad6676evb_bd.tcl new file mode 100644 index 000000000..30a5b5cf0 --- /dev/null +++ b/projects/ad6676evb/common/ad6676evb_bd.tcl @@ -0,0 +1,339 @@ + + # ad6676 + +set spi_csn_o [create_bd_port -dir O spi_csn_o] +set spi_csn_i [create_bd_port -dir I spi_csn_i] +set spi_clk_i [create_bd_port -dir I spi_clk_i] +set spi_clk_o [create_bd_port -dir O spi_clk_o] +set spi_sdo_i [create_bd_port -dir I spi_sdo_i] +set spi_sdo_o [create_bd_port -dir O spi_sdo_o] +set spi_sdi_i [create_bd_port -dir I spi_sdi_i] + +set rx_ref_clk [create_bd_port -dir I rx_ref_clk] +set rx_sync [create_bd_port -dir O rx_sync] +set rx_sysref [create_bd_port -dir O rx_sysref] +set rx_data_p [create_bd_port -dir I -from 1 -to 0 rx_data_p] +set rx_data_n [create_bd_port -dir I -from 1 -to 0 rx_data_n] + +set adc_clk [create_bd_port -dir O adc_clk] +set adc_enable_a [create_bd_port -dir O adc_enable_a] +set adc_valid_a [create_bd_port -dir O adc_valid_a] +set adc_data_a [create_bd_port -dir O -from 31 -to 0 adc_data_a] +set adc_enable_b [create_bd_port -dir O adc_enable_b] +set adc_valid_b [create_bd_port -dir O adc_valid_b] +set adc_data_b [create_bd_port -dir O -from 31 -to 0 adc_data_b] +set dma_wr [create_bd_port -dir I dma_wr] +set dma_sync [create_bd_port -dir I dma_sync] +set dma_data [create_bd_port -dir I -from 63 -to 0 dma_data] + +set ad6676_spi_intr [create_bd_port -dir O ad6676_spi_intr] +set ad6676_gpio_intr [create_bd_port -dir O ad6676_gpio_intr] +set ad6676_dma_intr [create_bd_port -dir O ad6676_dma_intr] + +if {$sys_zynq == 0} { + + set gpio_ctl_i [create_bd_port -dir I -from 4 -to 0 gpio_ctl_i] + set gpio_ctl_o [create_bd_port -dir O -from 4 -to 0 gpio_ctl_o] + set gpio_ctl_t [create_bd_port -dir O -from 4 -to 0 gpio_ctl_t] +} + +# adc peripherals + +set axi_ad6676_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad6676:1.0 axi_ad6676_core] + +set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad6676_jesd] +set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad6676_jesd +set_property -dict [list CONFIG.C_LANES {2}] $axi_ad6676_jesd + +set axi_ad6676_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad6676_gt] +set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {2}] $axi_ad6676_gt +set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {2}] $axi_ad6676_gt +set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_ad6676_gt +set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_ad6676_gt +set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {13}] $axi_ad6676_gt +set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {13}] $axi_ad6676_gt +set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad6676_gt +set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad6676_gt + +set axi_ad6676_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad6676_dma] +set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad6676_dma +set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad6676_dma +set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad6676_dma +set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad6676_dma +set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad6676_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad6676_dma +set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad6676_dma +set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad6676_dma +set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad6676_dma +set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad6676_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad6676_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad6676_dma + +if {$sys_zynq == 1} { + + set axi_ad6676_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad6676_gt_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad6676_gt_interconnect + + set axi_ad6676_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad6676_dma_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad6676_dma_interconnect +} + +# gpio and spi + +if {$sys_zynq == 0} { + + set axi_ad6676_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_ad6676_spi] + set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_ad6676_spi + set_property -dict [list CONFIG.C_NUM_SS_BITS {1}] $axi_ad6676_spi + set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_ad6676_spi + + set axi_ad6676_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_ad6676_gpio] + set_property -dict [list CONFIG.C_GPIO_WIDTH {10}] $axi_ad6676_gpio + set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_ad6676_gpio +} + +# additions to default configuration + +if {$sys_zynq == 1} { + + set_property -dict [list CONFIG.NUM_MI {11}] $axi_cpu_interconnect + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 + set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {42}] $sys_ps7 + set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 + + set_property LEFT 41 [get_bd_ports GPIO_I] + set_property LEFT 41 [get_bd_ports GPIO_O] + set_property LEFT 41 [get_bd_ports GPIO_T] + +} else { + + set_property -dict [list CONFIG.NUM_MI {13}] $axi_cpu_interconnect + set_property -dict [list CONFIG.NUM_SI {10}] $axi_mem_interconnect + set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc +} + +# connections (spi and gpio) + +if {$sys_zynq == 1} { + + connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I] + connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_ps7/SPI0_SS_O] + connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I] + connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O] + connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I] + connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O] + connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I] + +} else { + + connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_ad6676_spi/ss_i] + connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_ad6676_spi/ss_o] + connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_ad6676_spi/sck_i] + connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_ad6676_spi/sck_o] + connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_ad6676_spi/io0_i] + connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_ad6676_spi/io0_o] + connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_ad6676_spi/io1_i] +} + +if {$sys_zynq == 0} { + + connect_bd_net -net gpio_ctl_i [get_bd_ports gpio_ctl_i] [get_bd_pins axi_ad6676_gpio/gpio_io_i] + connect_bd_net -net gpio_ctl_o [get_bd_ports gpio_ctl_o] [get_bd_pins axi_ad6676_gpio/gpio_io_o] + connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_ad6676_gpio/gpio_io_t] +} + +# connections (gt) + +connect_bd_net -net axi_ad6676_gt_ref_clk_c [get_bd_pins axi_ad6676_gt/ref_clk_c] [get_bd_ports rx_ref_clk] +connect_bd_net -net axi_ad6676_gt_rx_data_p [get_bd_pins axi_ad6676_gt/rx_data_p] [get_bd_ports rx_data_p] +connect_bd_net -net axi_ad6676_gt_rx_data_n [get_bd_pins axi_ad6676_gt/rx_data_n] [get_bd_ports rx_data_n] +connect_bd_net -net axi_ad6676_gt_rx_sync [get_bd_pins axi_ad6676_gt/rx_sync] [get_bd_ports rx_sync] +connect_bd_net -net axi_ad6676_gt_rx_sysref [get_bd_pins axi_ad6676_gt/rx_sysref] [get_bd_ports rx_sysref] + +# connections (adc) + +connect_bd_net -net axi_ad6676_gt_rx_clk [get_bd_pins axi_ad6676_gt/rx_clk_g] +connect_bd_net -net axi_ad6676_gt_rx_clk [get_bd_pins axi_ad6676_gt/rx_clk] +connect_bd_net -net axi_ad6676_gt_rx_clk [get_bd_pins axi_ad6676_core/rx_clk] +connect_bd_net -net axi_ad6676_gt_rx_clk [get_bd_pins axi_ad6676_jesd/rx_core_clk] +connect_bd_net -net axi_ad6676_gt_rx_clk [get_bd_ports adc_clk] +connect_bd_net -net axi_ad6676_gt_rx_rst [get_bd_pins axi_ad6676_gt/rx_rst] +connect_bd_net -net axi_ad6676_gt_rx_rst [get_bd_pins axi_ad6676_jesd/rx_reset] + +connect_bd_net -net axi_ad6676_gt_rx_sysref [get_bd_pins axi_ad6676_jesd/rx_sysref] +connect_bd_net -net axi_ad6676_gt_rx_gt_charisk [get_bd_pins axi_ad6676_gt/rx_gt_charisk] [get_bd_pins axi_ad6676_jesd/gt_rxcharisk_in] +connect_bd_net -net axi_ad6676_gt_rx_gt_disperr [get_bd_pins axi_ad6676_gt/rx_gt_disperr] [get_bd_pins axi_ad6676_jesd/gt_rxdisperr_in] +connect_bd_net -net axi_ad6676_gt_rx_gt_notintable [get_bd_pins axi_ad6676_gt/rx_gt_notintable] [get_bd_pins axi_ad6676_jesd/gt_rxnotintable_in] +connect_bd_net -net axi_ad6676_gt_rx_gt_data [get_bd_pins axi_ad6676_gt/rx_gt_data] [get_bd_pins axi_ad6676_jesd/gt_rxdata_in] +connect_bd_net -net axi_ad6676_gt_rx_rst_done [get_bd_pins axi_ad6676_gt/rx_rst_done] [get_bd_pins axi_ad6676_jesd/rx_reset_done] +connect_bd_net -net axi_ad6676_gt_rx_ip_comma_align [get_bd_pins axi_ad6676_gt/rx_ip_comma_align] [get_bd_pins axi_ad6676_jesd/rxencommaalign_out] +connect_bd_net -net axi_ad6676_gt_rx_ip_sync [get_bd_pins axi_ad6676_gt/rx_ip_sync] [get_bd_pins axi_ad6676_jesd/rx_sync] +connect_bd_net -net axi_ad6676_gt_rx_ip_sof [get_bd_pins axi_ad6676_gt/rx_ip_sof] [get_bd_pins axi_ad6676_jesd/rx_start_of_frame] +connect_bd_net -net axi_ad6676_gt_rx_ip_data [get_bd_pins axi_ad6676_gt/rx_ip_data] [get_bd_pins axi_ad6676_jesd/rx_tdata] +connect_bd_net -net axi_ad6676_gt_rx_data [get_bd_pins axi_ad6676_gt/rx_data] [get_bd_pins axi_ad6676_core/rx_data] +connect_bd_net -net axi_ad6676_adc_clk [get_bd_pins axi_ad6676_core/adc_clk] [get_bd_pins axi_ad6676_dma/fifo_wr_clk] +connect_bd_net -net axi_ad6676_adc_enable_a [get_bd_pins axi_ad6676_core/adc_enable_a] [get_bd_ports adc_enable_a] +connect_bd_net -net axi_ad6676_adc_valid_a [get_bd_pins axi_ad6676_core/adc_valid_a] [get_bd_ports adc_valid_a] +connect_bd_net -net axi_ad6676_adc_data_a [get_bd_pins axi_ad6676_core/adc_data_a] [get_bd_ports adc_data_a] +connect_bd_net -net axi_ad6676_adc_enable_b [get_bd_pins axi_ad6676_core/adc_enable_b] [get_bd_ports adc_enable_b] +connect_bd_net -net axi_ad6676_adc_valid_b [get_bd_pins axi_ad6676_core/adc_valid_b] [get_bd_ports adc_valid_b] +connect_bd_net -net axi_ad6676_adc_data_b [get_bd_pins axi_ad6676_core/adc_data_b] [get_bd_ports adc_data_b] +connect_bd_net -net axi_ad6676_dma_wr [get_bd_pins axi_ad6676_dma/fifo_wr_en] [get_bd_ports dma_wr] +connect_bd_net -net axi_ad6676_dma_sync [get_bd_pins axi_ad6676_dma/fifo_wr_sync] [get_bd_ports dma_sync] +connect_bd_net -net axi_ad6676_dma_data [get_bd_pins axi_ad6676_dma/fifo_wr_din] [get_bd_ports dma_data] +connect_bd_net -net axi_ad6676_adc_dovf [get_bd_pins axi_ad6676_core/adc_dovf] [get_bd_pins axi_ad6676_dma/fifo_wr_overflow] +connect_bd_net -net axi_ad6676_dma_intr [get_bd_pins axi_ad6676_dma/irq] [get_bd_ports ad6676_dma_intr] + +# interconnect (cpu) + +connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad6676_dma/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad6676_core/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad6676_jesd/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad6676_gt/s_axi] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_gt/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_core/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_jesd/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_dma/s_axi_aclk] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_gt/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_core/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_jesd/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_dma/s_axi_aresetn] + +if {$sys_zynq == 0} { + + connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad6676_spi/axi_lite] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad6676_gpio/s_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_spi/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_spi/ext_spi_clk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_gpio/s_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_spi/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_gpio/s_axi_aresetn] + + connect_bd_net -net axi_ad6676_spi_intr [get_bd_pins axi_ad6676_spi/ip2intc_irpt] [get_bd_pins ad6676_spi_intr] + connect_bd_net -net axi_ad6676_gpio_intr [get_bd_pins axi_ad6676_gpio/ip2intc_irpt] [get_bd_pins ad6676_gpio_intr] +} + +# gt uses hp3, and 100MHz clock for both DRP and AXI4 + +if {$sys_zynq == 0} { + + connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_ad6676_gt/m_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_gt/m_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_gt/drp_clk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_gt/m_axi_aresetn] + +} else { + + connect_bd_intf_net -intf_net axi_ad6676_gt_interconnect_m00_axi [get_bd_intf_pins axi_ad6676_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3] + connect_bd_intf_net -intf_net axi_ad6676_gt_interconnect_s00_axi [get_bd_intf_pins axi_ad6676_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_ad6676_gt/m_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_gt_interconnect/ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_gt_interconnect/M00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_gt_interconnect/S00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_gt/m_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_gt/drp_clk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_gt_interconnect/ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_gt/m_axi_aresetn] +} + +# memory interconnects share the same clock (fclk2) + +if {$sys_zynq == 1} { + + set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2] + set sys_fmc_dma_resetn_source [get_bd_pins sys_ps7/FCLK_RESET2_N] + + connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source +} + +# interconnect (mem/dac) + +if {$sys_zynq == 0} { + + connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad6676_dma/m_dest_axi] + connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source + connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad6676_dma/m_dest_axi_aclk] + connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_200m_resetn_source + connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad6676_dma/m_dest_axi_aresetn] + +} else { + + connect_bd_intf_net -intf_net axi_ad6676_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad6676_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] + connect_bd_intf_net -intf_net axi_ad6676_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad6676_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad6676_dma/m_dest_axi] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad6676_dma_interconnect/ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad6676_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad6676_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad6676_dma/m_dest_axi_aclk] + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad6676_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad6676_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad6676_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad6676_dma/m_dest_axi_aresetn] +} + +# ila + +set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon] +set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon +set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_jesd_rx_mon +set_property -dict [list CONFIG.C_PROBE0_WIDTH {170}] $ila_jesd_rx_mon +set_property -dict [list CONFIG.C_PROBE1_WIDTH {4}] $ila_jesd_rx_mon +set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_jesd_rx_mon +set_property -dict [list CONFIG.C_PROBE3_WIDTH {32}] $ila_jesd_rx_mon +set_property -dict [list CONFIG.C_PROBE4_WIDTH {32}] $ila_jesd_rx_mon + +connect_bd_net -net axi_ad6676_gt_rx_mon_data [get_bd_pins axi_ad6676_gt/rx_mon_data] +connect_bd_net -net axi_ad6676_gt_rx_mon_trigger [get_bd_pins axi_ad6676_gt/rx_mon_trigger] +connect_bd_net -net axi_ad6676_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK] +connect_bd_net -net axi_ad6676_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0] +connect_bd_net -net axi_ad6676_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1] +connect_bd_net -net axi_ad6676_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2] +connect_bd_net -net axi_ad6676_adc_data_a [get_bd_pins ila_jesd_rx_mon/PROBE3] +connect_bd_net -net axi_ad6676_adc_data_b [get_bd_pins ila_jesd_rx_mon/PROBE4] + +# address map + +create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad6676_core/s_axi/axi_lite] SEG_data_ad6676_core +create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad6676_dma/s_axi/axi_lite] SEG_data_ad6676_dma +create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad6676_jesd/s_axi/Reg] SEG_data_ad6676_jesd +create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad6676_gt/s_axi/axi_lite] SEG_data_ad6676_gt + +if {$sys_zynq == 0} { + + create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad6676_spi/axi_lite/Reg] SEG_data_ad6676_spi + create_bd_addr_seg -range 0x00010000 -offset 0x40000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad6676_gpio/S_AXI/Reg] SEG_data_ad6676_gpio +} + +if {$sys_zynq == 0} { + + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad6676_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad6676_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl + +} else { + + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad6676_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad6676_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm +} + diff --git a/projects/ad6676evb/vc707/system_bd.tcl b/projects/ad6676evb/vc707/system_bd.tcl new file mode 100644 index 000000000..039a24b8a --- /dev/null +++ b/projects/ad6676evb/vc707/system_bd.tcl @@ -0,0 +1,4 @@ + +source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl +source ../common/ad6676evb_bd.tcl + diff --git a/projects/ad6676evb/vc707/system_constr.xdc b/projects/ad6676evb/vc707/system_constr.xdc new file mode 100644 index 000000000..f76c6a295 --- /dev/null +++ b/projects/ad6676evb/vc707/system_constr.xdc @@ -0,0 +1,40 @@ + +# ad6676 + +set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVDS} [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P +set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVDS} [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N +set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVDS} [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN D7 IOSTANDARD LVDS} [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVDS} [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN C5 IOSTANDARD LVDS} [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN J40 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P +set_property -dict {PACKAGE_PIN J41 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N +set_property -dict {PACKAGE_PIN K39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G06 FMC_HPC_LA00_CC_P +set_property -dict {PACKAGE_PIN K40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G07 FMC_HPC_LA00_CC_N + +set_property -dict {PACKAGE_PIN L41 IOSTANDARD LVCMOS18} [get_ports spi_csn] ; ## D12 FMC_HPC_LA05_N +set_property -dict {PACKAGE_PIN H41 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## H11 FMC_HPC_LA04_N +set_property -dict {PACKAGE_PIN H40 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN M41 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## D11 FMC_HPC_LA05_P + +set_property -dict {PACKAGE_PIN K42 IOSTANDARD LVCMOS18} [get_ports adc_resetb] ; ## C10 FMC_HPC_LA06_P +set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVCMOS18} [get_ports adc_agc1] ; ## H07 FMC_HPC_LA02_P +set_property -dict {PACKAGE_PIN N41 IOSTANDARD LVCMOS18} [get_ports adc_agc2] ; ## H08 FMC_HPC_LA02_N +set_property -dict {PACKAGE_PIN M42 IOSTANDARD LVCMOS18} [get_ports adc_agc3] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_agc4] ; ## G10 FMC_HPC_LA03_N + +# clocks + +create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p] +create_clock -name rx_div_clk -period 6.60 [get_nets i_system_wrapper/system_i/axi_ad6676_gt_rx_clk] +create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] + +set_clock_groups -asynchronous -group {rx_div_clk} +set_clock_groups -asynchronous -group {fmc_dma_clk} + +set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE] diff --git a/projects/ad6676evb/vc707/system_project.tcl b/projects/ad6676evb/vc707/system_project.tcl new file mode 100644 index 000000000..3d24a9535 --- /dev/null +++ b/projects/ad6676evb/vc707/system_project.tcl @@ -0,0 +1,15 @@ + + + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl + +adi_project_create ad6676evb_vc707 +adi_project_files ad6676evb_vc707 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ] + +adi_project_run ad6676evb_vc707 + + diff --git a/projects/ad6676evb/vc707/system_top.v b/projects/ad6676evb/vc707/system_top.v new file mode 100644 index 000000000..b1bec65f7 --- /dev/null +++ b/projects/ad6676evb/vc707/system_top.v @@ -0,0 +1,309 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + sys_rst, + sys_clk_p, + sys_clk_n, + + uart_sin, + uart_sout, + + ddr3_addr, + ddr3_ba, + ddr3_cas_n, + ddr3_ck_n, + ddr3_ck_p, + ddr3_cke, + ddr3_cs_n, + ddr3_dm, + ddr3_dq, + ddr3_dqs_n, + ddr3_dqs_p, + ddr3_odt, + ddr3_ras_n, + ddr3_reset_n, + ddr3_we_n, + + sgmii_rxp, + sgmii_rxn, + sgmii_txp, + sgmii_txn, + + phy_rstn, + mgt_clk_p, + mgt_clk_n, + mdio_mdc, + mdio_mdio, + + fan_pwm, + + gpio_lcd, + gpio_led, + gpio_sw, + + iic_rstn, + iic_scl, + iic_sda, + + hdmi_out_clk, + hdmi_hsync, + hdmi_vsync, + hdmi_data_e, + hdmi_data, + + spdif, + + rx_ref_clk_p, + rx_ref_clk_n, + rx_sysref_p, + rx_sysref_n, + rx_sync_p, + rx_sync_n, + rx_data_p, + rx_data_n, + + adc_resetb, + adc_agc1, + adc_agc2, + adc_agc3, + adc_agc4, + + spi_csn, + spi_clk, + spi_mosi, + spi_miso); + + input sys_rst; + input sys_clk_p; + input sys_clk_n; + + input uart_sin; + output uart_sout; + + output [13:0] ddr3_addr; + output [ 2:0] ddr3_ba; + output ddr3_cas_n; + output [ 0:0] ddr3_ck_n; + output [ 0:0] ddr3_ck_p; + output [ 0:0] ddr3_cke; + output [ 0:0] ddr3_cs_n; + output [ 7:0] ddr3_dm; + inout [63:0] ddr3_dq; + inout [ 7:0] ddr3_dqs_n; + inout [ 7:0] ddr3_dqs_p; + output [ 0:0] ddr3_odt; + output ddr3_ras_n; + output ddr3_reset_n; + output ddr3_we_n; + + input sgmii_rxp; + input sgmii_rxn; + output sgmii_txp; + output sgmii_txn; + + output phy_rstn; + input mgt_clk_p; + input mgt_clk_n; + output mdio_mdc; + inout mdio_mdio; + + output fan_pwm; + + output [ 6:0] gpio_lcd; + output [ 7:0] gpio_led; + input [12:0] gpio_sw; + + output iic_rstn; + inout iic_scl; + inout iic_sda; + + output hdmi_out_clk; + output hdmi_hsync; + output hdmi_vsync; + output hdmi_data_e; + output [35:0] hdmi_data; + + output spdif; + + input rx_ref_clk_p; + input rx_ref_clk_n; + output rx_sysref_p; + output rx_sysref_n; + output rx_sync_p; + output rx_sync_n; + input [ 1:0] rx_data_p; + input [ 1:0] rx_data_n; + + inout adc_resetb; + inout adc_agc1; + inout adc_agc2; + inout adc_agc3; + inout adc_agc4; + + output spi_csn; + output spi_clk; + output spi_mosi; + input spi_miso; + + // internal signals + + wire [4:0] gpio_i; + wire [4:0] gpio_o; + wire [4:0] gpio_t; + + wire rx_ref_clk; + wire rx_sysref; + wire rx_sync; + + // instantiations + + IBUFDS_GTE2 i_ibufds_rx_ref_clk ( + .CEB (1'd0), + .I (rx_ref_clk_p), + .IB (rx_ref_clk_n), + .O (rx_ref_clk), + .ODIV2 ()); + + OBUFDS i_obufds_rx_sysref ( + .I (rx_sysref), + .O (rx_sysref_p), + .OB (rx_sysref_n)); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + IOBUF i_iobuf_gpio_adc_resetb ( + .I (gpio_o[4]), + .O (gpio_i[4]), + .T (gpio_t[4]), + .IO (adc_resetb)); + + IOBUF i_iobuf_gpio_adc_agc1 ( + .I (gpio_o[3]), + .O (gpio_i[3]), + .T (gpio_t[3]), + .IO (adc_agc1)); + + IOBUF i_iobuf_gpio_adc_agc2 ( + .I (gpio_o[2]), + .O (gpio_i[2]), + .T (gpio_t[2]), + .IO (adc_agc2)); + + IOBUF i_iobuf_gpio_adc_agc3 ( + .I (gpio_o[1]), + .O (gpio_i[1]), + .T (gpio_t[1]), + .IO (adc_agc3)); + + IOBUF i_iobuf_gpio_adc_agc4 ( + .I (gpio_o[0]), + .O (gpio_i[0]), + .T (gpio_t[0]), + .IO (adc_agc4)); + + system_wrapper i_system_wrapper ( + .ddr3_addr (ddr3_addr), + .ddr3_ba (ddr3_ba), + .ddr3_cas_n (ddr3_cas_n), + .ddr3_ck_n (ddr3_ck_n), + .ddr3_ck_p (ddr3_ck_p), + .ddr3_cke (ddr3_cke), + .ddr3_cs_n (ddr3_cs_n), + .ddr3_dm (ddr3_dm), + .ddr3_dq (ddr3_dq), + .ddr3_dqs_n (ddr3_dqs_n), + .ddr3_dqs_p (ddr3_dqs_p), + .ddr3_odt (ddr3_odt), + .ddr3_ras_n (ddr3_ras_n), + .ddr3_reset_n (ddr3_reset_n), + .ddr3_we_n (ddr3_we_n), + .fan_pwm (fan_pwm), + .gpio_lcd_tri_o (gpio_lcd), + .gpio_led_tri_o (gpio_led), + .gpio_sw_tri_i (gpio_sw), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .iic_rstn (iic_rstn), + .mdio_mdc (mdio_mdc), + .mdio_mdio_io (mdio_mdio), + .mgt_clk_clk_n (mgt_clk_n), + .mgt_clk_clk_p (mgt_clk_p), + .phy_rstn (phy_rstn), + .sgmii_rxn (sgmii_rxn), + .sgmii_rxp (sgmii_rxp), + .sgmii_txn (sgmii_txn), + .sgmii_txp (sgmii_txp), + .spdif (spdif), + .sys_clk_n (sys_clk_n), + .sys_clk_p (sys_clk_p), + .sys_rst (sys_rst), + .uart_sin (uart_sin), + .uart_sout (uart_sout), + .gpio_ctl_i (gpio_i), + .gpio_ctl_o (gpio_o), + .gpio_ctl_t (gpio_t), + .rx_data_n (rx_data_n), + .rx_data_p (rx_data_p), + .rx_ref_clk (rx_ref_clk), + .rx_sync (rx_sync), + .rx_sysref (rx_sysref), + .spi_clk_i (1'b0), + .spi_clk_o (spi_clk), + .spi_csn_i (1'b1), + .spi_csn_o (spi_csn), + .spi_sdi_i (spi_miso), + .spi_sdo_i (1'b0), + .spi_sdo_o (spi_mosi)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/ad6676evb/zc706/system_bd.tcl b/projects/ad6676evb/zc706/system_bd.tcl new file mode 100644 index 000000000..a3066b0d4 --- /dev/null +++ b/projects/ad6676evb/zc706/system_bd.tcl @@ -0,0 +1,5 @@ + +source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl +source ../common/ad6676evb_bd.tcl + + diff --git a/projects/ad6676evb/zc706/system_constr.xdc b/projects/ad6676evb/zc706/system_constr.xdc new file mode 100644 index 000000000..87d4552bd --- /dev/null +++ b/projects/ad6676evb/zc706/system_constr.xdc @@ -0,0 +1,35 @@ + +# ad6676 + +set_property -dict {PACKAGE_PIN AD10} [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P +set_property -dict {PACKAGE_PIN AD9 } [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N +set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N +set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N +set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G06 FMC_HPC_LA00_CC_P +set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G07 FMC_HPC_LA00_CC_N + +set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## D12 FMC_HPC_LA05_N +set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H11 FMC_HPC_LA04_N +set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## D11 FMC_HPC_LA05_P + +set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports adc_oen] ; ## C11 FMC_HPC_LA06_N +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports adc_sela] ; ## G12 FMC_HPC_LA08_P +set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports adc_selb] ; ## G13 FMC_HPC_LA08_N +set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports adc_s0] ; ## H13 FMC_HPC_LA07_P +set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports adc_s1] ; ## H14 FMC_HPC_LA07_N +set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports adc_resetb] ; ## C10 FMC_HPC_LA06_P +set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports adc_agc1] ; ## H07 FMC_HPC_LA02_P +set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS25} [get_ports adc_agc2] ; ## H08 FMC_HPC_LA02_N +set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports adc_agc3] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_agc4] ; ## G10 FMC_HPC_LA03_N + +# clocks + +create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p] +create_clock -name rx_div_clk -period 6.60 [get_nets i_system_wrapper/system_i/axi_ad6676_gt_rx_clk] + diff --git a/projects/ad6676evb/zc706/system_project.tcl b/projects/ad6676evb/zc706/system_project.tcl new file mode 100644 index 000000000..3a1fee051 --- /dev/null +++ b/projects/ad6676evb/zc706/system_project.tcl @@ -0,0 +1,19 @@ + + + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl + +adi_project_create ad6676evb_zc706 +adi_project_files ad6676evb_zc706 [list \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] + +set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc] +set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] + +adi_project_run ad6676evb_zc706 + + diff --git a/projects/ad6676evb/zc706/system_top.v b/projects/ad6676evb/zc706/system_top.v new file mode 100644 index 000000000..a7a1e04a8 --- /dev/null +++ b/projects/ad6676evb/zc706/system_top.v @@ -0,0 +1,332 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + spdif, + + iic_scl, + iic_sda, + + rx_ref_clk_p, + rx_ref_clk_n, + rx_sysref_p, + rx_sysref_n, + rx_sync_p, + rx_sync_n, + rx_data_p, + rx_data_n, + + adc_oen, + adc_sela, + adc_selb, + adc_s0, + adc_s1, + adc_resetb, + adc_agc1, + adc_agc2, + adc_agc3, + adc_agc4, + + spi_csn, + spi_clk, + spi_mosi, + spi_miso); + + inout [14:0] DDR_addr; + inout [ 2:0] DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [ 3:0] DDR_dm; + inout [31:0] DDR_dq; + inout [ 3:0] DDR_dqs_n; + inout [ 3:0] DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0] FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + + inout [14:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [23:0] hdmi_data; + + output spdif; + + inout iic_scl; + inout iic_sda; + + input rx_ref_clk_p; + input rx_ref_clk_n; + output rx_sysref_p; + output rx_sysref_n; + output rx_sync_p; + output rx_sync_n; + input [ 1:0] rx_data_p; + input [ 1:0] rx_data_n; + + inout adc_oen; + inout adc_sela; + inout adc_selb; + inout adc_s0; + inout adc_s1; + inout adc_resetb; + inout adc_agc1; + inout adc_agc2; + inout adc_agc3; + inout adc_agc4; + + output spi_csn; + output spi_clk; + output spi_mosi; + input spi_miso; + + // internal registers + + reg dma_wr = 'd0; + reg [63:0] dma_data = 'd0; + + // internal signals + + wire [41:0] gpio_i; + wire [41:0] gpio_o; + wire [41:0] gpio_t; + wire rx_ref_clk; + wire rx_sysref; + wire rx_sync; + wire adc_clk; + wire adc_enable_a; + wire [31:0] adc_data_a; + wire adc_enable_b; + wire [31:0] adc_data_b; + wire [15:0] ps_intrs; + + // pack & unpack here + + always @(posedge adc_clk) begin + case ({adc_enable_b, adc_enable_a}) + 2'b11: begin + dma_wr <= 1'b1; + dma_data[63:48] <= adc_data_b[31:16]; + dma_data[47:32] <= adc_data_a[31:16]; + dma_data[31:16] <= adc_data_b[15: 0]; + dma_data[15: 0] <= adc_data_a[15: 0]; + end + 2'b10: begin + dma_wr <= ~dma_wr; + dma_data[63:48] <= adc_data_b[31:16]; + dma_data[47:32] <= adc_data_b[15: 0]; + dma_data[31:16] <= dma_data[63:48]; + dma_data[15: 0] <= dma_data[47:32]; + end + 2'b01: begin + dma_wr <= ~dma_wr; + dma_data[63:48] <= adc_data_a[31:16]; + dma_data[47:32] <= adc_data_a[15: 0]; + dma_data[31:16] <= dma_data[63:48]; + dma_data[15: 0] <= dma_data[47:32]; + end + default: begin + dma_wr <= 1'b0; + dma_data[63:48] <= 16'd0; + dma_data[47:32] <= 16'd0; + dma_data[31:16] <= 16'd0; + dma_data[15: 0] <= 16'd0; + end + endcase + end + + // instantiations + + IBUFDS_GTE2 i_ibufds_rx_ref_clk ( + .CEB (1'd0), + .I (rx_ref_clk_p), + .IB (rx_ref_clk_n), + .O (rx_ref_clk), + .ODIV2 ()); + + OBUFDS i_obufds_rx_sysref ( + .I (rx_sysref), + .O (rx_sysref_p), + .OB (rx_sysref_n)); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + ad_iobuf #(.DATA_WIDTH(25)) i_iobuf ( + .dt ({gpio_t[41:32], gpio_t[14:0]}), + .di ({gpio_o[41:32], gpio_o[14:0]}), + .do ({gpio_i[41:32], gpio_i[14:0]}), + .dio ({ adc_oen, + adc_sela, + adc_selb, + adc_s0, + adc_s1, + adc_resetb, + adc_agc1, + adc_agc2, + adc_agc3, + adc_agc4, + gpio_bd})); + + system_wrapper i_system_wrapper ( + .DDR_addr (DDR_addr), + .DDR_ba (DDR_ba), + .DDR_cas_n (DDR_cas_n), + .DDR_ck_n (DDR_ck_n), + .DDR_ck_p (DDR_ck_p), + .DDR_cke (DDR_cke), + .DDR_cs_n (DDR_cs_n), + .DDR_dm (DDR_dm), + .DDR_dq (DDR_dq), + .DDR_dqs_n (DDR_dqs_n), + .DDR_dqs_p (DDR_dqs_p), + .DDR_odt (DDR_odt), + .DDR_ras_n (DDR_ras_n), + .DDR_reset_n (DDR_reset_n), + .DDR_we_n (DDR_we_n), + .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), + .FIXED_IO_mio (FIXED_IO_mio), + .FIXED_IO_ps_clk (FIXED_IO_ps_clk), + .FIXED_IO_ps_porb (FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), + .GPIO_I (gpio_i), + .GPIO_O (gpio_o), + .GPIO_T (gpio_t), + .ad6676_dma_intr (ps_intrs[13]), + .ad6676_gpio_intr (), + .ad6676_spi_intr (), + .adc_clk (adc_clk), + .adc_data_a (adc_data_a), + .adc_data_b (adc_data_b), + .adc_enable_a (adc_enable_a), + .adc_enable_b (adc_enable_b), + .adc_valid_a (), + .adc_valid_b (), + .dma_data (dma_data), + .dma_sync (1'b1), + .dma_wr (dma_wr), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .ps_intr_0 (ps_intrs[0]), + .ps_intr_1 (ps_intrs[1]), + .ps_intr_10 (ps_intrs[10]), + .ps_intr_11 (ps_intrs[11]), + .ps_intr_12 (ps_intrs[12]), + .ps_intr_13 (ps_intrs[13]), + .ps_intr_2 (ps_intrs[2]), + .ps_intr_3 (ps_intrs[3]), + .ps_intr_4 (ps_intrs[4]), + .ps_intr_5 (ps_intrs[5]), + .ps_intr_6 (ps_intrs[6]), + .ps_intr_7 (ps_intrs[7]), + .ps_intr_8 (ps_intrs[8]), + .ps_intr_9 (ps_intrs[9]), + .rx_data_n (rx_data_n), + .rx_data_p (rx_data_p), + .rx_ref_clk (rx_ref_clk), + .rx_sync (rx_sync), + .rx_sysref (rx_sysref), + .spdif (spdif), + .spi_clk_i (1'b0), + .spi_clk_o (spi_clk), + .spi_csn_i (1'b1), + .spi_csn_o (spi_csn), + .spi_sdi_i (spi_miso), + .spi_sdo_i (1'b0), + .spi_sdo_o (spi_mosi)); + +endmodule + +// *************************************************************************** +// ***************************************************************************