diff --git a/projects/sdrstk/system_bd.tcl b/projects/sdrstk/system_bd.tcl index 6e482a32c..5ca44c4a5 100644 --- a/projects/sdrstk/system_bd.tcl +++ b/projects/sdrstk/system_bd.tcl @@ -82,14 +82,10 @@ set_property -dict [list CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}] $sys_ps7 set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}] $sys_ps7 -set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.066}] $sys_ps7 -set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.029}] $sys_ps7 -set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.017}] $sys_ps7 -set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.038}] $sys_ps7 -set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.301}] $sys_ps7 -set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.330}] $sys_ps7 -set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.314}] $sys_ps7 -set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.333}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.048}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.050}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.241}] $sys_ps7 +set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.240}] $sys_ps7 set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc] set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc diff --git a/projects/sdrstk/system_constr.xdc b/projects/sdrstk/system_constr.xdc index bb185337e..678037305 100644 --- a/projects/sdrstk/system_constr.xdc +++ b/projects/sdrstk/system_constr.xdc @@ -3,33 +3,33 @@ set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18 } [get_ports rx_clk_in] set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18 } [get_ports rx_frame_in] -set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[0]] -set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[1]] -set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[2]] -set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[3]] -set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[4]] -set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[5]] -set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[6]] -set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[7]] -set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[8]] -set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[9]] -set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[10]] -set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[11]] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[0]] +set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[1]] +set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[2]] +set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[3]] +set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[4]] +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[5]] +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[6]] +set_property -dict {PACKAGE_PIN P13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[7]] +set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[8]] +set_property -dict {PACKAGE_PIN M9 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[9]] +set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[10]] +set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[11]] set_property -dict {PACKAGE_PIN P10 IOSTANDARD LVCMOS18} [get_ports tx_clk_out] set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS18} [get_ports tx_frame_out] -set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]] -set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]] -set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]] -set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]] -set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]] -set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]] -set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]] -set_property -dict {PACKAGE_PIN P13 IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]] -set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]] -set_property -dict {PACKAGE_PIN M9 IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]] -set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]] -set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]] +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]] +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]] +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]] +set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]] +set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]] +set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]] +set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]] +set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]] +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]] +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]] +set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]] +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]] set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] @@ -56,8 +56,8 @@ set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn] set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports spi_clk] -set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports spi_mosi] -set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports spi_miso] +set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports spi_mosi] +set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports spi_miso] set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports gpio_bd] set_property -dict {PACKAGE_PIN P8 IOSTANDARD LVCMOS18} [get_ports clk_out]