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jesd204_soft_pcs_rx: Add support for lane polarity inversion 

Some designs choose to swap the positive and negative side of the of the
JESD204 lanes. One reason for this would be because it can simplify the
PCB layout.

To support this add a parameter to the jesd204_soft_pcs_rx module that
allows to specify whether the lane polarity is inverted or not.

The way the polarity inversion is implemented it is for free since it will
only invert the input mapping of the 8b10b decoder LUT tables.

The pattern align module does not care whether the polarity is inverted or
not since the pattern align symbols look the same in both cases.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2018-04-05 13:08:02 +02:00 committed by Lars-Peter Clausen
parent ee57f869f1
commit 30c3f8244c
2 changed files with 6 additions and 3 deletions
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8
library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v
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@ -45,7 +45,8 @@
module jesd204_soft_pcs_rx #( module jesd204_soft_pcs_rx #(
parameter NUM_LANES = 1, parameter NUM_LANES = 1,
parameter DATA_PATH_WIDTH = 4, parameter DATA_PATH_WIDTH = 4,
parameter REGISTER_INPUTS = 0 parameter REGISTER_INPUTS = 0,
parameter INVERT_INPUTS = 0
) ( ) (
input clk, input clk,
input reset, input reset,
@ -94,7 +95,6 @@ if (REGISTER_INPUTS == 1) begin
end end
assign patternalign_en_s = patternalign_en_r; assign patternalign_en_s = patternalign_en_r;
assign data_s = data_r; assign data_s = data_r;
end else begin end else begin
assign patternalign_en_s = patternalign_en; assign patternalign_en_s = patternalign_en;
assign data_s = data; assign data_s = data;
@ -125,9 +125,11 @@ for (lane = 0; lane < NUM_LANES; lane = lane + 1) begin: gen_lane
for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_dpw for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_dpw
localparam j = DATA_PATH_WIDTH * lane + i; localparam j = DATA_PATH_WIDTH * lane + i;
wire [9:0] in_char = INVERT_INPUTS ? ~data_aligned[j*10+:10] :
data_aligned[j*10+:10];
jesd204_8b10b_decoder i_dec ( jesd204_8b10b_decoder i_dec (
.in_char(data_aligned[j*10+:10]), .in_char(in_char),
.out_char(char_s[j*8+:8]), .out_char(char_s[j*8+:8]),
.out_charisk(charisk_s[j]), .out_charisk(charisk_s[j]),
.out_notintable(notintable_s[j]), .out_notintable(notintable_s[j]),

1
library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl
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@ -50,6 +50,7 @@ source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
ad_ip_create jesd204_soft_pcs_rx "ADI JESD204 Transmit Soft PCS" ad_ip_create jesd204_soft_pcs_rx "ADI JESD204 Transmit Soft PCS"
ad_ip_parameter REGISTER_INPUTS INTEGER 0 ad_ip_parameter REGISTER_INPUTS INTEGER 0
ad_ip_parameter INVERT_INPUTS INTEGER 0
set_module_property INTERNAL true set_module_property INTERNAL true