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adrv9364: Use new pack/unpack infrastructure 

Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Matt Fornero <matt.fornero@mathworks.com>
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Matt Fornero 2017-12-19 10:03:22 -08:00 committed by Adrian Costina
parent 0a67746352
commit 3052c28c01
4 changed files with 44 additions and 52 deletions
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4
projects/adrv9364z7020/ccbob_cmos/Makefile
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@ -17,10 +17,10 @@ LIB_DEPS += axi_ad9361
LIB_DEPS += axi_dmac LIB_DEPS += axi_dmac
LIB_DEPS += axi_gpreg LIB_DEPS += axi_gpreg
LIB_DEPS += util_clkdiv LIB_DEPS += util_clkdiv
LIB_DEPS += util_cpack LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo LIB_DEPS += util_rfifo
LIB_DEPS += util_tdd_sync LIB_DEPS += util_tdd_sync
LIB_DEPS += util_upack
LIB_DEPS += util_wfifo LIB_DEPS += util_wfifo
include ../../scripts/project-xilinx.mk include ../../scripts/project-xilinx.mk

4
projects/adrv9364z7020/ccbob_lvds/Makefile
View File

@ -17,10 +17,10 @@ LIB_DEPS += axi_ad9361
LIB_DEPS += axi_dmac LIB_DEPS += axi_dmac
LIB_DEPS += axi_gpreg LIB_DEPS += axi_gpreg
LIB_DEPS += util_clkdiv LIB_DEPS += util_clkdiv
LIB_DEPS += util_cpack LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo LIB_DEPS += util_rfifo
LIB_DEPS += util_tdd_sync LIB_DEPS += util_tdd_sync
LIB_DEPS += util_upack
LIB_DEPS += util_wfifo LIB_DEPS += util_wfifo
include ../../scripts/project-xilinx.mk include ../../scripts/project-xilinx.mk

4
projects/adrv9364z7020/ccbox_lvds/Makefile
View File

@ -18,10 +18,10 @@ LIB_DEPS += axi_ad9361
LIB_DEPS += axi_dmac LIB_DEPS += axi_dmac
LIB_DEPS += axi_i2s_adi LIB_DEPS += axi_i2s_adi
LIB_DEPS += util_clkdiv LIB_DEPS += util_clkdiv
LIB_DEPS += util_cpack LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo LIB_DEPS += util_rfifo
LIB_DEPS += util_tdd_sync LIB_DEPS += util_tdd_sync
LIB_DEPS += util_upack
LIB_DEPS += util_wfifo LIB_DEPS += util_wfifo
include ../../scripts/project-xilinx.mk include ../../scripts/project-xilinx.mk

84
projects/adrv9364z7020/common/adrv9364z7020_bd.tcl
View File

@ -276,23 +276,21 @@ ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
# adc-path channel pack # adc-path channel pack
ad_ip_instance util_cpack util_ad9361_adc_pack ad_ip_instance util_cpack2 util_ad9361_adc_pack { \
ad_ip_parameter util_ad9361_adc_pack CONFIG.NUM_OF_CHANNELS 4 NUM_OF_CHANNELS 4 \
ad_ip_parameter util_ad9361_adc_pack CONFIG.CHANNEL_DATA_WIDTH 16 SAMPLE_DATA_WIDTH 16 \
ad_connect util_ad9361_divclk/clk_out util_ad9361_adc_pack/adc_clk }
ad_connect util_ad9361_divclk_reset/peripheral_reset util_ad9361_adc_pack/adc_rst
ad_connect util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0 ad_connect util_ad9361_divclk/clk_out util_ad9361_adc_pack/clk
ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0 ad_connect util_ad9361_divclk_reset/peripheral_reset util_ad9361_adc_pack/reset
ad_connect util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0
ad_connect util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1 ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/fifo_wr_en
ad_connect util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1 ad_connect util_ad9361_adc_pack/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
ad_connect util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1
ad_connect util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2 for {set i 0} {$i < 4} {incr i} {
ad_connect util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2 ad_connect util_ad9361_adc_fifo/dout_enable_${i} util_ad9361_adc_pack/enable_${i}
ad_connect util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2 ad_connect util_ad9361_adc_fifo/dout_data_${i} util_ad9361_adc_pack/fifo_wr_data_${i}
ad_connect util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3 }
ad_connect util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3
ad_connect util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3
# adc-path dma # adc-path dma
@ -306,10 +304,7 @@ ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 64 ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_connect util_ad9361_divclk/clk_out axi_ad9361_adc_dma/fifo_wr_clk ad_connect util_ad9361_divclk/clk_out axi_ad9361_adc_dma/fifo_wr_clk
ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en ad_connect util_ad9361_adc_pack/packed_fifo_wr axi_ad9361_adc_dma/fifo_wr
ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn
# dac-path rfifo # dac-path rfifo
@ -338,40 +333,37 @@ ad_connect axi_ad9361_dac_fifo/dout_unf axi_ad9361/dac_dunf
# dac-path channel unpack # dac-path channel unpack
ad_ip_instance util_upack util_ad9361_dac_upack ad_ip_instance util_upack2 util_ad9361_dac_upack { \
ad_ip_parameter util_ad9361_dac_upack CONFIG.NUM_OF_CHANNELS 4 NUM_OF_CHANNELS 4 \
ad_ip_parameter util_ad9361_dac_upack CONFIG.CHANNEL_DATA_WIDTH 16 SAMPLE_DATA_WIDTH 16 \
ad_connect util_ad9361_divclk/clk_out util_ad9361_dac_upack/dac_clk }
ad_connect util_ad9361_dac_upack/dac_enable_0 axi_ad9361_dac_fifo/din_enable_0
ad_connect util_ad9361_dac_upack/dac_valid_0 axi_ad9361_dac_fifo/din_valid_0 ad_connect util_ad9361_divclk/clk_out util_ad9361_dac_upack/clk
ad_connect util_ad9361_dac_upack/dac_valid_out_0 axi_ad9361_dac_fifo/din_valid_in_0 ad_connect util_ad9361_divclk_reset/peripheral_reset util_ad9361_dac_upack/reset
ad_connect util_ad9361_dac_upack/dac_data_0 axi_ad9361_dac_fifo/din_data_0
ad_connect util_ad9361_dac_upack/dac_enable_1 axi_ad9361_dac_fifo/din_enable_1 ad_connect util_ad9361_dac_upack/fifo_rd_en axi_ad9361_dac_fifo/din_valid_0
ad_connect util_ad9361_dac_upack/dac_valid_1 axi_ad9361_dac_fifo/din_valid_1 ad_connect util_ad9361_dac_upack/fifo_rd_underflow axi_ad9361_dac_fifo/din_unf
ad_connect util_ad9361_dac_upack/dac_valid_out_1 axi_ad9361_dac_fifo/din_valid_in_1
ad_connect util_ad9361_dac_upack/dac_data_1 axi_ad9361_dac_fifo/din_data_1 for {set i 0} {$i < 4} {incr i} {
ad_connect util_ad9361_dac_upack/dac_enable_2 axi_ad9361_dac_fifo/din_enable_2 ad_connect util_ad9361_dac_upack/enable_$i axi_ad9361_dac_fifo/din_enable_$i
ad_connect util_ad9361_dac_upack/dac_valid_2 axi_ad9361_dac_fifo/din_valid_2 ad_connect util_ad9361_dac_upack/fifo_rd_valid axi_ad9361_dac_fifo/din_valid_in_$i
ad_connect util_ad9361_dac_upack/dac_valid_out_2 axi_ad9361_dac_fifo/din_valid_in_2 ad_connect util_ad9361_dac_upack/fifo_rd_data_$i axi_ad9361_dac_fifo/din_data_$i
ad_connect util_ad9361_dac_upack/dac_data_2 axi_ad9361_dac_fifo/din_data_2 }
ad_connect util_ad9361_dac_upack/dac_enable_3 axi_ad9361_dac_fifo/din_enable_3
ad_connect util_ad9361_dac_upack/dac_valid_3 axi_ad9361_dac_fifo/din_valid_3
ad_connect util_ad9361_dac_upack/dac_valid_out_3 axi_ad9361_dac_fifo/din_valid_in_3
ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361_dac_fifo/din_data_3
# dac-path dma # dac-path dma
ad_ip_instance axi_dmac axi_ad9361_dac_dma ad_ip_instance axi_dmac axi_ad9361_dac_dma
ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_SRC 0 ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_DEST 2 ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_DEST 1
ad_ip_parameter axi_ad9361_dac_dma CONFIG.CYCLIC 1 ad_ip_parameter axi_ad9361_dac_dma CONFIG.CYCLIC 1
ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_SRC 0 ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_DEST 1 ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 64 ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_connect util_ad9361_divclk/clk_out axi_ad9361_dac_dma/fifo_rd_clk
ad_connect axi_ad9361_dac_dma/fifo_rd_en util_ad9361_dac_upack/dac_valid ad_connect util_ad9361_divclk/clk_out axi_ad9361_dac_dma/m_axis_aclk
ad_connect axi_ad9361_dac_dma/fifo_rd_dout util_ad9361_dac_upack/dac_data ad_connect axi_ad9361_dac_dma/m_axis util_ad9361_dac_upack/s_axis
ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
# interconnects # interconnects