fmcomms2: Updated mitx045 project. Updated constraints. Updated interrupts
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@ -62,8 +62,3 @@ set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports spi_miso
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create_clock -name rx_clk -period 4.00 [get_ports rx_clk_in_p]
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create_clock -name ad9361_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
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create_clock -name fmc_dma_clk -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
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set_clock_groups -asynchronous -group {ad9361_clk}
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set_clock_groups -asynchronous -group {fmc_dma_clk}
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@ -183,6 +183,7 @@ module system_top (
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wire [48:0] gpio_o;
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wire [48:0] gpio_t;
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wire [19:0] gpio_wire;
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wire [15:0] ps_intrs;
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// instantiations
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@ -237,6 +238,22 @@ module system_top (
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.i2s_sdata_out (i2s_sdata_out),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.ps_intr_0 (ps_intrs[0]),
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.ps_intr_1 (ps_intrs[1]),
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.ps_intr_10 (ps_intrs[10]),
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.ps_intr_11 (ps_intrs[11]),
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.ps_intr_12 (ps_intrs[12]),
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.ps_intr_13 (ps_intrs[13]),
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.ps_intr_2 (ps_intrs[2]),
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.ps_intr_3 (ps_intrs[3]),
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.ps_intr_4 (ps_intrs[4]),
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.ps_intr_5 (ps_intrs[5]),
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.ps_intr_6 (ps_intrs[6]),
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.ps_intr_7 (ps_intrs[7]),
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.ps_intr_8 (ps_intrs[8]),
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.ps_intr_9 (ps_intrs[9]),
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.ad9361_dac_dma_irq (ps_intrs[12]),
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.ad9361_adc_dma_irq (ps_intrs[13]),
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.rx_clk_in_n (rx_clk_in_n),
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.rx_clk_in_p (rx_clk_in_p),
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.rx_data_in_n (rx_data_in_n),
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