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adrv9371x/zc706: Update project with the new axi_dacfifo

main
Istvan Csomortani 2016-06-22 12:33:47 +03:00
parent cdf01a492e
commit 2e80dec513
2 changed files with 9 additions and 4 deletions
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7
projects/adrv9371x/common/adrv9371x_bd.tcl
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@ -36,7 +36,7 @@ ad_connect sys_dma_rstgen/ext_reset_in sys_ps7/FCLK_RESET2_N
set axi_ad9371_tx_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9371_tx_dma]
set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9371_tx_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9371_tx_dma
@ -251,14 +251,15 @@ ad_connect axi_ad9371_core/dac_valid_q1 util_ad9371_tx_upack/dac_valid_3
ad_connect axi_ad9371_core/dac_enable_q1 util_ad9371_tx_upack/dac_enable_3
ad_connect axi_ad9371_core/dac_data_q1 util_ad9371_tx_upack/dac_data_3
ad_connect axi_tx_clkgen/clk_0 axi_ad9371_tx_dma/m_axis_aclk
ad_connect pl_ddr_clk axi_ad9371_dacfifo/ddr_clk
ad_connect pl_ddr_clk axi_ad9371_tx_dma/m_axis_aclk
ad_connect pl_ddr_clk axi_ad9371_dacfifo/dma_clk
ad_connect sys_dma_resetn axi_ad9371_tx_dma/m_src_axi_aresetn
ad_connect util_ad9371_gt/tx_rst axi_ad9371_dacfifo/dac_rst
ad_connect util_ad9371_tx_upack/dma_xfer_in axi_ad9371_dacfifo/dac_xfer_out
ad_connect axi_tx_clkgen/clk_0 axi_ad9371_dacfifo/dac_clk
ad_connect util_ad9371_tx_upack/dac_valid axi_ad9371_dacfifo/dac_valid
ad_connect util_ad9371_tx_upack/dac_data axi_ad9371_dacfifo/dac_data
ad_connect axi_tx_clkgen/clk_0 axi_ad9371_dacfifo/dma_clk
ad_connect axi_ad9371_dacfifo/dma_xfer_req axi_ad9371_tx_dma/m_axis_xfer_req
ad_connect axi_ad9371_dacfifo/dma_rready axi_ad9371_tx_dma/m_axis_ready

6
projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
View File

@ -33,6 +33,8 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
create_bd_pin -dir I dma_xfer_req
create_bd_pin -dir I dma_xfer_last
create_bd_pin -dir O ddr_clk
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/"
@ -50,6 +52,7 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
set_property -dict [list CONFIG.AXI_LENGTH {15}] $axi_dacfifo
set_property -dict [list CONFIG.AXI_ADDRESS {0x80000000}] $axi_dacfifo
set_property -dict [list CONFIG.AXI_ADDRESS_LIMIT {0xa0000000}] $axi_dacfifo
set_property -dict [list CONFIG.BYPASS_EN {1}] $axi_dacfifo
## clock and reset
@ -58,8 +61,9 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
ad_connect axi_clk axi_ddr_cntrl/ui_clk
ad_connect axi_clk axi_dacfifo/axi_clk
ad_connect axi_clk axi_rstgen/slowest_sync_clk
ad_connect dac_clk axi_dacfifo/dac_clk
ad_connect dma_clk axi_dacfifo/dma_clk
ad_connect ddr_clk axi_ddr_cntrl/ui_clk
ad_connect dac_clk axi_dacfifo/dac_clk
ad_connect axi_resetn axi_rstgen/peripheral_aresetn
ad_connect axi_resetn axi_dacfifo/axi_resetn