fmcomms1: Updated VC707 project with latest interrupts and linear flash. Fixed constraints and constraint priority

projects/fmcomms1/vc707/system_constr.xdc

@@ -85,13 +85,6 @@ set_property  -dict {PACKAGE_PIN AG41   IOSTANDARD LVDS DIFF_TERM TRUE} [get_por
 create_clock -name dac_clk_in   -period  2.00  [get_ports dac_clk_in_p]
 create_clock -name adc_clk_in   -period  4.00  [get_ports adc_clk_in_p]
 create_clock -name dac_div_clk  -period  8.00  [get_pins i_system_wrapper/system_i/axi_ad9122/dac_div_clk]
-create_clock -name adc_clk      -period  4.00  [get_pins i_system_wrapper/system_i/axi_ad9643/adc_clk]
-create_clock -name ref_clk      -period  33.33 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out2]
-create_clock -name ila_clk      -period  8.00   [get_pins i_system_wrapper/system_i/ila_clkgen/clk_out1]
-
-set_clock_groups -asynchronous -group {dac_div_clk}
-set_clock_groups -asynchronous -group {adc_clk}
-set_clock_groups -asynchronous -group {ref_clk}
-set_clock_groups -asynchronous -group {ila_clk}
-
 
+set_false_path -from [get_pins i_system_wrapper/system_i/axi_ad9643_dma/inst/i_request_arb/i_src_dma_fifo/overflow_reg/C] \
+               -to [get_pins i_system_wrapper/system_i/sys_wfifo/wfifo_ctl/inst/m_wovf_m1_reg/D]

projects/fmcomms1/vc707/system_project.tcl

@@ -10,6 +10,9 @@ adi_project_files fmcomms1_vc707 [list \
   "system_constr.xdc"\
   "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
 
+set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc]
+set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
+
 adi_project_run fmcomms1_vc707
 
 

projects/fmcomms1/vc707/system_top.v

@@ -77,6 +77,13 @@ module system_top (
 
   fan_pwm,
 
+  linear_flash_addr,
+  linear_flash_adv_ldn,
+  linear_flash_ce_n,
+  linear_flash_oen,
+  linear_flash_wen,
+  linear_flash_dq_io,
+
   gpio_lcd,
   gpio_led,
   gpio_sw,
@@ -148,6 +155,13 @@ module system_top (
 
   output          fan_pwm;
 
+  output  [26:1]  linear_flash_addr;
+  output          linear_flash_adv_ldn;
+  output          linear_flash_ce_n;
+  output          linear_flash_oen;
+  output          linear_flash_wen;
+  inout   [15:0]  linear_flash_dq_io;
+
   output  [ 6:0]  gpio_lcd;
   output  [ 7:0]  gpio_led;
   input   [12:0]  gpio_sw;
@@ -208,6 +222,11 @@ module system_top (
   wire    [15:0]  adc_data_1;
   wire            ref_clk;
   wire            oddr_ref_clk;
+  wire    [31:0]  mb_intrs;
+
+  // assignments
+
+  assign fan_pwm = 1'b1;
 
   // instantiations
 
@@ -275,7 +294,12 @@ module system_top (
     .ddr3_ras_n (ddr3_ras_n),
     .ddr3_reset_n (ddr3_reset_n),
     .ddr3_we_n (ddr3_we_n),
-    .fan_pwm (fan_pwm),
+    .linear_flash_addr (linear_flash_addr),
+    .linear_flash_adv_ldn (linear_flash_adv_ldn),
+    .linear_flash_ce_n (linear_flash_ce_n),
+    .linear_flash_oen (linear_flash_oen),
+    .linear_flash_wen (linear_flash_wen),
+    .linear_flash_dq_io(linear_flash_dq_io),
     .gpio_lcd_tri_o (gpio_lcd),
     .gpio_led_tri_o (gpio_led),
     .gpio_sw_tri_i (gpio_sw),
@@ -321,6 +345,30 @@ module system_top (
     .iic_main_scl_io (iic_scl),
     .iic_main_sda_io (iic_sda),
     .iic_rstn (iic_rstn),
+    .mb_intr_10 (mb_intrs[10]),
+    .mb_intr_11 (mb_intrs[11]),
+    .mb_intr_12 (mb_intrs[12]),
+    .mb_intr_13 (mb_intrs[13]),
+    .mb_intr_14 (mb_intrs[14]),
+    .mb_intr_15 (mb_intrs[15]),
+    .mb_intr_16 (mb_intrs[16]),
+    .mb_intr_17 (mb_intrs[17]),
+    .mb_intr_18 (mb_intrs[18]),
+    .mb_intr_19 (mb_intrs[19]),
+    .mb_intr_20 (mb_intrs[20]),
+    .mb_intr_21 (mb_intrs[21]),
+    .mb_intr_22 (mb_intrs[22]),
+    .mb_intr_23 (mb_intrs[23]),
+    .mb_intr_24 (mb_intrs[24]),
+    .mb_intr_25 (mb_intrs[25]),
+    .mb_intr_26 (mb_intrs[26]),
+    .mb_intr_27 (mb_intrs[27]),
+    .mb_intr_28 (mb_intrs[28]),
+    .mb_intr_29 (mb_intrs[29]),
+    .mb_intr_30 (mb_intrs[30]),
+    .mb_intr_31 (mb_intrs[31]),
+    .ad9122_dma_irq (mb_intrs[12]),
+    .ad9643_dma_irq (mb_intrs[13]),
     .mdio_mdc (mdio_mdc),
     .mdio_mdio_io (mdio_mdio),
     .mgt_clk_clk_n (mgt_clk_n),
@@ -335,10 +383,7 @@ module system_top (
     .sys_clk_p (sys_clk_p),
     .sys_rst (sys_rst),
     .uart_sin (uart_sin),
-    .uart_sout (uart_sout),
+    .uart_sout (uart_sout));
-    .unc_int0 (1'b0),
-    .unc_int1 (1'b0),
-    .unc_int4 (1'b0));
 
 endmodule