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axi_ad9361_tdd: Initial commit. 

Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
main
Istvan Csomortani 2015-05-11 12:09:09 +03:00
parent 00335a2af2
commit 2e7135c3c2
7 changed files with 1375 additions and 11 deletions
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6
library/axi_ad9361/Makefile
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@ -20,6 +20,7 @@ M_DEPS += ../common/ad_dds.v
M_DEPS += ../common/ad_datafmt.v
M_DEPS += ../common/ad_dcfilter.v
M_DEPS += ../common/ad_iqcor.v
M_DEPS += ../common/ad_tdd_control.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
@ -30,14 +31,17 @@ M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../common/up_tdd_cntrl.v
M_DEPS += axi_ad9361_dev_if.v
M_DEPS += axi_ad9361_rx_pnmon.v
M_DEPS += axi_ad9361_rx_channel.v
M_DEPS += axi_ad9361_rx.v
M_DEPS += axi_ad9361_tx_channel.v
M_DEPS += axi_ad9361_tx.v
M_DEPS += axi_ad9361.v
M_DEPS += axi_ad9361_tdd.v
M_DEPS += axi_ad9361_tdd_if.v
M_DEPS += axi_ad9361_constr.xdc
M_DEPS += axi_ad9361.v
M_VIVADO := vivado -mode batch -source

89
library/axi_ad9361/axi_ad9361.v
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@ -107,6 +107,9 @@ module axi_ad9361 (
dac_dunf,
dac_r1_mode,
tdd_enable,
tdd_txnrx,
// axi interface
s_axi_aclk,
@ -141,7 +144,9 @@ module axi_ad9361 (
// chipscope signals
dev_dbg_data,
dev_l_dbg_data);
dev_l_dbg_data,
tdd_dbg);
// parameters
@ -218,6 +223,9 @@ module axi_ad9361 (
input dac_dunf;
output dac_r1_mode;
output tdd_enable;
output tdd_txnrx;
// axi interface
input s_axi_aclk;
@ -254,6 +262,8 @@ module axi_ad9361 (
output [111:0] dev_dbg_data;
output [ 61:0] dev_l_dbg_data;
output [34:0] tdd_dbg;
// internal registers
reg up_wack = 'd0;
@ -293,6 +303,25 @@ module axi_ad9361 (
wire up_rack_rx_s;
wire [31:0] up_rdata_tx_s;
wire up_rack_tx_s;
wire up_wack_tdd_s;
wire up_rack_tdd_s;
wire [31:0] up_rdata_tdd_s;
wire tdd_tx_dp_en_s;
wire tdd_rx_vco_en_s;
wire tdd_tx_vco_en_s;
wire tdd_rx_rf_en_s;
wire tdd_tx_rf_en_s;
wire [ 7:0] ad9361_tdd_status_s;
wire tdd_enable;
wire tdd_txnrx;
wire dac_valid_i0_s;
wire dac_valid_q0_s;
wire dac_valid_i1_s;
wire dac_valid_q1_s;
wire tdd_mode_enable_s;
// signal name changes
@ -307,9 +336,9 @@ module axi_ad9361 (
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_wack <= up_wack_rx_s | up_wack_tx_s;
up_rack <= up_rack_rx_s | up_rack_tx_s;
up_rdata <= up_rdata_rx_s | up_rdata_tx_s;
up_wack <= up_wack_rx_s | up_wack_tx_s | up_wack_tdd_s;
up_rack <= up_rack_rx_s | up_rack_tx_s | up_rack_tdd_s;
up_rdata <= up_rdata_rx_s | up_rdata_tx_s | up_rdata_tdd_s;
end
end
@ -354,6 +383,45 @@ module axi_ad9361 (
.dev_dbg_data (dev_dbg_data),
.dev_l_dbg_data (dev_l_dbg_data));
// TDD interface
axi_ad9361_tdd_if #(.MODE_OF_ENABLE(1)) i_tdd_if(
.clk(clk),
.rst(tdd_rst),
.tdd_rx_vco_en(tdd_rx_vco_en_s),
.tdd_tx_vco_en(tdd_tx_vco_en_s),
.tdd_rx_rf_en(tdd_rx_rf_en_s),
.tdd_tx_rf_en(tdd_tx_rf_en_s),
.ad9361_txnrx(tdd_txnrx),
.ad9361_enable(tdd_enable),
.ad9361_tdd_status(ad9361_tdd_status_s)
);
// TDD control
axi_ad9361_tdd i_tdd(
.clk(clk),
.rst(tdd_rst),
.tdd_enable(tdd_mode_enable_s),
.tdd_tx_dp_en(tdd_tx_dp_en_s),
.tdd_rx_vco_en(tdd_rx_vco_en_s),
.tdd_tx_vco_en(tdd_tx_vco_en_s),
.tdd_rx_rf_en(tdd_rx_rf_en_s),
.tdd_tx_rf_en(tdd_tx_rf_en_s),
.tdd_status(ad9361_tdd_status_s),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq(up_wreq_s),
.up_waddr(up_waddr_s),
.up_wdata(up_wdata_s),
.up_wack(up_wack_tdd_s),
.up_rreq(up_rreq_s),
.up_raddr(up_raddr_s),
.up_rdata(up_rdata_tdd_s),
.up_rack(up_rack_tdd_s),
.tdd_dbg(tdd_dbg)
);
// receive
axi_ad9361_rx #(
@ -418,16 +486,16 @@ module axi_ad9361 (
.dac_sync_in (dac_sync_in),
.dac_sync_out (dac_sync_out),
.dac_enable_i0 (dac_enable_i0),
.dac_valid_i0 (dac_valid_i0),
.dac_valid_i0 (dac_valid_i0_s),
.dac_data_i0 (dac_data_i0),
.dac_enable_q0 (dac_enable_q0),
.dac_valid_q0 (dac_valid_q0),
.dac_valid_q0 (dac_valid_q0_s),
.dac_data_q0 (dac_data_q0),
.dac_enable_i1 (dac_enable_i1),
.dac_valid_i1 (dac_valid_i1),
.dac_valid_i1 (dac_valid_i1_s),
.dac_data_i1 (dac_data_i1),
.dac_enable_q1 (dac_enable_q1),
.dac_valid_q1 (dac_valid_q1),
.dac_valid_q1 (dac_valid_q1_s),
.dac_data_q1 (dac_data_q1),
.dac_dovf(dac_dovf),
.dac_dunf(dac_dunf),
@ -444,6 +512,11 @@ module axi_ad9361 (
.up_rdata (up_rdata_tx_s),
.up_rack (up_rack_tx_s));
assign dac_valid_i0 = (tdd_mode_enable_s == 1) ? (dac_valid_i0_s & tdd_tx_dp_en_s) : dac_valid_i0_s;
assign dac_valid_q0 = (tdd_mode_enable_s == 1) ? (dac_valid_q0_s & tdd_tx_dp_en_s) : dac_valid_q0_s;
assign dac_valid_i1 = (tdd_mode_enable_s == 1) ? (dac_valid_i1_s & tdd_tx_dp_en_s) : dac_valid_i1_s;
assign dac_valid_q1 = (tdd_mode_enable_s == 1) ? (dac_valid_q1_s & tdd_tx_dp_en_s) : dac_valid_q1_s;
// axi interface
up_axi i_up_axi (

8
library/axi_ad9361/axi_ad9361_ip.tcl
View File

@ -17,6 +17,7 @@ adi_ip_files axi_ad9361 [list \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/ad_dcfilter.v" \
"$ad_hdl_dir/library/common/ad_iqcor.v" \
"$ad_hdl_dir/library/common/ad_tdd_control.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
@ -27,14 +28,17 @@ adi_ip_files axi_ad9361 [list \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
"$ad_hdl_dir/library/common/up_tdd_cntrl.v" \
"axi_ad9361_dev_if.v" \
"axi_ad9361_rx_pnmon.v" \
"axi_ad9361_rx_channel.v" \
"axi_ad9361_rx.v" \
"axi_ad9361_tx_channel.v" \
"axi_ad9361_tx.v" \
"axi_ad9361.v" \
"axi_ad9361_constr.xdc" ]
"axi_ad9361_tdd.v" \
"axi_ad9361_tdd_if.v" \
"axi_ad9361_constr.xdc" \
"axi_ad9361.v" ]
adi_ip_properties axi_ad9361
adi_ip_constraints axi_dmac "axi_ad9361_constr.xdc" "late"

234
library/axi_ad9361/axi_ad9361_tdd.v Normal file
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@ -0,0 +1,234 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_ad9361_tdd (
// clock
clk,
rst,
// control signals from the tdd control
tdd_enable,
tdd_tx_dp_en,
tdd_rx_vco_en,
tdd_tx_vco_en,
tdd_rx_rf_en,
tdd_tx_rf_en,
// status signal
tdd_status,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack,
tdd_dbg
);
input clk;
output rst;
// control signals from the tdd control
output tdd_enable;
output tdd_tx_dp_en;
output tdd_rx_vco_en;
output tdd_tx_vco_en;
output tdd_rx_rf_en;
output tdd_tx_rf_en;
input [ 7:0] tdd_status;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
output [34:0] tdd_dbg;
// internal signals
wire rst;
wire tdd_start_s;
wire tdd_counter_reset_s;
wire tdd_update_regs_s;
wire tdd_secondary_s;
wire tdd_burst_en_s;
wire [ 5:0] tdd_burst_count_s;
wire tdd_infinite_burst_s;
wire [21:0] tdd_counter_init_s;
wire [21:0] tdd_frame_length_s;
wire [ 7:0] tdd_tx_dp_delay_s;
wire [21:0] tdd_vco_rx_on_1_s;
wire [21:0] tdd_vco_rx_off_1_s;
wire [21:0] tdd_vco_tx_on_1_s;
wire [21:0] tdd_vco_tx_off_1_s;
wire [21:0] tdd_rx_on_1_s;
wire [21:0] tdd_rx_off_1_s;
wire [21:0] tdd_tx_on_1_s;
wire [21:0] tdd_tx_off_1_s;
wire [21:0] tdd_tx_dp_on_1_s;
wire [21:0] tdd_tx_dp_off_1_s;
wire [21:0] tdd_vco_rx_on_2_s;
wire [21:0] tdd_vco_rx_off_2_s;
wire [21:0] tdd_vco_tx_on_2_s;
wire [21:0] tdd_vco_tx_off_2_s;
wire [21:0] tdd_rx_on_2_s;
wire [21:0] tdd_rx_off_2_s;
wire [21:0] tdd_tx_on_2_s;
wire [21:0] tdd_tx_off_2_s;
wire [21:0] tdd_tx_dp_on_2_s;
wire [21:0] tdd_tx_dp_off_2_s;
wire [29:0] tdd_counter_status;
assign tdd_dbg = {tdd_counter_status, tdd_enable, tdd_tx_dp_en,
tdd_rx_vco_en, tdd_tx_vco_en, tdd_rx_rf_en, tdd_tx_rf_en};
// instantiations
up_tdd_cntrl i_up_tdd_cntrl(
.clk(clk),
.tdd_enable(tdd_enable),
.tdd_start(tdd_start_s),
.tdd_rst(rst),
.tdd_counter_reset(tdd_counter_reset_s),
.tdd_update_regs(tdd_update_regs_s),
.tdd_secondary(tdd_secondary_s),
.tdd_burst_en(tdd_burst_en_s),
.tdd_burst_count(tdd_burst_count_s),
.tdd_infinite_burst(tdd_infinite_burst_s),
.tdd_counter_init(tdd_counter_init_s),
.tdd_frame_length(tdd_frame_length_s),
.tdd_tx_dp_delay(tdd_tx_dp_delay_s),
.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
.tdd_vco_tx_off_1(tdd_vco_tx_off_1_s),
.tdd_rx_on_1(tdd_rx_on_1_s),
.tdd_rx_off_1(tdd_rx_off_1_s),
.tdd_tx_on_1(tdd_tx_on_1_s),
.tdd_tx_off_1(tdd_tx_off_1_s),
.tdd_tx_dp_on_1(tdd_tx_dp_on_1_s),
.tdd_tx_dp_off_1(tdd_tx_dp_off_1_s),
.tdd_vco_rx_on_2(tdd_vco_rx_on_2_s),
.tdd_vco_rx_off_2(tdd_vco_rx_off_2_s),
.tdd_vco_tx_on_2(tdd_vco_tx_on_2_s),
.tdd_vco_tx_off_2(tdd_vco_tx_off_2_s),
.tdd_rx_on_2(tdd_rx_on_2_s),
.tdd_rx_off_2(tdd_rx_off_2_s),
.tdd_tx_on_2(tdd_tx_on_2_s),
.tdd_tx_off_2(tdd_tx_off_2_s),
.tdd_tx_dp_on_2(tdd_tx_dp_on_2_s),
.tdd_tx_dp_off_2(tdd_tx_dp_off_2_s),
.tdd_status(tdd_status),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_wack(up_wack),
.up_rreq(up_rreq),
.up_raddr(up_raddr),
.up_rdata(up_rdata),
.up_rack(up_rack));
ad_tdd_control i_tdd_control(
.clk(clk),
.rst(rst),
.tdd_start(tdd_start_s),
.tdd_counter_reset(tdd_counter_reset_s),
.tdd_update_regs(tdd_update_regs_s),
.tdd_secondary(tdd_secondary_s),
.tdd_counter_init(tdd_counter_init_s),
.tdd_frame_length(tdd_frame_length_s),
.tdd_burst_en(tdd_burst_en_s),
.tdd_burst_count(tdd_burst_count_s),
.tdd_infinite_burst(tdd_infinite_burst_s),
.tdd_tx_dp_delay(tdd_tx_dp_delay_s),
.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
.tdd_vco_tx_off_1(tdd_vco_tx_off_1_s),
.tdd_rx_on_1(tdd_rx_on_1_s),
.tdd_rx_off_1(tdd_rx_off_1_s),
.tdd_tx_on_1(tdd_tx_on_1_s),
.tdd_tx_off_1(tdd_tx_off_1_s),
.tdd_tx_dp_on_1(tdd_tx_dp_on_1_s),
.tdd_tx_dp_off_1(tdd_tx_dp_off_1_s),
.tdd_vco_rx_on_2(tdd_vco_rx_on_2_s),
.tdd_vco_rx_off_2(tdd_vco_rx_off_2_s),
.tdd_vco_tx_on_2(tdd_vco_tx_on_2_s),
.tdd_vco_tx_off_2(tdd_vco_tx_off_2_s),
.tdd_rx_on_2(tdd_rx_on_2_s),
.tdd_rx_off_2(tdd_rx_off_2_s),
.tdd_tx_on_2(tdd_tx_on_2_s),
.tdd_tx_off_2(tdd_tx_off_2_s),
.tdd_tx_dp_on_2(tdd_tx_dp_on_2_s),
.tdd_tx_dp_off_2(tdd_tx_dp_off_2_s),
.tdd_tx_dp_en(tdd_tx_dp_en),
.tdd_rx_vco_en(tdd_rx_vco_en),
.tdd_tx_vco_en(tdd_tx_vco_en),
.tdd_rx_rf_en(tdd_rx_rf_en),
.tdd_tx_rf_en(tdd_tx_rf_en),
.tdd_counter_status(tdd_counter_status));
endmodule

135
library/axi_ad9361/axi_ad9361_tdd_if.v Normal file
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@ -0,0 +1,135 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_ad9361_tdd_if(
// clock
clk,
rst,
// control signals from the tdd control
tdd_rx_vco_en,
tdd_tx_vco_en,
tdd_rx_rf_en,
tdd_tx_rf_en,
// device interface
ad9361_txnrx,
ad9361_enable,
// interface status
ad9361_tdd_status
);
// parameters
parameter MODE_OF_ENABLE = 0;
localparam PULSE_MODE = 0;
localparam LEVEL_MODE = 1;
// clock
input clk;
input rst;
// control signals from the tdd control
input tdd_rx_vco_en;
input tdd_tx_vco_en;
input tdd_rx_rf_en;
input tdd_tx_rf_en;
// device interface
output ad9361_txnrx;
output ad9361_enable;
// interface status
output [ 7:0] ad9361_tdd_status;
// internal registers
reg tdd_rx_rf_en_d = 1'b0;
reg tdd_tx_rf_en_d = 1'b0;
reg tdd_vco_overlap = 1'b0;
reg tdd_rf_overlap = 1'b0;
wire ad9361_txnrx_s;
wire ad9361_enable_s;
// just one VCO can be enabled at a time
assign ad9361_txnrx_s = tdd_tx_vco_en;
always @(posedge clk) begin
tdd_rx_rf_en_d <= tdd_rx_rf_en;
tdd_tx_rf_en_d <= tdd_tx_rf_en;
end
assign ad9361_enable_s = (MODE_OF_ENABLE == PULSE_MODE) ?
((~tdd_rx_rf_en_d & tdd_rx_rf_en) | (tdd_rx_rf_en_d & ~tdd_rx_rf_en) |
(~tdd_tx_rf_en_d & tdd_tx_rf_en) | (tdd_tx_rf_en_d & ~tdd_tx_rf_en)) :
(tdd_rx_rf_en | tdd_tx_rf_en);
always @(posedge clk) begin
if(rst == 1'b1) begin
tdd_vco_overlap <= 1'b0;
tdd_rf_overlap <= 1'b0;
end else begin
tdd_vco_overlap <= tdd_rx_vco_en & tdd_tx_vco_en;
tdd_rf_overlap <= tdd_rx_rf_en & tdd_tx_rf_en;
end
end
assign ad9361_tdd_status = {6'b0, tdd_rf_overlap, tdd_vco_overlap};
assign ad9361_txnrx = ad9361_txnrx_s;
assign ad9361_enable = ad9361_enable_s;
endmodule

417
library/common/ad_tdd_control.v Normal file
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@ -0,0 +1,417 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module ad_tdd_control(
// clock and reset
clk,
rst,
// TDD timming signals
tdd_start,
tdd_counter_reset,
tdd_update_regs,
tdd_secondary,
tdd_counter_init,
tdd_frame_length,
tdd_burst_en,
tdd_burst_count,
tdd_infinite_burst,
tdd_tx_dp_delay,
tdd_vco_rx_on_1,
tdd_vco_rx_off_1,
tdd_vco_tx_on_1,
tdd_vco_tx_off_1,
tdd_rx_on_1,
tdd_rx_off_1,
tdd_tx_on_1,
tdd_tx_off_1,
tdd_tx_dp_on_1,
tdd_tx_dp_off_1,
tdd_vco_rx_on_2,
tdd_vco_rx_off_2,
tdd_vco_tx_on_2,
tdd_vco_tx_off_2,
tdd_rx_on_2,
tdd_rx_off_2,
tdd_tx_on_2,
tdd_tx_off_2,
tdd_tx_dp_on_2,
tdd_tx_dp_off_2,
// TDD control signals
tdd_tx_dp_en,
tdd_rx_vco_en,
tdd_tx_vco_en,
tdd_rx_rf_en,
tdd_tx_rf_en,
tdd_counter_status);
// parameters
localparam ON = 1;
localparam OFF = 0;
// input/output signals
input clk;
input rst;
input tdd_start;
input tdd_secondary;
input tdd_counter_reset;
input tdd_update_regs;
input [21:0] tdd_counter_init;
input [21:0] tdd_frame_length;
input tdd_burst_en;
input [ 5:0] tdd_burst_count;
input tdd_infinite_burst;
input [ 7:0] tdd_tx_dp_delay;
input [21:0] tdd_vco_rx_on_1;
input [21:0] tdd_vco_rx_off_1;
input [21:0] tdd_vco_tx_on_1;
input [21:0] tdd_vco_tx_off_1;
input [21:0] tdd_rx_on_1;
input [21:0] tdd_rx_off_1;
input [21:0] tdd_tx_on_1;
input [21:0] tdd_tx_off_1;
input [21:0] tdd_tx_dp_on_1;
input [21:0] tdd_tx_dp_off_1;
input [21:0] tdd_vco_rx_on_2;
input [21:0] tdd_vco_rx_off_2;
input [21:0] tdd_vco_tx_on_2;
input [21:0] tdd_vco_tx_off_2;
input [21:0] tdd_rx_on_2;
input [21:0] tdd_rx_off_2;
input [21:0] tdd_tx_on_2;
input [21:0] tdd_tx_off_2;
input [21:0] tdd_tx_dp_on_2;
input [21:0] tdd_tx_dp_off_2;
output tdd_tx_dp_en; // initiate vco tx2rx switch
output tdd_rx_vco_en; // initiate vco rx2tx switch
output tdd_tx_vco_en; // power up RF Rx
output tdd_rx_rf_en; // power up RF Tx
output tdd_tx_rf_en; // enable Tx datapath
output [23:0] tdd_counter_status;
// tdd control related
reg tdd_secondary_d = 1'h0;
reg tdd_start_d = 1'h0;
reg [21:0] tdd_counter_init_d = 22'h0;
reg [21:0] tdd_frame_length_d = 22'h0;
reg tdd_burst_en_d = 1'h0;
reg [ 5:0] tdd_burst_count_d = 5'h0;
reg tdd_infinite_burst_d = 1'h0;
reg [ 7:0] tdd_tx_dp_delay_d = 8'h0;
reg [21:0] tdd_vco_rx_on_1_d = 22'h0;
reg [21:0] tdd_vco_rx_off_1_d = 22'h0;
reg [21:0] tdd_vco_tx_on_1_d = 22'h0;
reg [21:0] tdd_vco_tx_off_1_d = 22'h0;
reg [21:0] tdd_rx_on_1_d = 22'h0;
reg [21:0] tdd_rx_off_1_d = 22'h0;
reg [21:0] tdd_tx_on_1_d = 22'h0;
reg [21:0] tdd_tx_off_1_d = 22'h0;
reg [21:0] tdd_tx_dp_on_1_d = 22'h0;
reg [21:0] tdd_tx_dp_off_1_d = 22'h0;
reg [21:0] tdd_vco_rx_on_2_d = 22'h0;
reg [21:0] tdd_vco_rx_off_2_d = 22'h0;
reg [21:0] tdd_vco_tx_on_2_d = 22'h0;
reg [21:0] tdd_vco_tx_off_2_d = 22'h0;
reg [21:0] tdd_rx_on_2_d = 22'h0;
reg [21:0] tdd_rx_off_2_d = 22'h0;
reg [21:0] tdd_tx_on_2_d = 22'h0;
reg [21:0] tdd_tx_off_2_d = 22'h0;
reg [21:0] tdd_tx_dp_on_2_d = 22'h0;
reg [21:0] tdd_tx_dp_off_2_d = 22'h0;
reg tdd_tx_dp_en = 1'b0;
reg tdd_rx_vco_en = 1'b0;
reg tdd_tx_vco_en = 1'b0;
reg tdd_rx_rf_en = 1'b0;
reg tdd_tx_rf_en = 1'b0;
// tdd counter related
reg [21:0] tdd_counter = 22'h0;
reg [ 5:0] tdd_burst_counter = 6'h0;
reg tdd_counter_state = OFF;
reg tdd_burst_state = OFF;
assign tdd_counter_status = tdd_counter;
// ***************************************************************************
// all the control registers needs to be updated at the same time
// ***************************************************************************
always @(posedge clk) begin
if(rst == 1'b1) begin
tdd_secondary_d <= 1'h0;
tdd_start_d <= 1'h0;
tdd_counter_init_d <= 22'h0;
tdd_frame_length_d <= 22'h0;
tdd_burst_en_d <= 1'h0;
tdd_burst_count_d <= 5'h0;
tdd_infinite_burst_d <= 1'h0;
tdd_tx_dp_delay_d <= 8'h0;
tdd_vco_rx_on_1_d <= 22'h0;
tdd_vco_rx_on_1_d <= 22'h0;
tdd_vco_tx_on_1_d <= 22'h0;
tdd_vco_tx_off_1_d <= 22'h0;
tdd_rx_on_1_d <= 22'h0;
tdd_rx_off_1_d <= 22'h0;
tdd_tx_on_1_d <= 22'h0;
tdd_tx_off_1_d <= 22'h0;
tdd_tx_dp_on_1_d <= 22'h0;
tdd_tx_dp_off_1_d <= 22'h0;
tdd_vco_rx_on_2_d <= 22'h0;
tdd_vco_rx_off_2_d <= 22'h0;
tdd_vco_tx_on_2_d <= 22'h0;
tdd_vco_tx_off_2_d <= 22'h0;
tdd_rx_on_2_d <= 22'h0;
tdd_rx_off_2_d <= 22'h0;
tdd_tx_on_2_d <= 22'h0;
tdd_tx_off_2_d <= 22'h0;
tdd_tx_dp_on_2_d <= 22'h0;
tdd_tx_dp_off_2_d <= 22'h0;
end else begin
//if((tdd_update_regs == 1'b1) && (tdd_counter_state == OFF)) begin
tdd_secondary_d <= tdd_secondary;
tdd_start_d <= tdd_start;
tdd_frame_length_d <= tdd_frame_length;
tdd_counter_init_d <= tdd_counter_init;
tdd_burst_en_d <= tdd_burst_en;
tdd_burst_count_d <= tdd_burst_count;
tdd_infinite_burst_d <= tdd_infinite_burst;
tdd_tx_dp_delay_d <= tdd_tx_dp_delay;
tdd_vco_rx_on_1_d <= tdd_vco_rx_on_1;
tdd_vco_rx_off_1_d <= tdd_vco_rx_off_1;
tdd_vco_tx_on_1_d <= tdd_vco_tx_on_1;
tdd_vco_tx_off_1_d <= tdd_vco_tx_off_1;
tdd_rx_on_1_d <= tdd_rx_on_1;
tdd_rx_off_1_d <= tdd_rx_off_1;
tdd_tx_on_1_d <= tdd_tx_on_1;
tdd_tx_off_1_d <= tdd_tx_off_1;
tdd_tx_dp_on_1_d <= tdd_tx_dp_on_1;
tdd_tx_dp_off_1_d <= tdd_tx_dp_off_1;
tdd_vco_rx_on_2_d <= tdd_vco_rx_on_2;
tdd_vco_rx_off_2_d <= tdd_vco_rx_off_2;
tdd_vco_tx_on_2_d <= tdd_vco_tx_on_2;
tdd_vco_tx_off_2_d <= tdd_vco_tx_off_2;
tdd_rx_on_2_d <= tdd_rx_on_2;
tdd_rx_off_2_d <= tdd_rx_off_2;
tdd_tx_on_2_d <= tdd_tx_on_2;
tdd_tx_off_2_d <= tdd_tx_off_2;
tdd_tx_dp_on_2_d <= tdd_tx_dp_on_2;
tdd_tx_dp_off_2_d <= tdd_tx_dp_off_2;
//end
end
end
// ***************************************************************************
// tdd counter (state machine)
// ***************************************************************************
always @(posedge clk) begin
// sync reset
if (rst == 1'b1) begin
tdd_counter <= 24'h0;
tdd_counter_state <= OFF;
tdd_burst_state <= OFF;
end else begin
// counter reset
if (tdd_counter_reset == 1'b1) begin
tdd_counter_state <= OFF;
tdd_burst_state <= OFF;
end else
// start counter, the start pulse should have one clock cycle
// NOTE: a start pulse during a transaction will reinitialize the counter
if (tdd_start == 1'b1) begin
tdd_counter <= tdd_counter_init_d;
tdd_burst_counter <= tdd_burst_count_d;
tdd_counter_state <= ON;
if ((tdd_burst_en_d == 1) &&
((tdd_burst_count_d > 0) || (tdd_infinite_burst_d == 1))) begin
tdd_burst_state <= ON;
end else begin
tdd_burst_state <= OFF;
end
end else
// free running counter
if (tdd_counter_state == ON) begin
if (tdd_counter == tdd_frame_length_d) begin
tdd_counter <= 22'h0;
if ((tdd_burst_state == ON) && ((tdd_burst_counter > 0) || (tdd_infinite_burst_d == 1))) begin
tdd_burst_counter <= tdd_burst_counter - 1;
tdd_counter_state <= ON;
end else begin
tdd_burst_counter <= 6'h0;
tdd_counter_state <= OFF;
tdd_burst_state <= OFF;
end
end else begin
tdd_counter <= tdd_counter + 1;
end
end
end
end
// ***************************************************************************
// generate control signals
// ***************************************************************************
// start/stop rx vco
always @(posedge clk) begin
if(tdd_counter_state == ON) begin
if (tdd_counter == (tdd_vco_rx_on_1_d - 1)) begin
tdd_rx_vco_en <= 1'b1;
end else if ((tdd_secondary_d == 1'b1) && (tdd_counter == (tdd_vco_rx_on_2_d - 1))) begin
tdd_rx_vco_en <= 1'b1;
end else if (tdd_counter == (tdd_vco_rx_off_1_d - 1)) begin
tdd_rx_vco_en <= 1'b0;
end else if ((tdd_secondary_d == 1'b1) && (tdd_counter == (tdd_vco_rx_off_2_d - 1))) begin
tdd_rx_vco_en <= 1'b0;
end
end else begin
tdd_rx_vco_en <= 1'b0;
end
end
// start/stop tx vco
always @(posedge clk) begin
if(tdd_counter_state == ON) begin
if (tdd_counter == (tdd_vco_tx_on_1_d - 1)) begin
tdd_tx_vco_en <= 1'b1;
end else if ((tdd_secondary_d == 1'b1) && (tdd_counter == (tdd_vco_tx_on_2_d - 1))) begin
tdd_tx_vco_en <= 1'b1;
end else if (tdd_counter == (tdd_vco_tx_off_1_d - 1)) begin
tdd_tx_vco_en <= 1'b0;
end else if ((tdd_secondary_d == 1'b1) && (tdd_counter == (tdd_vco_tx_off_2_d - 1))) begin
tdd_tx_vco_en <= 1'b0;
end
end else begin
tdd_tx_vco_en <= 1'b0;
end
end
// start/stop rx rf path
always @(posedge clk) begin
if(tdd_counter_state == ON) begin
if (tdd_counter == (tdd_rx_on_1_d - 1)) begin
tdd_rx_rf_en <= 1'b1;
end else if ((tdd_secondary_d == 1'b1) && (tdd_counter == (tdd_rx_on_2_d - 1))) begin
tdd_rx_rf_en <= 1'b1;
end else if (tdd_counter == (tdd_rx_off_1_d - 1)) begin
tdd_rx_rf_en <= 1'b0;
end else if ((tdd_secondary_d == 1'b1) && (tdd_counter == (tdd_rx_off_2_d - 1))) begin
tdd_rx_rf_en <= 1'b0;
end
end else begin
tdd_rx_rf_en <= 1'b0;
end
end
// start/stop tx rf path
always @(posedge clk) begin
if(tdd_counter_state == ON) begin
if (tdd_counter == (tdd_tx_on_1_d - 1)) begin
tdd_tx_rf_en <= 1'b1;
end else if ((tdd_secondary_d == 1'b1) && (tdd_counter == (tdd_tx_on_2_d - 1))) begin
tdd_tx_rf_en <= 1'b1;
end else if (tdd_counter == (tdd_tx_off_1_d - 1)) begin
tdd_tx_rf_en <= 1'b0;
end else if ((tdd_secondary_d == 1'b1) && (tdd_counter == (tdd_tx_off_2_d - 1))) begin
tdd_tx_rf_en <= 1'b0;
end
end else begin
tdd_tx_rf_en <= 1'b0;
end
end
// start/stop tx data path
always @(posedge clk) begin
if(tdd_counter_state == ON) begin
if (tdd_counter == (tdd_tx_dp_on_1_d - tdd_tx_dp_delay_d)) begin
tdd_tx_dp_en <= 1'b1;
end else if ((tdd_secondary_d == 1'b1) && (tdd_counter == (tdd_tx_dp_on_2_d - tdd_tx_dp_delay_d))) begin
tdd_tx_dp_en <= 1'b1;
end else if (tdd_counter == (tdd_tx_dp_off_1_d - tdd_tx_dp_delay_d)) begin
tdd_tx_dp_en <= 1'b0;
end else if ((tdd_secondary_d == 1'b1) && (tdd_counter == (tdd_tx_dp_off_2_d - tdd_tx_dp_delay_d))) begin
tdd_tx_dp_en <= 1'b0;
end
end else begin
tdd_tx_dp_en <= 1'b0;
end
end
endmodule

497
library/common/up_tdd_cntrl.v Normal file
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@ -0,0 +1,497 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_tdd_cntrl (
clk,
//rf tdd interface control
tdd_enable,
tdd_start,
tdd_rst,
tdd_counter_reset,
tdd_update_regs,
tdd_secondary,
tdd_burst_en,
tdd_burst_count,
tdd_infinite_burst,
tdd_counter_init,
tdd_frame_length,
tdd_tx_dp_delay,
tdd_vco_rx_on_1,
tdd_vco_rx_off_1,
tdd_vco_tx_on_1,
tdd_vco_tx_off_1,
tdd_rx_on_1,
tdd_rx_off_1,
tdd_tx_on_1,
tdd_tx_off_1,
tdd_tx_dp_on_1,
tdd_tx_dp_off_1,
tdd_vco_rx_on_2,
tdd_vco_rx_off_2,
tdd_vco_tx_on_2,
tdd_vco_tx_off_2,
tdd_rx_on_2,
tdd_rx_off_2,
tdd_tx_on_2,
tdd_tx_off_2,
tdd_tx_dp_on_2,
tdd_tx_dp_off_2,
tdd_status,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00010001;
parameter PCORE_ID = 0;
input clk;
output tdd_enable;
output tdd_start;
output tdd_rst;
output tdd_update_regs;
output tdd_counter_reset;
output tdd_secondary;
output [21:0] tdd_counter_init;
output [21:0] tdd_frame_length;
output tdd_burst_en;
output [ 5:0] tdd_burst_count;
output tdd_infinite_burst;
output [ 7:0] tdd_tx_dp_delay;
output [21:0] tdd_vco_rx_on_1;
output [21:0] tdd_vco_rx_off_1;
output [21:0] tdd_vco_tx_on_1;
output [21:0] tdd_vco_tx_off_1;
output [21:0] tdd_rx_on_1;
output [21:0] tdd_rx_off_1;
output [21:0] tdd_tx_on_1;
output [21:0] tdd_tx_off_1;
output [21:0] tdd_tx_dp_on_1;
output [21:0] tdd_tx_dp_off_1;
output [21:0] tdd_vco_rx_on_2;
output [21:0] tdd_vco_rx_off_2;
output [21:0] tdd_vco_tx_on_2;
output [21:0] tdd_vco_tx_off_2;
output [21:0] tdd_rx_on_2;
output [21:0] tdd_rx_off_2;
output [21:0] tdd_tx_on_2;
output [21:0] tdd_tx_off_2;
output [21:0] tdd_tx_dp_on_2;
output [21:0] tdd_tx_dp_off_2;
input [ 7:0] tdd_status;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_wack = 1'h0;
reg [31:0] up_scratch = 32'h0;
reg up_resetn = 1'h0;
reg up_rack = 1'h0;
reg [31:0] up_rdata = 32'h0;
reg up_tdd_enable = 1'h0;
reg up_tdd_start = 1'h0;
reg up_tdd_update_regs = 1'h0;
reg up_tdd_counter_reset = 1'h0;
reg up_tdd_secondary = 1'h0;
reg [21:0] up_tdd_counter_init = 22'h0;
reg [21:0] up_tdd_frame_length = 22'h0;
reg up_tdd_burst_en = 1'h0;
reg [ 5:0] up_tdd_burst_count = 6'h0;
reg up_tdd_infinite_burst = 1'h0;
reg [ 7:0] up_tdd_tx_dp_delay = 8'h0;
reg [21:0] up_tdd_vco_rx2tx_1 = 22'h0;
reg [21:0] up_tdd_vco_tx2rx_1 = 22'h0;
reg [21:0] up_tdd_vco_rx_on_1 = 22'h0;
reg [21:0] up_tdd_vco_rx_off_1 = 22'h0;
reg [21:0] up_tdd_vco_tx_on_1 = 22'h0;
reg [21:0] up_tdd_vco_tx_off_1 = 22'h0;
reg [21:0] up_tdd_rx_on_1 = 22'h0;
reg [21:0] up_tdd_rx_off_1 = 22'h0;
reg [21:0] up_tdd_tx_on_1 = 22'h0;
reg [21:0] up_tdd_tx_off_1 = 22'h0;
reg [21:0] up_tdd_tx_dp_on_1 = 22'h0;
reg [21:0] up_tdd_tx_dp_off_1 = 22'h0;
reg [21:0] up_tdd_vco_rx_on_2 = 22'h0;
reg [21:0] up_tdd_vco_rx_off_2 = 22'h0;
reg [21:0] up_tdd_vco_tx_on_2 = 22'h0;
reg [21:0] up_tdd_vco_tx_off_2 = 22'h0;
reg [21:0] up_tdd_rx_on_2 = 22'h0;
reg [21:0] up_tdd_rx_off_2 = 22'h0;
reg [21:0] up_tdd_tx_on_2 = 22'h0;
reg [21:0] up_tdd_tx_off_2 = 22'h0;
reg [21:0] up_tdd_tx_dp_on_2 = 22'h0;
reg [21:0] up_tdd_tx_dp_off_2 = 22'h0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire up_preset_s;
wire tdd_rst;
wire up_cntrl_xfer_done;
wire [ 7:0] up_tdd_status_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h20) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h20) ? up_rreq : 1'b0;
assign up_preset_s = ~up_resetn;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 1'h0;
up_scratch <= 32'h0;
up_resetn <= 1'h0;
up_tdd_start <= 1'h0;
up_tdd_update_regs <= 1'h0;
up_tdd_counter_reset <= 1'h0;
up_tdd_enable <= 1'h0;
up_tdd_secondary <= 1'h0;
up_tdd_counter_init <= 22'h0;
up_tdd_frame_length <= 22'h0;
up_tdd_burst_en <= 1'h0;
up_tdd_burst_count <= 6'h0;
up_tdd_infinite_burst <= 1'h0;
up_tdd_vco_rx_on_1 <= 22'h0;
up_tdd_vco_rx_off_1 <= 22'h0;
up_tdd_vco_tx_on_1 <= 22'h0;
up_tdd_vco_tx_off_1 <= 22'h0;
up_tdd_rx_on_1 <= 22'h0;
up_tdd_rx_off_1 <= 22'h0;
up_tdd_tx_on_1 <= 22'h0;
up_tdd_tx_off_1 <= 22'h0;
up_tdd_tx_dp_on_1 <= 22'h0;
up_tdd_vco_rx_on_2 <= 22'h0;
up_tdd_vco_rx_off_2 <= 22'h0;
up_tdd_vco_tx_on_2 <= 22'h0;
up_tdd_vco_tx_off_2 <= 22'h0;
up_tdd_rx_on_2 <= 22'h0;
up_tdd_rx_off_2 <= 22'h0;
up_tdd_tx_on_2 <= 22'h0;
up_tdd_tx_off_2 <= 22'h0;
up_tdd_tx_dp_on_2 <= 22'h0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_resetn <= up_wdata[0];
end
if (up_tdd_update_regs == 1'b1) begin
if (up_cntrl_xfer_done == 1) begin
up_tdd_update_regs <= 1'h0;
end
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_tdd_update_regs <= up_wdata[3];
up_tdd_counter_reset <= up_wdata[2];
up_tdd_enable <= up_wdata[0];
end
if (up_tdd_start == 1) begin
if (up_cntrl_xfer_done == 1) begin
up_tdd_start <= 1'h0;
end
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_tdd_start <= up_wdata[1];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
up_tdd_burst_count <= up_wdata[21:16];
up_tdd_infinite_burst <= up_wdata[2];
up_tdd_burst_en <= up_wdata[1];
up_tdd_secondary <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
up_tdd_counter_init <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
up_tdd_frame_length <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h15)) begin
up_tdd_tx_dp_delay <= up_wdata[ 7:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
up_tdd_vco_rx_on_1 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
up_tdd_vco_rx_off_1 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_tdd_vco_tx_on_1 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
up_tdd_vco_tx_off_1 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
up_tdd_rx_on_1 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h25)) begin
up_tdd_rx_off_1 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h26)) begin
up_tdd_tx_on_1 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h27)) begin
up_tdd_tx_off_1 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_tdd_tx_dp_on_1 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
up_tdd_tx_dp_off_1 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
up_tdd_vco_rx_on_2 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
up_tdd_vco_rx_off_2 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_tdd_vco_tx_on_2 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
up_tdd_vco_tx_off_2 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h32)) begin
up_tdd_rx_on_2 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h33)) begin
up_tdd_rx_off_2 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h34)) begin
up_tdd_tx_on_2 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h35)) begin
up_tdd_tx_off_2 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h36)) begin
up_tdd_tx_dp_on_2 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h37)) begin
up_tdd_tx_dp_off_2 <= up_wdata[21:0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 1'b0;
up_rdata <= 1'b0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= PCORE_ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {31'h0, up_resetn};
8'h11: up_rdata <= {28'h0, up_tdd_update_regs, up_tdd_counter_reset, up_tdd_start, up_tdd_enable};
8'h12: up_rdata <= {10'h0, up_tdd_burst_count, 13'h0, up_tdd_infinite_burst, up_tdd_burst_en, up_tdd_secondary};
8'h13: up_rdata <= {10'h0, up_tdd_counter_init};
8'h14: up_rdata <= {10'h0, up_tdd_frame_length};
8'h15: up_rdata <= {24'h0, up_tdd_tx_dp_delay};
8'h1A: up_rdata <= {24'h0, up_tdd_status_s};
8'h20: up_rdata <= {10'h0, up_tdd_vco_rx_on_1};
8'h21: up_rdata <= {10'h0, up_tdd_vco_rx_off_1};
8'h22: up_rdata <= {10'h0, up_tdd_vco_tx_on_1};
8'h23: up_rdata <= {10'h0, up_tdd_vco_tx_off_1};
8'h24: up_rdata <= {10'h0, up_tdd_rx_on_1};
8'h25: up_rdata <= {10'h0, up_tdd_rx_off_1};
8'h26: up_rdata <= {10'h0, up_tdd_tx_on_1};
8'h27: up_rdata <= {10'h0, up_tdd_tx_off_1};
8'h28: up_rdata <= {10'h0, up_tdd_tx_dp_on_1};
8'h29: up_rdata <= {10'h0, up_tdd_tx_dp_off_1};
8'h30: up_rdata <= {10'h0, up_tdd_vco_rx_on_2};
8'h31: up_rdata <= {10'h0, up_tdd_vco_rx_off_2};
8'h32: up_rdata <= {10'h0, up_tdd_vco_tx_on_2};
8'h33: up_rdata <= {10'h0, up_tdd_vco_tx_off_2};
8'h34: up_rdata <= {10'h0, up_tdd_rx_on_2};
8'h35: up_rdata <= {10'h0, up_tdd_rx_off_2};
8'h36: up_rdata <= {10'h0, up_tdd_tx_on_2};
8'h37: up_rdata <= {10'h0, up_tdd_tx_off_2};
8'h38: up_rdata <= {10'h0, up_tdd_tx_dp_on_2};
8'h39: up_rdata <= {10'h0, up_tdd_tx_dp_off_2};
default: up_rdata <= 32'h0;
endcase
end
end
end
// resets
ad_rst i_rf_rst_reg (
.preset(up_preset_s),
.clk(clk),
.rst(tdd_rst)
);
// rf tdd control signal CDC
up_xfer_cntrl #(.DATA_WIDTH(13)) i_tdd_control (
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_cntrl({up_tdd_enable,
up_tdd_counter_reset,
up_tdd_update_regs,
up_tdd_secondary,
up_tdd_start,
up_tdd_burst_en,
up_tdd_burst_count,
up_tdd_infinite_burst
}),
.up_xfer_done(up_cntrl_xfer_done),
.d_rst(tdd_rst),
.d_clk(clk),
.d_data_cntrl({tdd_enable,
tdd_counter_reset,
tdd_update_regs,
tdd_secondary,
tdd_start,
tdd_burst_en,
tdd_burst_count,
tdd_infinite_burst
}));
up_xfer_cntrl #(.DATA_WIDTH(492)) i_tdd_counter_values (
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_cntrl({up_tdd_counter_init,
up_tdd_frame_length,
up_tdd_tx_dp_delay,
up_tdd_vco_rx_on_1,
up_tdd_vco_rx_off_1,
up_tdd_vco_tx_on_1,
up_tdd_vco_tx_off_1,
up_tdd_rx_on_1,
up_tdd_rx_off_1,
up_tdd_tx_on_1,
up_tdd_tx_off_1,
up_tdd_tx_dp_on_1,
up_tdd_tx_dp_off_1,
up_tdd_vco_rx_on_2,
up_tdd_vco_rx_off_2,
up_tdd_vco_tx_on_2,
up_tdd_vco_tx_off_2,
up_tdd_rx_on_2,
up_tdd_rx_off_2,
up_tdd_tx_on_2,
up_tdd_tx_off_2,
up_tdd_tx_dp_on_2,
up_tdd_tx_dp_off_2
}),
.up_xfer_done(),
.d_rst(tdd_rst),
.d_clk(clk),
.d_data_cntrl({tdd_counter_init,
tdd_frame_length,
tdd_tx_dp_delay,
tdd_vco_rx_on_1,
tdd_vco_rx_off_1,
tdd_vco_tx_on_1,
tdd_vco_tx_off_1,
tdd_rx_on_1,
tdd_rx_off_1,
tdd_tx_on_1,
tdd_tx_off_1,
tdd_tx_dp_on_1,
tdd_tx_dp_off_1,
tdd_vco_rx_on_2,
tdd_vco_rx_off_2,
tdd_vco_tx_on_2,
tdd_vco_tx_off_2,
tdd_rx_on_2,
tdd_rx_off_2,
tdd_tx_on_2,
tdd_tx_off_2,
tdd_tx_dp_on_2,
tdd_tx_dp_off_2
}));
up_xfer_status #(.DATA_WIDTH(8)) i_tdd_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status (up_tdd_status_s),
.d_rst (tdd_rst),
.d_clk (clk),
.d_data_status (tdd_status));
endmodule
// ***************************************************************************
// ***************************************************************************