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adrv9371: Increase FCLK2 to 200MHz to support max sampling rates 

This fixes an issue seen when using 307.2 MSPS on the Observation RX.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
main
Michael Hennerich 2018-01-09 15:20:06 +01:00
parent 3e3955ce91
commit 2e59a70cdd
3 changed files with 3 additions and 3 deletions
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2
projects/adrv9371x/kcu105/system_bd.tcl
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@ -8,7 +8,7 @@ source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl
source $ad_hdl_dir/projects/common/kcu105/kcu105_system_mig.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ 150
ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ 200
source ../common/adrv9371x_bd.tcl

2
projects/adrv9371x/zc706/system_bd.tcl
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@ -7,7 +7,7 @@ set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl
ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 150
ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 200
source ../common/adrv9371x_bd.tcl

2
projects/adrv9371x/zcu102/system_bd.tcl
View File

@ -9,7 +9,7 @@ source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL2_ENABLE 1
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL}
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ 150
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ 200
source ../common/adrv9371x_bd.tcl