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motcon2_fmc: Update project to use the latest util_gmii_to_rgmii

main
Adrian Costina 2015-06-16 17:43:10 +03:00
parent d137811952
commit 2e46bda916
3 changed files with 15 additions and 54 deletions
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7
projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
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@ -184,10 +184,12 @@
#ethernet gmii to rgmii converters #ethernet gmii to rgmii converters
# phy 1 # phy 1
set gmii_to_rgmii_eth1 [ create_bd_cell -type ip -vlnv analog.com:user:util_gmii_to_rgmii:1.0 gmii_to_rgmii_eth1 ] set gmii_to_rgmii_eth1 [ create_bd_cell -type ip -vlnv analog.com:user:util_gmii_to_rgmii:1.0 gmii_to_rgmii_eth1 ]
set_property -dict [list CONFIG.PHY_AD {"00000"}] [get_bd_cells gmii_to_rgmii_eth1] set_property -dict [list CONFIG.PHY_AD {"00000"}] $gmii_to_rgmii_eth1
set_property -dict [list CONFIG.IODELAY_CTRL {1}] $gmii_to_rgmii_eth1
# phy 2 # phy 2
set gmii_to_rgmii_eth2 [ create_bd_cell -type ip -vlnv analog.com:user:util_gmii_to_rgmii:1.0 gmii_to_rgmii_eth2 ] set gmii_to_rgmii_eth2 [ create_bd_cell -type ip -vlnv analog.com:user:util_gmii_to_rgmii:1.0 gmii_to_rgmii_eth2 ]
set_property -dict [list CONFIG.PHY_AD {"00001"}] [get_bd_cells gmii_to_rgmii_eth2] set_property -dict [list CONFIG.PHY_AD {"00001"}] $gmii_to_rgmii_eth2
# iic # iic
set iic_ee2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 iic_ee2 ] set iic_ee2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 iic_ee2 ]
@ -488,6 +490,7 @@
ad_connect sys_ps7/ENET0_MDIO_T eth_mdio_t ad_connect sys_ps7/ENET0_MDIO_T eth_mdio_t
ad_connect sys_ps7/ENET0_MDIO_I eth_mdio_i ad_connect sys_ps7/ENET0_MDIO_I eth_mdio_i
# phy 1 # phy 1
ad_connect sys_200m_clk gmii_to_rgmii_eth1/idelayctrl_clk
ad_connect gmii_to_rgmii_eth1/gmii sys_ps7/GMII_ETHERNET_0 ad_connect gmii_to_rgmii_eth1/gmii sys_ps7/GMII_ETHERNET_0
ad_connect eth1_rgmii gmii_to_rgmii_eth1/rgmii ad_connect eth1_rgmii gmii_to_rgmii_eth1/rgmii
ad_connect gmii_to_rgmii_eth1/reset sys_rstgen/peripheral_reset ad_connect gmii_to_rgmii_eth1/reset sys_rstgen/peripheral_reset

18
projects/motcon2_fmc/zed/system_constr.xdc
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@ -139,18 +139,18 @@ set_clock_groups -asynchronous \
# Ethernet common # Ethernet common
set_property IODELAY_GROUP eth_idelay_grp [get_cells dlyctrl] #set_property IODELAY_GROUP eth_idelay_grp [get_cells dlyctrl]
# Ethernet 1 # Ethernet 1
#IDELAY #IDELAY
set_property IDELAY_VALUE 16 [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] #set_property IDELAY_VALUE 16 [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl]
set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth1*/*delay_rgmii_rd*}] #set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth1*/*delay_rgmii_rd*}]
set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] #set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl]
set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth1*/*delay_rgmii_rd*}] #set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth1*/*delay_rgmii_rd*}]
# Ethernet 2 # Ethernet 2
#IDELAY #IDELAY
set_property IDELAY_VALUE 16 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] #set_property IDELAY_VALUE 16 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl]
set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rd*}] #set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rd*}]
set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] #set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl]
set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth2*/*delay_rgmii_rd*}] #set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth2*/*delay_rgmii_rd*}]

42
projects/motcon2_fmc/zed/system_top.v
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@ -273,15 +273,10 @@ module system_top (
wire [ 1:0] iic_mux_sda_o_s; wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s; wire iic_mux_sda_t_s;
wire refclk;
wire refclk_rst;
wire eth_mdio_o; wire eth_mdio_o;
wire eth_mdio_i; wire eth_mdio_i;
wire eth_mdio_t; wire eth_mdio_t;
reg idelayctrl_reset;
reg [ 3:0] idelay_reset_cnt;
// assignments // assignments
@ -326,40 +321,6 @@ module system_top (
.dio_o(eth_mdio_i), .dio_o(eth_mdio_i),
.dio_p(eth_mdio_p)); .dio_p(eth_mdio_p));
always @(posedge refclk) begin
if (refclk_rst == 1'b1) begin
idelay_reset_cnt <= 4'h0;
idelayctrl_reset <= 1'b1;
end else begin
idelayctrl_reset <= 1'b1;
case (idelay_reset_cnt)
4'h0: idelay_reset_cnt <= 4'h1;
4'h1: idelay_reset_cnt <= 4'h2;
4'h2: idelay_reset_cnt <= 4'h3;
4'h3: idelay_reset_cnt <= 4'h4;
4'h4: idelay_reset_cnt <= 4'h5;
4'h5: idelay_reset_cnt <= 4'h6;
4'h6: idelay_reset_cnt <= 4'h7;
4'h7: idelay_reset_cnt <= 4'h8;
4'h8: idelay_reset_cnt <= 4'h9;
4'h9: idelay_reset_cnt <= 4'ha;
4'ha: idelay_reset_cnt <= 4'hb;
4'hb: idelay_reset_cnt <= 4'hc;
4'hc: idelay_reset_cnt <= 4'hd;
4'hd: idelay_reset_cnt <= 4'he;
default: begin
idelay_reset_cnt <= 4'he;
idelayctrl_reset <= 1'b0;
end
endcase
end
end
IDELAYCTRL dlyctrl (
.RDY(),
.REFCLK(refclk),
.RST(idelayctrl_reset));
system_wrapper i_system_wrapper ( system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr), .ddr_addr (ddr_addr),
.ddr_ba (ddr_ba), .ddr_ba (ddr_ba),
@ -458,7 +419,6 @@ module system_top (
.ps_intr_02 (1'b0), .ps_intr_02 (1'b0),
.ps_intr_03 (1'b0), .ps_intr_03 (1'b0),
.ps_intr_04 (1'b0), .ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.iic_ee2_scl_io(iic_ee2_scl_io), .iic_ee2_scl_io(iic_ee2_scl_io),
.iic_ee2_sda_io(iic_ee2_sda_io), .iic_ee2_sda_io(iic_ee2_sda_io),
.spi0_clk_i (1'b0), .spi0_clk_i (1'b0),
@ -479,8 +439,6 @@ module system_top (
.spi1_sdi_i (1'b0), .spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0), .spi1_sdo_i (1'b0),
.spi1_sdo_o (), .spi1_sdo_o (),
.refclk(refclk),
.refclk_rst(refclk_rst),
.otg_vbusoc (otg_vbusoc), .otg_vbusoc (otg_vbusoc),
.spdif (spdif)); .spdif (spdif));