axi_logic_analyzer: Auto sync to ADC path
The number of delay taps in the LA data path can be controlled manually, from the regmap or automatically, according to the axi_adc_decimate's rate. Moreover, because the rate is configure by software, and the time of initialization, is different for the ADC path and LA path. There is an uncertainty of plus/minus one sample between the two. Because ADC and LA paths share the same clock we can easily synchronize the two paths. We can't use reset, because the rate generation mechanism is different between the two. So the ADC path is used as master valid generator and we can use it to drive the LA path. The synchronization is done by setting the rate source bit. This mechanism can only be used if the desired rate for both path is equal, including oversampling fom ADC decimation.main
AndreiGrozav
AndreiGrozav
parent
d2b1164567
commit
2e0ba5bffd
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@ -35,11 +35,7 @@
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`timescale 1ns/100ps
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module axi_logic_analyzer #(
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// add sample delays on LA to compensate for adc path delay
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parameter ADC_PATH_DELAY = 19) (
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module axi_logic_analyzer (
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// interface
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@ -58,6 +54,9 @@ module axi_logic_analyzer #(
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input dac_valid,
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output reg dac_read,
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input [ 2:0] external_rate,
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input external_valid,
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input external_decimation_en,
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input trigger_in,
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output trigger_out,
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output trigger_out_adc,
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@ -128,6 +127,40 @@ module axi_logic_analyzer #(
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reg [15:0] adc_data_mn = 'd0;
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reg [31:0] trigger_holdoff_counter = 32'd0;
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reg [ 4:0] adc_data_delay = 5'd0;
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reg [15:0] data_m_0;
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reg [15:0] data_m_1;
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reg [15:0] data_m_2;
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reg [15:0] data_m_3;
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reg [15:0] data_m_4;
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reg [15:0] data_m_5;
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reg [15:0] data_m_6;
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reg [15:0] data_m_7;
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reg [15:0] data_m_8;
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reg [15:0] data_m_9;
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reg [15:0] data_m_10;
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reg [15:0] data_m_11;
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reg [15:0] data_m_12;
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reg [15:0] data_m_13;
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reg [15:0] data_m_14;
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reg [15:0] data_m_15;
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reg [15:0] data_m_16;
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reg [15:0] data_m_17;
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reg [15:0] data_m_18;
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reg [15:0] data_m_19;
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reg [15:0] data_m_20;
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reg [15:0] data_m_21;
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reg [15:0] data_m_22;
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reg [15:0] data_m_23;
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reg [15:0] data_m_24;
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reg [15:0] data_m_25;
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reg [15:0] data_m_26;
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reg [15:0] data_m_27;
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reg [15:0] data_m_28;
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reg [15:0] data_m_29;
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reg [15:0] data_m_30;
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reg [15:0] data_m_31;
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// internal signals
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@ -181,6 +214,11 @@ module axi_logic_analyzer #(
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wire streaming;
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wire [ 4:0] in_data_delay;
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wire [ 4:0] up_data_delay;
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wire master_delay_ctrl;
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wire [ 9:0] data_delay_control;
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genvar i;
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// signal name changes
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@ -189,9 +227,10 @@ module axi_logic_analyzer #(
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assign up_rstn = s_axi_aresetn;
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assign trigger_out = trigger_delay == 32'h0 ? trigger_out_holdoff | streaming_on : trigger_out_delayed | streaming_on;
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assign trigger_out_delayed = delay_counter == 32'h0 ? 1 : 0;
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always @(posedge clk_out) begin
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always @(posedge clk_out) begin
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if (trigger_delay == 0) begin
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if (streaming == 1'b1 && sample_valid_la == 1'b1 && trigger_out_holdoff == 1'b1) begin
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streaming_on <= 1'b1;
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@ -208,7 +247,7 @@ module axi_logic_analyzer #(
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end
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always @(posedge clk_out) begin
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always @(posedge clk_out) begin
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if (sample_valid_la == 1'b1 && trigger_out_holdoff == 1'b1) begin
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up_triggered_set <= 1'b1;
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end else if (up_triggered_reset == 1'b1) begin
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@ -254,41 +293,92 @@ module axi_logic_analyzer #(
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// - synchronization
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// - compensate for m2k adc path delay
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// - transfer data at clock frequency if capture is enabled
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genvar j;
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generate
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reg [15:0] data_m[ADC_PATH_DELAY-2:0];
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always @(posedge clk_out) begin
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if (sample_valid_la == 1'b1) begin
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data_m[0] <= data_i;
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end
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always @(posedge clk_out) begin
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data_m_0 <= data_i;
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data_m_1 <= data_m_0;
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data_m_2 <= data_m_1;
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data_m_3 <= data_m_2;
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data_m_4 <= data_m_3;
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data_m_5 <= data_m_4;
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data_m_6 <= data_m_5;
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data_m_7 <= data_m_6;
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data_m_8 <= data_m_7;
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data_m_9 <= data_m_8;
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data_m_10 <= data_m_9;
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data_m_11 <= data_m_10;
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data_m_12 <= data_m_11;
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data_m_13 <= data_m_12;
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data_m_14 <= data_m_13;
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data_m_15 <= data_m_14;
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data_m_16 <= data_m_15;
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if (sample_valid_la == 1'b1) begin
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data_m_17 <= data_m_16;
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data_m_18 <= data_m_17;
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data_m_19 <= data_m_18;
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data_m_20 <= data_m_19;
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data_m_21 <= data_m_20;
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data_m_22 <= data_m_21;
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data_m_23 <= data_m_22;
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data_m_24 <= data_m_23;
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data_m_25 <= data_m_24;
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data_m_26 <= data_m_25;
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data_m_27 <= data_m_26;
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data_m_28 <= data_m_27;
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data_m_29 <= data_m_28;
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data_m_30 <= data_m_29;
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data_m_31 <= data_m_30;
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end
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end
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for (j = 0; j < ADC_PATH_DELAY - 2; j = j + 1) begin
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always @(posedge clk_out) begin
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if (sample_valid_la == 1'b1) begin
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data_m[j+1] <= data_m[j];
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end
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end
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end
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// adc path 'rate delay' given by axi_adc_decimate
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always @(posedge clk_out) begin
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case (external_rate)
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3'd0: adc_data_delay <= 5'd1; // 100MSPS
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3'd1: adc_data_delay <= 5'd3; // 10MSPS
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default: adc_data_delay <= 5'd1; // <= 1MSPS
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endcase
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end
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always @(posedge clk_out) begin
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if (sample_valid_la == 1'b1) begin
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adc_data_mn <= data_m[ADC_PATH_DELAY-2];
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adc_data <= adc_data_mn;
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end
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assign up_data_delay = data_delay_control[4:0];
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assign rate_gen_select = data_delay_control[8];
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// select if the delay taps number is chosen by the user or automatically
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assign master_delay_ctrl = data_delay_control[9];
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assign in_data_delay = master_delay_ctrl ? up_data_delay :
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external_decimation_en ? 5'd0 : adc_data_delay;
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always @(posedge clk_out) begin
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if (sample_valid_la == 1'b1) begin
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case (in_data_delay)
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5'd0: adc_data_mn <= data_m_16;
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5'd1: adc_data_mn <= data_m_17;
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5'd2: adc_data_mn <= data_m_18;
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5'd3: adc_data_mn <= data_m_19;
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5'd4: adc_data_mn <= data_m_20;
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5'd5: adc_data_mn <= data_m_21;
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5'd6: adc_data_mn <= data_m_22;
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5'd7: adc_data_mn <= data_m_23;
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5'd8: adc_data_mn <= data_m_24;
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5'd9: adc_data_mn <= data_m_25;
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5'd10: adc_data_mn <= data_m_26;
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5'd11: adc_data_mn <= data_m_27;
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5'd12: adc_data_mn <= data_m_28;
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5'd13: adc_data_mn <= data_m_29;
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5'd14: adc_data_mn <= data_m_30;
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5'd15: adc_data_mn <= data_m_31;
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default: adc_data_mn <= data_m_16;
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endcase
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adc_data <= adc_data_mn;
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end
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endgenerate
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end
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assign adc_valid = sample_valid_la;
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always @(posedge clk_out) begin
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trigger_m1 <= trigger_i;
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end
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// downsampler logic analyzer
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always @(posedge clk_out) begin
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@ -296,7 +386,10 @@ module axi_logic_analyzer #(
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sample_valid_la <= 1'b0;
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downsampler_counter_la <= 32'h0;
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end else begin
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if (downsampler_counter_la < divider_counter_la ) begin
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if (rate_gen_select) begin
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downsampler_counter_la <= 32'h0;
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sample_valid_la <= external_valid;
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end else if (downsampler_counter_la < divider_counter_la ) begin
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downsampler_counter_la <= downsampler_counter_la + 1;
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sample_valid_la <= 1'b0;
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end else begin
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@ -404,7 +497,6 @@ module axi_logic_analyzer #(
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end
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end
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axi_logic_analyzer_trigger i_trigger (
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.clk (clk_out),
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.reset (reset),
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@ -446,11 +538,10 @@ module axi_logic_analyzer #(
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.overwrite_data (overwrite_data),
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.input_data (adc_data_mn),
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.od_pp_n (od_pp_n),
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.triggered (up_triggered),
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.pg_trigger_config (pg_trigger_config),
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.streaming(streaming),
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.data_delay_control (data_delay_control),
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// bus interface
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@ -1,7 +1,12 @@
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set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_d*}]
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set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_reset_d*}]
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set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *data_m*}]
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set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_sync_ack_m*}]
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set_false_path -to [get_pins BUFGMUX_CTRL_inst/S*]
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set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_d1* && IS_SEQUENTIAL}]
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set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_reset_d1* && IS_SEQUENTIAL}]
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set_false_path -to [get_cells -hier -filter {name =~ *data_m* && IS_SEQUENTIAL}]
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set_false_path -to [get_cells -hier -filter {name =~ *up_sync_ack_m* && IS_SEQUENTIAL}]
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@ -62,8 +62,8 @@ module axi_logic_analyzer_reg (
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output [19:0] pg_trigger_config,
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input triggered,
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output streaming,
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output [ 9:0] data_delay_control,
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// bus interface
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@ -102,6 +102,7 @@ module axi_logic_analyzer_reg (
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reg [19:0] up_pg_trigger_config = 20'h0;
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reg up_triggered = 0;
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reg up_streaming = 0;
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reg [ 9:0] up_data_delay_control = 10'd0;
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wire [15:0] up_input_data;
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@ -128,6 +129,7 @@ module axi_logic_analyzer_reg (
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up_streaming <= 1'd0;
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up_trigger_holdoff <= 32'h0;
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up_pg_trigger_config <= 20'd0;
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up_data_delay_control <= 10'h0;
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end else begin
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up_wack <= up_wreq;
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
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@ -192,6 +194,9 @@ module axi_logic_analyzer_reg (
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h15)) begin
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up_pg_trigger_config <= up_wdata[19:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h16)) begin
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up_data_delay_control <= up_wdata[9:0];
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end
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end
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end
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@ -227,6 +232,7 @@ module axi_logic_analyzer_reg (
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5'h13: up_rdata <= {31'h0,up_streaming};
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5'h14: up_rdata <= up_trigger_holdoff;
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5'h15: up_rdata <= {12'h0,up_pg_trigger_config};
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5'h16: up_rdata <= {22'h0,up_data_delay_control};
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default: up_rdata <= 0;
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endcase
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end else begin
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@ -237,7 +243,7 @@ module axi_logic_analyzer_reg (
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ad_rst i_core_rst_reg (.rst_async(~up_rstn), .clk(clk), .rstn(), .rst(reset));
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up_xfer_cntrl #(.DATA_WIDTH(343)) i_xfer_cntrl (
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up_xfer_cntrl #(.DATA_WIDTH(353)) i_xfer_cntrl (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_data_cntrl ({ up_streaming, // 1
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@ -257,7 +263,8 @@ module axi_logic_analyzer_reg (
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up_io_selection, // 16
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up_pg_trigger_config, // 20
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up_divider_counter_pg, // 32
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up_divider_counter_la}), // 32
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up_divider_counter_la, // 32
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up_data_delay_control}), // 10
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.up_xfer_done (),
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.d_rst (1'b0),
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@ -279,7 +286,8 @@ module axi_logic_analyzer_reg (
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io_selection, // 16
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pg_trigger_config, // 20
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divider_counter_pg, // 32
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divider_counter_la})); // 32
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divider_counter_la, // 32
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data_delay_control})); // 10
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up_xfer_status #(.DATA_WIDTH(16)) i_xfer_status (
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