From 2dfcb0c599dec78d0f582f6f5203ced071b43d10 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Tue, 7 Oct 2014 19:41:54 +0300
Subject: [PATCH] usdrx1: Initial commit for a5gt

axi_ad9671: added start of frame information to the altera core.
---
 library/axi_ad9671/axi_ad9671.v         |    4 +-
 library/axi_ad9671/axi_ad9671_alt.v     |    5 +-
 library/axi_ad9671/axi_ad9671_hw.tcl    |    5 +-
 library/common/altera/ad_jesd_align.v   |   14 +-
 projects/usdrx1/a5gt/system_bd.qsys     | 2786 +++++++++++++++++++++++
 projects/usdrx1/a5gt/system_constr.sdc  |   34 +
 projects/usdrx1/a5gt/system_project.tcl |  167 ++
 projects/usdrx1/a5gt/system_timing.tcl  |    3 +
 projects/usdrx1/a5gt/system_top.v       |  515 +++++
 9 files changed, 3523 insertions(+), 10 deletions(-)
 create mode 100644 projects/usdrx1/a5gt/system_bd.qsys
 create mode 100644 projects/usdrx1/a5gt/system_constr.sdc
 create mode 100644 projects/usdrx1/a5gt/system_project.tcl
 create mode 100644 projects/usdrx1/a5gt/system_timing.tcl
 create mode 100644 projects/usdrx1/a5gt/system_top.v

diff --git a/library/axi_ad9671/axi_ad9671.v b/library/axi_ad9671/axi_ad9671.v
index 9b1d923b2..8aab4a505 100644
--- a/library/axi_ad9671/axi_ad9671.v
+++ b/library/axi_ad9671/axi_ad9671.v
@@ -292,7 +292,9 @@ module axi_ad9671 (
 
   // up bus interface
 
-  up_axi i_up_axi (
+  up_axi #(
+    .PCORE_ADDR_WIDTH (14)
+  ) i_up_axi (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_axi_awvalid (s_axi_awvalid),
diff --git a/library/axi_ad9671/axi_ad9671_alt.v b/library/axi_ad9671/axi_ad9671_alt.v
index 87248100e..0d11acce8 100644
--- a/library/axi_ad9671/axi_ad9671_alt.v
+++ b/library/axi_ad9671/axi_ad9671_alt.v
@@ -46,6 +46,7 @@ module axi_ad9671_alt (
 
   rx_clk,
   rx_data,
+  rx_data_sof,
 
   // dma interface
 
@@ -106,6 +107,7 @@ module axi_ad9671_alt (
 
   input                               rx_clk;
   input   [(64*PCORE_4L_2L_N)+63:0]   rx_data;
+  input                               rx_data_sof;
 
   // dma interface
 
@@ -160,7 +162,7 @@ module axi_ad9671_alt (
 
   assign s_axi_bid = s_axi_awid;
   assign s_axi_rid = s_axi_arid;
-  assign s_axi_rlast = 1'd0;
+  assign s_axi_rlast = 1'd1;
 
   // ad9671 lite version
 
@@ -173,6 +175,7 @@ module axi_ad9671_alt (
   i_ad9671 (
     .rx_clk (rx_clk),
     .rx_data (rx_data),
+    .rx_data_sof (rx_data_sof),
     .adc_clk (adc_clk),
     .adc_valid (adc_valid),
     .adc_enable (adc_enable),
diff --git a/library/axi_ad9671/axi_ad9671_hw.tcl b/library/axi_ad9671/axi_ad9671_hw.tcl
index c4a24310a..b0209fe12 100644
--- a/library/axi_ad9671/axi_ad9671_hw.tcl
+++ b/library/axi_ad9671/axi_ad9671_hw.tcl
@@ -116,6 +116,7 @@ add_interface_port xcvr_clk rx_clk clk Input 1
 add_interface xcvr_data conduit end
 set_interface_property xcvr_data associatedClock xcvr_clk
 add_interface_port xcvr_data rx_data data Input 64*PCORE_4L_2L_N+64
+add_interface_port xcvr_data rx_data_sof data_sof Input 1
 
 # dma interface
 
@@ -124,8 +125,8 @@ add_interface_port adc_clock adc_clk clk Output 1
 
 add_interface adc_dma_if conduit end
 set_interface_property adc_dma_if associatedClock adc_clock
-add_interface_port adc_dma_if adc_valid valid Output 7
-add_interface_port adc_dma_if adc_enable enable Output 7
+add_interface_port adc_dma_if adc_valid valid Output 8
+add_interface_port adc_dma_if adc_enable enable Output 8
 add_interface_port adc_dma_if adc_data data Output 128
 add_interface_port adc_dma_if adc_dovf dovf Input 1
 add_interface_port adc_dma_if adc_dunf dunf Input 1
diff --git a/library/common/altera/ad_jesd_align.v b/library/common/altera/ad_jesd_align.v
index 17b171a4e..aa73f9baf 100644
--- a/library/common/altera/ad_jesd_align.v
+++ b/library/common/altera/ad_jesd_align.v
@@ -44,6 +44,7 @@ module ad_jesd_align (
   rx_clk,
   rx_sof,
   rx_ip_data,
+  rx_data_sof,
   rx_data);
 
   // jesd interface
@@ -54,6 +55,7 @@ module ad_jesd_align (
 
   // aligned data
 
+  output          rx_data_sof;
   output  [31:0]  rx_data;
 
   // internal registers
@@ -64,33 +66,33 @@ module ad_jesd_align (
 
   // internal signals
 
-  wire    [ 3:0]  rx_sof_s;
 
   // dword may contain more than one frame per clock
 
-  assign rx_sof_s = (rx_sof == 4'd0) ? rx_sof_hold : rx_sof;
+  assign rx_data_sof = |rx_sof;
+
 
   always @(posedge rx_clk) begin
     if (rx_sof != 4'd0) begin
       rx_sof_hold <= rx_sof;
     end
     rx_ip_data_d <= rx_ip_data;
-    if (rx_sof_s[3] == 1'b1) begin
+    if (rx_sof_hold[3] == 1'b1) begin
       rx_data[31:24] <= rx_ip_data[ 7: 0];
       rx_data[23:16] <= rx_ip_data[15: 8];
       rx_data[15: 8] <= rx_ip_data[23:16];
       rx_data[ 7: 0] <= rx_ip_data[31:24];
-    end else if (rx_sof_s[2] == 1'b1) begin
+    end else if (rx_sof_hold[2] == 1'b1) begin
       rx_data[31:24] <= rx_ip_data[31:24];
       rx_data[23:16] <= rx_ip_data_d[ 7: 0];
       rx_data[15: 8] <= rx_ip_data_d[15: 8];
       rx_data[ 7: 0] <= rx_ip_data_d[23:16];
-    end else if (rx_sof_s[1] == 1'b1) begin
+    end else if (rx_sof_hold[1] == 1'b1) begin
       rx_data[31:24] <= rx_ip_data[23:16];
       rx_data[23:16] <= rx_ip_data[31:24];
       rx_data[15: 8] <= rx_ip_data_d[ 7: 0];
       rx_data[ 7: 0] <= rx_ip_data_d[15: 8];
-    end else if (rx_sof_s[0] == 1'b1) begin
+    end else if (rx_sof_hold[0] == 1'b1) begin
       rx_data[31:24] <= rx_ip_data[15: 8];
       rx_data[23:16] <= rx_ip_data[23:16];
       rx_data[15: 8] <= rx_ip_data[31:24];
diff --git a/projects/usdrx1/a5gt/system_bd.qsys b/projects/usdrx1/a5gt/system_bd.qsys
new file mode 100644
index 000000000..38aeea349
--- /dev/null
+++ b/projects/usdrx1/a5gt/system_bd.qsys
@@ -0,0 +1,2786 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags=""
+   categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element $${FILENAME}
+   {
+   }
+   element sys_uart.avalon_jtag_slave
+   {
+      datum baseAddress
+      {
+         value = "86025440";
+         type = "String";
+      }
+   }
+   element sys_ddr3_cntrl.avl
+   {
+      datum _lockedAddress
+      {
+         value = "0";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element axi_ad9671_0
+   {
+      datum _sortIndex
+      {
+         value = "18";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element axi_ad9671_1
+   {
+      datum _sortIndex
+      {
+         value = "19";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element axi_ad9671_2
+   {
+      datum _sortIndex
+      {
+         value = "20";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element axi_ad9671_3
+   {
+      datum _sortIndex
+      {
+         value = "21";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element axi_dmac
+   {
+      datum _sortIndex
+      {
+         value = "22";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_ddr3_cpuconnect.cntl
+   {
+      datum baseAddress
+      {
+         value = "86025424";
+         type = "String";
+      }
+   }
+   element sys_ethernet.control_port
+   {
+      datum baseAddress
+      {
+         value = "86024192";
+         type = "String";
+      }
+   }
+   element sys_id.control_slave
+   {
+      datum baseAddress
+      {
+         value = "86025432";
+         type = "String";
+      }
+   }
+   element sys_ethernet_dma_tx.csr
+   {
+      datum baseAddress
+      {
+         value = "86025216";
+         type = "String";
+      }
+   }
+   element sys_ethernet_dma_rx.csr
+   {
+      datum baseAddress
+      {
+         value = "86025280";
+         type = "String";
+      }
+   }
+   element sys_jesd204b_s1.jesd204_rx_avs
+   {
+      datum baseAddress
+      {
+         value = "67108864";
+         type = "String";
+      }
+   }
+   element sys_cpu.jtag_debug_module
+   {
+      datum _lockedAddress
+      {
+         value = "0";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "86022144";
+         type = "String";
+      }
+   }
+   element sys_ddr3_dmaconnect.s0
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element sys_ddr3_interconnect.s0
+   {
+      datum _lockedAddress
+      {
+         value = "0";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element sys_gpio.s1
+   {
+      datum baseAddress
+      {
+         value = "86025408";
+         type = "String";
+      }
+   }
+   element sys_timer.s1
+   {
+      datum baseAddress
+      {
+         value = "86025376";
+         type = "String";
+      }
+   }
+   element sys_int_mem.s1
+   {
+      datum _lockedAddress
+      {
+         value = "0";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "83886080";
+         type = "String";
+      }
+   }
+   element sys_tcm_mem.s1
+   {
+      datum baseAddress
+      {
+         value = "86016000";
+         type = "String";
+      }
+   }
+   element sys_ethernet_desc_mem.s1
+   {
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+   element sys_tcm_mem.s2
+   {
+      datum baseAddress
+      {
+         value = "86016000";
+         type = "String";
+      }
+   }
+   element sys_int_mem.s2
+   {
+      datum _lockedAddress
+      {
+         value = "0";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "83886080";
+         type = "String";
+      }
+   }
+   element axi_ad9671_2.s_axi
+   {
+      datum baseAddress
+      {
+         value = "86114304";
+         type = "String";
+      }
+   }
+   element axi_ad9671_3.s_axi
+   {
+      datum baseAddress
+      {
+         value = "86179840";
+         type = "String";
+      }
+   }
+   element axi_ad9671_0.s_axi
+   {
+      datum baseAddress
+      {
+         value = "85983232";
+         type = "String";
+      }
+   }
+   element axi_dmac.s_axi
+   {
+      datum baseAddress
+      {
+         value = "85999616";
+         type = "String";
+      }
+   }
+   element axi_ad9671_1.s_axi
+   {
+      datum baseAddress
+      {
+         value = "86048768";
+         type = "String";
+      }
+   }
+   element sys_spi.spi_control_port
+   {
+      datum baseAddress
+      {
+         value = "86025344";
+         type = "String";
+      }
+   }
+   element sys_clk
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_cpu
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_ddr3_cntrl
+   {
+      datum _sortIndex
+      {
+         value = "5";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_ddr3_cpuconnect
+   {
+      datum _sortIndex
+      {
+         value = "7";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_ddr3_dmaconnect
+   {
+      datum _sortIndex
+      {
+         value = "17";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_ddr3_interconnect
+   {
+      datum _sortIndex
+      {
+         value = "6";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_ethernet
+   {
+      datum _sortIndex
+      {
+         value = "8";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_ethernet_desc_mem
+   {
+      datum _sortIndex
+      {
+         value = "11";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_ethernet_dma_rx
+   {
+      datum _sortIndex
+      {
+         value = "9";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_ethernet_dma_tx
+   {
+      datum _sortIndex
+      {
+         value = "10";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_gpio
+   {
+      datum _sortIndex
+      {
+         value = "15";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_id
+   {
+      datum _sortIndex
+      {
+         value = "14";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_int_mem
+   {
+      datum _sortIndex
+      {
+         value = "3";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_jesd204b_s1
+   {
+      datum _sortIndex
+      {
+         value = "26";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_jesd204b_s1_pll
+   {
+      datum _sortIndex
+      {
+         value = "24";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_jesd204b_s1_ref_clk
+   {
+      datum _sortIndex
+      {
+         value = "23";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_jesd204b_s1_rx_clk
+   {
+      datum _sortIndex
+      {
+         value = "25";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_pll
+   {
+      datum _sortIndex
+      {
+         value = "1";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_spi
+   {
+      datum _sortIndex
+      {
+         value = "16";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_tcm_mem
+   {
+      datum _sortIndex
+      {
+         value = "4";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_timer
+   {
+      datum _sortIndex
+      {
+         value = "13";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_uart
+   {
+      datum _sortIndex
+      {
+         value = "12";
+         type = "int";
+      }
+      datum sopceditor_expanded
+      {
+         value = "1";
+         type = "boolean";
+      }
+   }
+   element sys_ddr3_cpuconnect.windowed_slave
+   {
+      datum _lockedAddress
+      {
+         value = "1";
+         type = "boolean";
+      }
+      datum baseAddress
+      {
+         value = "0";
+         type = "String";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="FIFO" />
+ <parameter name="device" value="5AGTFD7K3F40I3" />
+ <parameter name="deviceFamily" value="Arria V" />
+ <parameter name="deviceSpeedGrade" value="3_H3" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="maxAdditionalLatency" value="2" />
+ <parameter name="projectName" value="usdrx1_a5gt.qpf" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="sys_reset"
+   internal="sys_clk.clk_in_reset"
+   type="reset"
+   dir="end" />
+ <interface
+   name="sys_125m_clk"
+   internal="sys_pll.outclk2"
+   type="clock"
+   dir="start" />
+ <interface
+   name="sys_25m_clk"
+   internal="sys_pll.outclk3"
+   type="clock"
+   dir="start" />
+ <interface
+   name="sys_2m5_clk"
+   internal="sys_pll.outclk4"
+   type="clock"
+   dir="start" />
+ <interface
+   name="sys_ddr3_phy"
+   internal="sys_ddr3_cntrl.memory"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ddr3_oct"
+   internal="sys_ddr3_cntrl.oct"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ethernet_tx_clk"
+   internal="sys_ethernet.pcs_mac_tx_clock_connection"
+   type="clock"
+   dir="end" />
+ <interface
+   name="sys_ethernet_rx_clk"
+   internal="sys_ethernet.pcs_mac_rx_clock_connection"
+   type="clock"
+   dir="end" />
+ <interface
+   name="sys_ethernet_status"
+   internal="sys_ethernet.mac_status_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ethernet_rgmii"
+   internal="sys_ethernet.mac_rgmii_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_ethernet_mdio"
+   internal="sys_ethernet.mac_mdio_connection"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_gpio"
+   internal="sys_gpio.external_connection"
+   type="conduit"
+   dir="end" />
+ <interface name="sys_spi" internal="sys_spi.external" type="conduit" dir="end" />
+ <interface
+   name="axi_dmac_0_fifo_wr_clock"
+   internal="axi_dmac.fifo_wr_clock"
+   type="clock"
+   dir="end" />
+ <interface
+   name="axi_dmac_0_fifo_wr_if"
+   internal="axi_dmac.fifo_wr_if"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_rx_link"
+   internal="sys_jesd204b_s1.jesd204_rx_link"
+   type="avalon_streaming"
+   dir="start" />
+ <interface
+   name="sys_jesd204b_s1_lane_aligned_all"
+   internal="sys_jesd204b_s1.alldev_lane_aligned"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_sysref"
+   internal="sys_jesd204b_s1.sysref"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_rx_ferr"
+   internal="sys_jesd204b_s1.jesd204_rx_frame_error"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_lane_aligned"
+   internal="sys_jesd204b_s1.dev_lane_aligned"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_sync_n"
+   internal="sys_jesd204b_s1.dev_sync_n"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_rx_sof"
+   internal="sys_jesd204b_s1.sof"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_rx_xcvr_data"
+   internal="sys_jesd204b_s1.rx_serial_data"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_rx_analogreset"
+   internal="sys_jesd204b_s1.rx_analogreset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_rx_digitalreset"
+   internal="sys_jesd204b_s1.rx_digitalreset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_locked"
+   internal="sys_jesd204b_s1.rx_islockedtodata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_rx_cal_busy"
+   internal="sys_jesd204b_s1.rx_cal_busy"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_ref_clk"
+   internal="sys_jesd204b_s1_ref_clk.in_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="sys_jesd204b_s1_rx_clk"
+   internal="sys_jesd204b_s1_rx_clk.out_clk"
+   type="clock"
+   dir="start" />
+ <interface
+   name="sys_jesd204b_s1_pll_locked"
+   internal="sys_jesd204b_s1_pll.locked"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="sys_pll_locked"
+   internal="sys_pll.locked"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="axi_ad9671_0_xcvr_clk"
+   internal="axi_ad9671_0.xcvr_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="axi_ad9671_0_xcvr_data"
+   internal="axi_ad9671_0.xcvr_data"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="axi_ad9671_0_adc_clock"
+   internal="axi_ad9671_0.adc_clock"
+   type="clock"
+   dir="start" />
+ <interface
+   name="axi_ad9671_0_adc_dma_if"
+   internal="axi_ad9671_0.adc_dma_if"
+   type="conduit"
+   dir="end" />
+ <interface name="axi_ad9671_1_adc_mon_if" internal="axi_ad9671_0.adc_mon_if" />
+ <interface
+   name="axi_ad9671_1_xcvr_clk"
+   internal="axi_ad9671_1.xcvr_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="axi_ad9671_1_xcvr_data"
+   internal="axi_ad9671_1.xcvr_data"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="axi_ad9671_1_adc_clock"
+   internal="axi_ad9671_1.adc_clock"
+   type="clock"
+   dir="start" />
+ <interface
+   name="axi_ad9671_1_adc_dma_if"
+   internal="axi_ad9671_1.adc_dma_if"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="axi_ad9671_2_xcvr_clk"
+   internal="axi_ad9671_2.xcvr_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="axi_ad9671_2_xcvr_data"
+   internal="axi_ad9671_2.xcvr_data"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="axi_ad9671_2_adc_clock"
+   internal="axi_ad9671_2.adc_clock"
+   type="clock"
+   dir="start" />
+ <interface
+   name="axi_ad9671_2_adc_dma_if"
+   internal="axi_ad9671_2.adc_dma_if"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="axi_ad9671_3_xcvr_clk"
+   internal="axi_ad9671_3.xcvr_clk"
+   type="clock"
+   dir="end" />
+ <interface
+   name="axi_ad9671_3_xcvr_data"
+   internal="axi_ad9671_3.xcvr_data"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="axi_ad9671_3_adc_clock"
+   internal="axi_ad9671_3.adc_clock"
+   type="clock"
+   dir="start" />
+ <interface
+   name="axi_ad9671_3_adc_dma_if"
+   internal="axi_ad9671_3.adc_dma_if"
+   type="conduit"
+   dir="end" />
+ <interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
+ <module kind="clock_source" version="14.0" enabled="1" name="sys_clk">
+  <parameter name="clockFrequency" value="100000000" />
+  <parameter name="clockFrequencyKnown" value="true" />
+  <parameter name="inputClockFrequency" value="0" />
+  <parameter name="resetSynchronousEdges" value="DEASSERT" />
+ </module>
+ <module kind="altera_pll" version="14.0" enabled="1" name="sys_pll">
+  <parameter name="debug_print_output" value="false" />
+  <parameter name="debug_use_rbc_taf_method" value="false" />
+  <parameter name="device_family" value="Arria V" />
+  <parameter name="device" value="5AGTFD7K3F40I3" />
+  <parameter name="gui_device_speed_grade" value="2" />
+  <parameter name="gui_pll_mode" value="Integer-N PLL" />
+  <parameter name="gui_reference_clock_frequency" value="100.0" />
+  <parameter name="gui_channel_spacing" value="0.0" />
+  <parameter name="gui_operation_mode" value="direct" />
+  <parameter name="gui_feedback_clock" value="Global Clock" />
+  <parameter name="gui_fractional_cout" value="32" />
+  <parameter name="gui_dsm_out_sel" value="1st_order" />
+  <parameter name="gui_use_locked" value="true" />
+  <parameter name="gui_en_adv_params" value="false" />
+  <parameter name="gui_number_of_clocks" value="5" />
+  <parameter name="gui_multiply_factor" value="1" />
+  <parameter name="gui_frac_multiply_factor" value="1" />
+  <parameter name="gui_divide_factor_n" value="1" />
+  <parameter name="gui_cascade_counter0" value="false" />
+  <parameter name="gui_output_clock_frequency0" value="100.0" />
+  <parameter name="gui_divide_factor_c0" value="1" />
+  <parameter name="gui_actual_output_clock_frequency0" value="0 MHz" />
+  <parameter name="gui_ps_units0" value="ps" />
+  <parameter name="gui_phase_shift0" value="0" />
+  <parameter name="gui_phase_shift_deg0" value="0.0" />
+  <parameter name="gui_actual_phase_shift0" value="0" />
+  <parameter name="gui_duty_cycle0" value="50" />
+  <parameter name="gui_cascade_counter1" value="false" />
+  <parameter name="gui_output_clock_frequency1" value="166.666666" />
+  <parameter name="gui_divide_factor_c1" value="1" />
+  <parameter name="gui_actual_output_clock_frequency1" value="166.666666 MHz" />
+  <parameter name="gui_ps_units1" value="ps" />
+  <parameter name="gui_phase_shift1" value="0" />
+  <parameter name="gui_phase_shift_deg1" value="0.0" />
+  <parameter name="gui_actual_phase_shift1" value="0" />
+  <parameter name="gui_duty_cycle1" value="50" />
+  <parameter name="gui_cascade_counter2" value="false" />
+  <parameter name="gui_output_clock_frequency2" value="125.0" />
+  <parameter name="gui_divide_factor_c2" value="1" />
+  <parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
+  <parameter name="gui_ps_units2" value="ps" />
+  <parameter name="gui_phase_shift2" value="0" />
+  <parameter name="gui_phase_shift_deg2" value="0.0" />
+  <parameter name="gui_actual_phase_shift2" value="0" />
+  <parameter name="gui_duty_cycle2" value="50" />
+  <parameter name="gui_cascade_counter3" value="false" />
+  <parameter name="gui_output_clock_frequency3" value="25.0" />
+  <parameter name="gui_divide_factor_c3" value="1" />
+  <parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
+  <parameter name="gui_ps_units3" value="ps" />
+  <parameter name="gui_phase_shift3" value="0" />
+  <parameter name="gui_phase_shift_deg3" value="0.0" />
+  <parameter name="gui_actual_phase_shift3" value="0" />
+  <parameter name="gui_duty_cycle3" value="50" />
+  <parameter name="gui_cascade_counter4" value="false" />
+  <parameter name="gui_output_clock_frequency4" value="2.5" />
+  <parameter name="gui_divide_factor_c4" value="1" />
+  <parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
+  <parameter name="gui_ps_units4" value="ps" />
+  <parameter name="gui_phase_shift4" value="0" />
+  <parameter name="gui_phase_shift_deg4" value="0.0" />
+  <parameter name="gui_actual_phase_shift4" value="0" />
+  <parameter name="gui_duty_cycle4" value="50" />
+  <parameter name="gui_cascade_counter5" value="false" />
+  <parameter name="gui_output_clock_frequency5" value="100.0" />
+  <parameter name="gui_divide_factor_c5" value="1" />
+  <parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
+  <parameter name="gui_ps_units5" value="ps" />
+  <parameter name="gui_phase_shift5" value="0" />
+  <parameter name="gui_phase_shift_deg5" value="0.0" />
+  <parameter name="gui_actual_phase_shift5" value="0" />
+  <parameter name="gui_duty_cycle5" value="50" />
+  <parameter name="gui_cascade_counter6" value="false" />
+  <parameter name="gui_output_clock_frequency6" value="100.0" />
+  <parameter name="gui_divide_factor_c6" value="1" />
+  <parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
+  <parameter name="gui_ps_units6" value="ps" />
+  <parameter name="gui_phase_shift6" value="0" />
+  <parameter name="gui_phase_shift_deg6" value="0.0" />
+  <parameter name="gui_actual_phase_shift6" value="0" />
+  <parameter name="gui_duty_cycle6" value="50" />
+  <parameter name="gui_cascade_counter7" value="false" />
+  <parameter name="gui_output_clock_frequency7" value="100.0" />
+  <parameter name="gui_divide_factor_c7" value="1" />
+  <parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
+  <parameter name="gui_ps_units7" value="ps" />
+  <parameter name="gui_phase_shift7" value="0" />
+  <parameter name="gui_phase_shift_deg7" value="0.0" />
+  <parameter name="gui_actual_phase_shift7" value="0" />
+  <parameter name="gui_duty_cycle7" value="50" />
+  <parameter name="gui_cascade_counter8" value="false" />
+  <parameter name="gui_output_clock_frequency8" value="100.0" />
+  <parameter name="gui_divide_factor_c8" value="1" />
+  <parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
+  <parameter name="gui_ps_units8" value="ps" />
+  <parameter name="gui_phase_shift8" value="0" />
+  <parameter name="gui_phase_shift_deg8" value="0.0" />
+  <parameter name="gui_actual_phase_shift8" value="0" />
+  <parameter name="gui_duty_cycle8" value="50" />
+  <parameter name="gui_cascade_counter9" value="false" />
+  <parameter name="gui_output_clock_frequency9" value="100.0" />
+  <parameter name="gui_divide_factor_c9" value="1" />
+  <parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
+  <parameter name="gui_ps_units9" value="ps" />
+  <parameter name="gui_phase_shift9" value="0" />
+  <parameter name="gui_phase_shift_deg9" value="0.0" />
+  <parameter name="gui_actual_phase_shift9" value="0" />
+  <parameter name="gui_duty_cycle9" value="50" />
+  <parameter name="gui_cascade_counter10" value="false" />
+  <parameter name="gui_output_clock_frequency10" value="100.0" />
+  <parameter name="gui_divide_factor_c10" value="1" />
+  <parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
+  <parameter name="gui_ps_units10" value="ps" />
+  <parameter name="gui_phase_shift10" value="0" />
+  <parameter name="gui_phase_shift_deg10" value="0.0" />
+  <parameter name="gui_actual_phase_shift10" value="0" />
+  <parameter name="gui_duty_cycle10" value="50" />
+  <parameter name="gui_cascade_counter11" value="false" />
+  <parameter name="gui_output_clock_frequency11" value="100.0" />
+  <parameter name="gui_divide_factor_c11" value="1" />
+  <parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
+  <parameter name="gui_ps_units11" value="ps" />
+  <parameter name="gui_phase_shift11" value="0" />
+  <parameter name="gui_phase_shift_deg11" value="0.0" />
+  <parameter name="gui_actual_phase_shift11" value="0" />
+  <parameter name="gui_duty_cycle11" value="50" />
+  <parameter name="gui_cascade_counter12" value="false" />
+  <parameter name="gui_output_clock_frequency12" value="100.0" />
+  <parameter name="gui_divide_factor_c12" value="1" />
+  <parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
+  <parameter name="gui_ps_units12" value="ps" />
+  <parameter name="gui_phase_shift12" value="0" />
+  <parameter name="gui_phase_shift_deg12" value="0.0" />
+  <parameter name="gui_actual_phase_shift12" value="0" />
+  <parameter name="gui_duty_cycle12" value="50" />
+  <parameter name="gui_cascade_counter13" value="false" />
+  <parameter name="gui_output_clock_frequency13" value="100.0" />
+  <parameter name="gui_divide_factor_c13" value="1" />
+  <parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
+  <parameter name="gui_ps_units13" value="ps" />
+  <parameter name="gui_phase_shift13" value="0" />
+  <parameter name="gui_phase_shift_deg13" value="0.0" />
+  <parameter name="gui_actual_phase_shift13" value="0" />
+  <parameter name="gui_duty_cycle13" value="50" />
+  <parameter name="gui_cascade_counter14" value="false" />
+  <parameter name="gui_output_clock_frequency14" value="100.0" />
+  <parameter name="gui_divide_factor_c14" value="1" />
+  <parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
+  <parameter name="gui_ps_units14" value="ps" />
+  <parameter name="gui_phase_shift14" value="0" />
+  <parameter name="gui_phase_shift_deg14" value="0.0" />
+  <parameter name="gui_actual_phase_shift14" value="0" />
+  <parameter name="gui_duty_cycle14" value="50" />
+  <parameter name="gui_cascade_counter15" value="false" />
+  <parameter name="gui_output_clock_frequency15" value="100.0" />
+  <parameter name="gui_divide_factor_c15" value="1" />
+  <parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
+  <parameter name="gui_ps_units15" value="ps" />
+  <parameter name="gui_phase_shift15" value="0" />
+  <parameter name="gui_phase_shift_deg15" value="0.0" />
+  <parameter name="gui_actual_phase_shift15" value="0" />
+  <parameter name="gui_duty_cycle15" value="50" />
+  <parameter name="gui_cascade_counter16" value="false" />
+  <parameter name="gui_output_clock_frequency16" value="100.0" />
+  <parameter name="gui_divide_factor_c16" value="1" />
+  <parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
+  <parameter name="gui_ps_units16" value="ps" />
+  <parameter name="gui_phase_shift16" value="0" />
+  <parameter name="gui_phase_shift_deg16" value="0.0" />
+  <parameter name="gui_actual_phase_shift16" value="0" />
+  <parameter name="gui_duty_cycle16" value="50" />
+  <parameter name="gui_cascade_counter17" value="false" />
+  <parameter name="gui_output_clock_frequency17" value="100.0" />
+  <parameter name="gui_divide_factor_c17" value="1" />
+  <parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
+  <parameter name="gui_ps_units17" value="ps" />
+  <parameter name="gui_phase_shift17" value="0" />
+  <parameter name="gui_phase_shift_deg17" value="0.0" />
+  <parameter name="gui_actual_phase_shift17" value="0" />
+  <parameter name="gui_duty_cycle17" value="50" />
+  <parameter name="gui_pll_auto_reset" value="Off" />
+  <parameter name="gui_pll_bandwidth_preset" value="Auto" />
+  <parameter name="gui_en_reconf" value="false" />
+  <parameter name="gui_en_dps_ports" value="false" />
+  <parameter name="gui_en_phout_ports" value="false" />
+  <parameter name="gui_phout_division" value="1" />
+  <parameter name="gui_en_lvds_ports" value="false" />
+  <parameter name="gui_mif_generate" value="false" />
+  <parameter name="gui_enable_mif_dps" value="false" />
+  <parameter name="gui_dps_cntr" value="C0" />
+  <parameter name="gui_dps_num" value="1" />
+  <parameter name="gui_dps_dir" value="Positive" />
+  <parameter name="gui_refclk_switch" value="false" />
+  <parameter name="gui_refclk1_frequency" value="100.0" />
+  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+  <parameter name="gui_switchover_delay" value="0" />
+  <parameter name="gui_active_clk" value="false" />
+  <parameter name="gui_clk_bad" value="false" />
+  <parameter name="gui_enable_cascade_out" value="false" />
+  <parameter name="gui_cascade_outclk_index" value="0" />
+  <parameter name="gui_enable_cascade_in" value="false" />
+  <parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
+  <parameter name="AUTO_REFCLK_CLOCK_RATE" value="100000000" />
+ </module>
+ <module kind="altera_nios2_qsys" version="14.0" enabled="1" name="sys_cpu">
+  <parameter name="setting_showUnpublishedSettings" value="false" />
+  <parameter name="setting_showInternalSettings" value="false" />
+  <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
+  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+  <parameter name="setting_preciseDivisionErrorException" value="false" />
+  <parameter name="setting_performanceCounter" value="false" />
+  <parameter name="setting_illegalMemAccessDetection" value="false" />
+  <parameter name="setting_illegalInstructionsTrap" value="false" />
+  <parameter name="setting_fullWaveformSignals" value="false" />
+  <parameter name="setting_extraExceptionInfo" value="false" />
+  <parameter name="setting_exportPCB" value="false" />
+  <parameter name="setting_debugSimGen" value="false" />
+  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+  <parameter name="setting_bit31BypassDCache" value="true" />
+  <parameter name="setting_bigEndian" value="false" />
+  <parameter name="setting_export_large_RAMs" value="false" />
+  <parameter name="setting_asic_enabled" value="false" />
+  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
+  <parameter name="setting_oci_export_jtag_signals" value="false" />
+  <parameter name="setting_bhtIndexPcOnly" value="false" />
+  <parameter name="setting_avalonDebugPortPresent" value="false" />
+  <parameter name="setting_alwaysEncrypt" value="true" />
+  <parameter name="setting_allowFullAddressRange" value="false" />
+  <parameter name="setting_activateTrace" value="true" />
+  <parameter name="setting_activateTrace_user" value="false" />
+  <parameter name="setting_activateTestEndChecker" value="false" />
+  <parameter name="setting_ecc_sim_test_ports" value="false" />
+  <parameter name="setting_activateMonitors" value="true" />
+  <parameter name="setting_activateModelChecker" value="false" />
+  <parameter name="setting_HDLSimCachesCleared" value="true" />
+  <parameter name="setting_HBreakTest" value="false" />
+  <parameter name="setting_breakslaveoveride" value="false" />
+  <parameter name="muldiv_divider" value="false" />
+  <parameter name="mpu_useLimit" value="false" />
+  <parameter name="mpu_enabled" value="true" />
+  <parameter name="mmu_enabled" value="false" />
+  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+  <parameter name="manuallyAssignCpuID" value="true" />
+  <parameter name="debug_triggerArming" value="true" />
+  <parameter name="debug_embeddedPLL" value="true" />
+  <parameter name="debug_debugReqSignals" value="false" />
+  <parameter name="debug_assignJtagInstanceID" value="false" />
+  <parameter name="dcache_omitDataMaster" value="false" />
+  <parameter name="cpuReset" value="false" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="setting_removeRAMinit" value="false" />
+  <parameter name="setting_shadowRegisterSets" value="0" />
+  <parameter name="mpu_numOfInstRegion" value="8" />
+  <parameter name="mpu_numOfDataRegion" value="8" />
+  <parameter name="mmu_TLBMissExcOffset" value="4096" />
+  <parameter name="debug_jtagInstanceID" value="0" />
+  <parameter name="resetOffset" value="0" />
+  <parameter name="exceptionOffset" value="32" />
+  <parameter name="cpuID" value="0" />
+  <parameter name="cpuID_stored" value="0" />
+  <parameter name="breakOffset" value="32" />
+  <parameter name="userDefinedSettings" value="" />
+  <parameter name="resetSlave" value="sys_int_mem.s2" />
+  <parameter name="mmu_TLBMissExcSlave" value="sys_int_mem.s2" />
+  <parameter name="exceptionSlave" value="sys_int_mem.s2" />
+  <parameter name="breakSlave">sys_cpu.jtag_debug_module</parameter>
+  <parameter name="setting_perfCounterWidth" value="32" />
+  <parameter name="setting_interruptControllerType" value="Internal" />
+  <parameter name="setting_branchPredictionType" value="Automatic" />
+  <parameter name="setting_bhtPtrSz" value="8" />
+  <parameter name="muldiv_multiplierType" value="DSPBlock" />
+  <parameter name="mpu_minInstRegionSize" value="12" />
+  <parameter name="mpu_minDataRegionSize" value="12" />
+  <parameter name="mmu_uitlbNumEntries" value="4" />
+  <parameter name="mmu_udtlbNumEntries" value="6" />
+  <parameter name="mmu_tlbPtrSz" value="7" />
+  <parameter name="mmu_tlbNumWays" value="16" />
+  <parameter name="mmu_processIDNumBits" value="8" />
+  <parameter name="impl" value="Fast" />
+  <parameter name="icache_size" value="4096" />
+  <parameter name="icache_tagramBlockType" value="Automatic" />
+  <parameter name="icache_ramBlockType" value="Automatic" />
+  <parameter name="icache_numTCIM" value="1" />
+  <parameter name="icache_burstType" value="None" />
+  <parameter name="dcache_bursts" value="false" />
+  <parameter name="dcache_victim_buf_impl" value="ram" />
+  <parameter name="debug_level" value="Level1" />
+  <parameter name="debug_OCIOnchipTrace" value="_128" />
+  <parameter name="dcache_size" value="2048" />
+  <parameter name="dcache_tagramBlockType" value="Automatic" />
+  <parameter name="dcache_ramBlockType" value="Automatic" />
+  <parameter name="dcache_numTCDM" value="1" />
+  <parameter name="dcache_lineSize" value="32" />
+  <parameter name="setting_exportvectors" value="false" />
+  <parameter name="setting_ecc_present" value="false" />
+  <parameter name="setting_ic_ecc_present" value="true" />
+  <parameter name="setting_rf_ecc_present" value="true" />
+  <parameter name="setting_mmu_ecc_present" value="true" />
+  <parameter name="setting_dc_ecc_present" value="false" />
+  <parameter name="setting_itcm_ecc_present" value="false" />
+  <parameter name="setting_dtcm_ecc_present" value="false" />
+  <parameter name="regfile_ramBlockType" value="Automatic" />
+  <parameter name="ocimem_ramBlockType" value="Automatic" />
+  <parameter name="mmu_ramBlockType" value="Automatic" />
+  <parameter name="bht_ramBlockType" value="Automatic" />
+  <parameter name="instAddrWidth" value="27" />
+  <parameter name="dataAddrWidth" value="27" />
+  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="27" />
+  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="27" />
+  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cpuconnect.windowed_slave' start='0x0' end='0x4000000' /><slave name='sys_int_mem.s2' start='0x5000000' end='0x5180000' /><slave name='sys_cpu.jtag_debug_module' start='0x5209800' end='0x520A000' /></address-map>]]></parameter>
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='sys_ddr3_cpuconnect.windowed_slave' start='0x0' end='0x4000000' /><slave name='sys_jesd204b_s1.jesd204_rx_avs' start='0x4000000' end='0x4000400' /><slave name='sys_int_mem.s1' start='0x5000000' end='0x5180000' /><slave name='axi_ad9671_0.s_axi' start='0x5200000' end='0x5204000' /><slave name='axi_dmac.s_axi' start='0x5204000' end='0x5208000' /><slave name='sys_cpu.jtag_debug_module' start='0x5209800' end='0x520A000' /><slave name='sys_ethernet.control_port' start='0x520A000' end='0x520A400' /><slave name='sys_ethernet_dma_tx.csr' start='0x520A400' end='0x520A440' /><slave name='sys_ethernet_dma_rx.csr' start='0x520A440' end='0x520A480' /><slave name='sys_spi.spi_control_port' start='0x520A480' end='0x520A4A0' /><slave name='sys_timer.s1' start='0x520A4A0' end='0x520A4C0' /><slave name='sys_gpio.s1' start='0x520A4C0' end='0x520A4D0' /><slave name='sys_ddr3_cpuconnect.cntl' start='0x520A4D0' end='0x520A4D8' /><slave name='sys_id.control_slave' start='0x520A4D8' end='0x520A4E0' /><slave name='sys_uart.avalon_jtag_slave' start='0x520A4E0' end='0x520A4E8' /><slave name='axi_ad9671_1.s_axi' start='0x5210000' end='0x5214000' /><slave name='axi_ad9671_2.s_axi' start='0x5220000' end='0x5224000' /><slave name='axi_ad9671_3.s_axi' start='0x5230000' end='0x5234000' /></address-map>]]></parameter>
+  <parameter name="clockFrequency" value="100000000" />
+  <parameter name="deviceFamilyName" value="Arria V" />
+  <parameter name="internalIrqMaskSystemInfo" value="63" />
+  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
+  <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+  <parameter name="tightlyCoupledDataMaster0MapParam"><![CDATA[<address-map><slave name='sys_tcm_mem.s1' start='0x5208000' end='0x5209000' /></address-map>]]></parameter>
+  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster0MapParam"><![CDATA[<address-map><slave name='sys_tcm_mem.s2' start='0x5208000' end='0x5209000' /></address-map>]]></parameter>
+  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+ </module>
+ <module
+   kind="altera_avalon_onchip_memory2"
+   version="14.0"
+   enabled="1"
+   name="sys_int_mem">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="dualPort" value="true" />
+  <parameter name="initMemContent" value="true" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="1572864" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="autoInitializationFileName">$${FILENAME}_sys_int_mem</parameter>
+  <parameter name="deviceFamily" value="Arria V" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ </module>
+ <module
+   kind="altera_mem_if_ddr3_emif"
+   version="14.0"
+   enabled="1"
+   name="sys_ddr3_cntrl">
+  <parameter name="MEM_VENDOR" value="Micron" />
+  <parameter name="MEM_FORMAT" value="DISCRETE" />
+  <parameter name="RDIMM_CONFIG" value="0" />
+  <parameter name="LRDIMM_EXTENDED_CONFIG" value="0x0" />
+  <parameter name="DISCRETE_FLY_BY" value="true" />
+  <parameter name="DEVICE_DEPTH" value="1" />
+  <parameter name="DEVICE_WIDTH" value="1" />
+  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
+  <parameter name="MEM_CLK_FREQ_MAX" value="800.0" />
+  <parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
+  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
+  <parameter name="MEM_DQ_WIDTH" value="64" />
+  <parameter name="MEM_DQ_PER_DQS" value="8" />
+  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
+  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
+  <parameter name="MEM_IF_DQSN_EN" value="true" />
+  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
+  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
+  <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" />
+  <parameter name="MEM_CK_WIDTH" value="1" />
+  <parameter name="MEM_CS_WIDTH" value="1" />
+  <parameter name="MEM_CLK_EN_WIDTH" value="1" />
+  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
+  <parameter name="NEXTGEN" value="true" />
+  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
+  <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" />
+  <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" />
+  <parameter name="MEM_VERBOSE" value="true" />
+  <parameter name="PINGPONGPHY_EN" value="false" />
+  <parameter name="DUPLICATE_AC" value="false" />
+  <parameter name="REFRESH_BURST_VALIDATION" value="false" />
+  <parameter name="MEM_BL" value="OTF" />
+  <parameter name="MEM_BT" value="Sequential" />
+  <parameter name="MEM_ASR" value="Manual" />
+  <parameter name="MEM_SRT" value="Normal" />
+  <parameter name="MEM_PD" value="DLL off" />
+  <parameter name="MEM_DRV_STR" value="RZQ/6" />
+  <parameter name="MEM_DLL_EN" value="true" />
+  <parameter name="MEM_RTT_NOM" value="RZQ/6" />
+  <parameter name="MEM_RTT_WR" value="RZQ/4" />
+  <parameter name="MEM_WTCL" value="8" />
+  <parameter name="MEM_ATCL" value="Disabled" />
+  <parameter name="MEM_TCL" value="11" />
+  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
+  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
+  <parameter name="MEM_INIT_EN" value="false" />
+  <parameter name="MEM_INIT_FILE" value="" />
+  <parameter name="DAT_DATA_WIDTH" value="32" />
+  <parameter name="TIMING_TIS" value="170" />
+  <parameter name="TIMING_TIH" value="120" />
+  <parameter name="TIMING_TDS" value="10" />
+  <parameter name="TIMING_TDH" value="45" />
+  <parameter name="TIMING_TDQSQ" value="100" />
+  <parameter name="TIMING_TQH" value="0.38" />
+  <parameter name="TIMING_TDQSCK" value="255" />
+  <parameter name="TIMING_TDQSCKDS" value="450" />
+  <parameter name="TIMING_TDQSCKDM" value="900" />
+  <parameter name="TIMING_TDQSCKDL" value="1200" />
+  <parameter name="TIMING_TDQSS" value="0.27" />
+  <parameter name="TIMING_TQSH" value="0.4" />
+  <parameter name="TIMING_TDSH" value="0.18" />
+  <parameter name="TIMING_TDSS" value="0.18" />
+  <parameter name="MEM_TINIT_US" value="500" />
+  <parameter name="MEM_TMRD_CK" value="4" />
+  <parameter name="MEM_TRAS_NS" value="35.0" />
+  <parameter name="MEM_TRCD_NS" value="13.75" />
+  <parameter name="MEM_TRP_NS" value="13.75" />
+  <parameter name="MEM_TREFI_US" value="7.8" />
+  <parameter name="MEM_TRFC_NS" value="110.0" />
+  <parameter name="CFG_TCCD_NS" value="2.5" />
+  <parameter name="MEM_TWR_NS" value="15.0" />
+  <parameter name="MEM_TWTR" value="6" />
+  <parameter name="MEM_TFAW_NS" value="30.0" />
+  <parameter name="MEM_TRRD_NS" value="6.0" />
+  <parameter name="MEM_TRTP_NS" value="7.5" />
+  <parameter name="RATE" value="Quarter" />
+  <parameter name="MEM_CLK_FREQ" value="400.0" />
+  <parameter name="USE_MEM_CLK_FREQ" value="false" />
+  <parameter name="FORCE_DQS_TRACKING" value="AUTO" />
+  <parameter name="FORCE_SHADOW_REGS" value="AUTO" />
+  <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" />
+  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria V" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
+  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
+  <parameter name="DEVICE_FAMILY_PARAM" value="" />
+  <parameter name="SPEED_GRADE" value="3" />
+  <parameter name="IS_ES_DEVICE" value="false" />
+  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
+  <parameter name="HARD_EMIF" value="false" />
+  <parameter name="HHP_HPS" value="false" />
+  <parameter name="HHP_HPS_VERIFICATION" value="false" />
+  <parameter name="HHP_HPS_SIMULATION" value="false" />
+  <parameter name="HPS_PROTOCOL" value="DEFAULT" />
+  <parameter name="CUT_NEW_FAMILY_TIMING" value="true" />
+  <parameter name="POWER_OF_TWO_BUS" value="false" />
+  <parameter name="SOPC_COMPAT_RESET" value="false" />
+  <parameter name="AVL_MAX_SIZE" value="256" />
+  <parameter name="BYTE_ENABLE" value="true" />
+  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
+  <parameter name="CTL_DEEP_POWERDN_EN" value="false" />
+  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
+  <parameter name="AUTO_POWERDN_EN" value="false" />
+  <parameter name="AUTO_PD_CYCLES" value="0" />
+  <parameter name="CTL_USR_REFRESH_EN" value="false" />
+  <parameter name="CTL_AUTOPCH_EN" value="false" />
+  <parameter name="CTL_ZQCAL_EN" value="false" />
+  <parameter name="ADDR_ORDER" value="0" />
+  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
+  <parameter name="CONTROLLER_LATENCY" value="5" />
+  <parameter name="CFG_REORDER_DATA" value="true" />
+  <parameter name="STARVE_LIMIT" value="10" />
+  <parameter name="CTL_CSR_ENABLED" value="false" />
+  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="CTL_ECC_ENABLED" value="false" />
+  <parameter name="CTL_HRB_ENABLED" value="false" />
+  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
+  <parameter name="MULTICAST_EN" value="false" />
+  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
+  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
+  <parameter name="DEBUG_MODE" value="false" />
+  <parameter name="ENABLE_BURST_MERGE" value="false" />
+  <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" />
+  <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" />
+  <parameter name="LOCAL_ID_WIDTH" value="8" />
+  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
+  <parameter name="MAX_PENDING_WR_CMD" value="16" />
+  <parameter name="MAX_PENDING_RD_CMD" value="32" />
+  <parameter name="USE_MM_ADAPTOR" value="true" />
+  <parameter name="USE_AXI_ADAPTOR" value="false" />
+  <parameter name="HCX_COMPAT_MODE" value="false" />
+  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
+  <parameter name="CTL_CSR_READ_ONLY" value="1" />
+  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
+  <parameter name="NUM_OF_PORTS" value="1" />
+  <parameter name="ENABLE_BONDING" value="false" />
+  <parameter name="ENABLE_USER_ECC" value="false" />
+  <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" />
+  <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" />
+  <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" />
+  <parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter>
+  <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" />
+  <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" />
+  <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" />
+  <parameter name="REF_CLK_FREQ" value="100.0" />
+  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
+  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
+  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
+  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" />
+  <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" />
+  <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" />
+  <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" />
+  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
+  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
+  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
+  <parameter name="ENABLE_ISS_PROBES" value="false" />
+  <parameter name="CALIB_REG_WIDTH" value="8" />
+  <parameter name="USE_SEQUENCER_BFM" value="false" />
+  <parameter name="PLL_SHARING_MODE" value="None" />
+  <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" />
+  <parameter name="EXPORT_AFI_HALF_CLK" value="false" />
+  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
+  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" />
+  <parameter name="USE_FAKE_PHY" value="false" />
+  <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" />
+  <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" />
+  <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" />
+  <parameter name="TRACKING_ERROR_TEST" value="false" />
+  <parameter name="TRACKING_WATCH_TEST" value="false" />
+  <parameter name="MARGIN_VARIATION_TEST" value="false" />
+  <parameter name="EXTRA_SETTINGS" value="" />
+  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
+  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
+  <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" />
+  <parameter name="SEQUENCER_TYPE" value="NIOS" />
+  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
+  <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" />
+  <parameter name="PHY_ONLY" value="false" />
+  <parameter name="SEQ_MODE" value="0" />
+  <parameter name="ADVANCED_CK_PHASES" value="false" />
+  <parameter name="COMMAND_PHASE" value="0.0" />
+  <parameter name="MEM_CK_PHASE" value="0.0" />
+  <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" />
+  <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" />
+  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
+  <parameter name="PLL_LOCATION" value="Top_Bottom" />
+  <parameter name="SKIP_MEM_INIT" value="true" />
+  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
+  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
+  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
+  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
+  <parameter name="CALIBRATION_MODE" value="Skip" />
+  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
+  <parameter name="READ_FIFO_SIZE" value="8" />
+  <parameter name="PHY_CSR_ENABLED" value="false" />
+  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
+  <parameter name="USER_DEBUG_LEVEL" value="1" />
+  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
+  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
+  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
+  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
+  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
+  <parameter name="TIMING_BOARD_TIS" value="0.0" />
+  <parameter name="TIMING_BOARD_TIH" value="0.0" />
+  <parameter name="TIMING_BOARD_TDS" value="0.0" />
+  <parameter name="TIMING_BOARD_TDH" value="0.0" />
+  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
+  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
+  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" />
+  <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" />
+  <parameter name="PACKAGE_DESKEW" value="false" />
+  <parameter name="AC_PACKAGE_DESKEW" value="false" />
+  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" />
+  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" />
+  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
+  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" />
+  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" />
+  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" />
+  <parameter name="TIMING_BOARD_AC_SKEW" value="0.02" />
+  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
+  <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" />
+  <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" />
+  <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" />
+  <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" />
+  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
+  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
+  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
+  <parameter name="DLL_SHARING_MODE" value="None" />
+  <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" />
+  <parameter name="OCT_SHARING_MODE" value="None" />
+  <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" />
+  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
+ </module>
+ <module
+   kind="altera_avalon_mm_clock_crossing_bridge"
+   version="14.0"
+   enabled="1"
+   name="sys_ddr3_interconnect">
+  <parameter name="DATA_WIDTH" value="512" />
+  <parameter name="SYMBOL_WIDTH" value="8" />
+  <parameter name="ADDRESS_WIDTH" value="30" />
+  <parameter name="SYSINFO_ADDR_WIDTH" value="30" />
+  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
+  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
+  <parameter name="MAX_BURST_SIZE" value="1" />
+  <parameter name="COMMAND_FIFO_DEPTH" value="4" />
+  <parameter name="RESPONSE_FIFO_DEPTH" value="4" />
+  <parameter name="MASTER_SYNC_DEPTH" value="2" />
+  <parameter name="SLAVE_SYNC_DEPTH" value="2" />
+  <parameter name="AUTO_M0_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_S0_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
+ </module>
+ <module
+   kind="altera_avalon_jtag_uart"
+   version="14.0"
+   enabled="1"
+   name="sys_uart">
+  <parameter name="allowMultipleConnections" value="false" />
+  <parameter name="hubInstanceID" value="0" />
+  <parameter name="readBufferDepth" value="64" />
+  <parameter name="readIRQThreshold" value="8" />
+  <parameter name="simInputCharacterStream" value="" />
+  <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
+  <parameter name="useRegistersForReadBuffer" value="false" />
+  <parameter name="useRegistersForWriteBuffer" value="false" />
+  <parameter name="useRelativePathForSimFile" value="false" />
+  <parameter name="writeBufferDepth" value="64" />
+  <parameter name="writeIRQThreshold" value="8" />
+  <parameter name="avalonSpec" value="2.0" />
+ </module>
+ <module
+   kind="altera_avalon_timer"
+   version="14.0"
+   enabled="1"
+   name="sys_timer">
+  <parameter name="alwaysRun" value="false" />
+  <parameter name="counterSize" value="32" />
+  <parameter name="fixedPeriod" value="false" />
+  <parameter name="period" value="1" />
+  <parameter name="periodUnits" value="MSEC" />
+  <parameter name="resetOutput" value="false" />
+  <parameter name="snapshot" value="true" />
+  <parameter name="timeoutPulseOutput" value="false" />
+  <parameter name="systemFrequency" value="100000000" />
+ </module>
+ <module
+   kind="altera_avalon_sysid_qsys"
+   version="14.0"
+   enabled="1"
+   name="sys_id">
+  <parameter name="id" value="0" />
+  <parameter name="timestamp" value="0" />
+  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
+ </module>
+ <module kind="altera_eth_tse" version="14.0" enabled="1" name="sys_ethernet">
+  <parameter name="deviceFamilyName" value="Arria V" />
+  <parameter name="core_variation" value="MAC_ONLY" />
+  <parameter name="ifGMII" value="RGMII" />
+  <parameter name="enable_use_internal_fifo" value="true" />
+  <parameter name="enable_ecc" value="false" />
+  <parameter name="max_channels" value="1" />
+  <parameter name="use_misc_ports" value="true" />
+  <parameter name="transceiver_type" value="NONE" />
+  <parameter name="enable_hd_logic" value="true" />
+  <parameter name="enable_gmii_loopback" value="false" />
+  <parameter name="enable_sup_addr" value="false" />
+  <parameter name="stat_cnt_ena" value="true" />
+  <parameter name="ext_stat_cnt_ena" value="false" />
+  <parameter name="ena_hash" value="false" />
+  <parameter name="enable_shift16" value="true" />
+  <parameter name="enable_mac_flow_ctrl" value="true" />
+  <parameter name="enable_mac_vlan" value="false" />
+  <parameter name="enable_magic_detect" value="true" />
+  <parameter name="useMDIO" value="true" />
+  <parameter name="mdio_clk_div" value="30" />
+  <parameter name="enable_ena" value="32" />
+  <parameter name="eg_addr" value="11" />
+  <parameter name="ing_addr" value="11" />
+  <parameter name="phy_identifier" value="0" />
+  <parameter name="enable_sgmii" value="false" />
+  <parameter name="export_pwrdn" value="false" />
+  <parameter name="enable_alt_reconfig" value="false" />
+  <parameter name="starting_channel_number" value="0" />
+  <parameter name="phyip_pll_type" value="CMU" />
+  <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
+  <parameter name="phyip_en_synce_support" value="false" />
+  <parameter name="phyip_pma_bonding_mode" value="x1" />
+  <parameter name="nf_phyip_rcfg_enable" value="false" />
+  <parameter name="enable_timestamping" value="false" />
+  <parameter name="enable_ptp_1step" value="false" />
+  <parameter name="tstamp_fp_width" value="4" />
+  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
+ </module>
+ <module
+   kind="altera_avalon_sgdma"
+   version="14.0"
+   enabled="1"
+   name="sys_ethernet_dma_rx">
+  <parameter name="addressWidth" value="32" />
+  <parameter name="alwaysDoMaxBurst" value="true" />
+  <parameter name="avalonMMByteReorderMode" value="0" />
+  <parameter name="dataTransferFIFODepth" value="2" />
+  <parameter name="enableBurstTransfers" value="false" />
+  <parameter name="enableDescriptorReadMasterBurst" value="false" />
+  <parameter name="enableUnalignedTransfers" value="false" />
+  <parameter name="internalFIFODepth" value="2" />
+  <parameter name="readBlockDataWidth" value="32" />
+  <parameter name="readBurstcountWidth" value="4" />
+  <parameter name="sinkErrorWidth" value="0" />
+  <parameter name="sourceErrorWidth" value="0" />
+  <parameter name="transferMode" value="STREAM_TO_MEMORY" />
+  <parameter name="writeBurstcountWidth" value="4" />
+  <parameter name="deviceFamilyString" value="Arria V" />
+ </module>
+ <module
+   kind="altera_avalon_sgdma"
+   version="14.0"
+   enabled="1"
+   name="sys_ethernet_dma_tx">
+  <parameter name="addressWidth" value="32" />
+  <parameter name="alwaysDoMaxBurst" value="true" />
+  <parameter name="avalonMMByteReorderMode" value="0" />
+  <parameter name="dataTransferFIFODepth" value="2" />
+  <parameter name="enableBurstTransfers" value="false" />
+  <parameter name="enableDescriptorReadMasterBurst" value="false" />
+  <parameter name="enableUnalignedTransfers" value="false" />
+  <parameter name="internalFIFODepth" value="2" />
+  <parameter name="readBlockDataWidth" value="32" />
+  <parameter name="readBurstcountWidth" value="4" />
+  <parameter name="sinkErrorWidth" value="0" />
+  <parameter name="sourceErrorWidth" value="0" />
+  <parameter name="transferMode" value="MEMORY_TO_STREAM" />
+  <parameter name="writeBurstcountWidth" value="4" />
+  <parameter name="deviceFamilyString" value="Arria V" />
+ </module>
+ <module
+   kind="altera_avalon_onchip_memory2"
+   version="14.0"
+   enabled="1"
+   name="sys_ethernet_desc_mem">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="dualPort" value="false" />
+  <parameter name="initMemContent" value="true" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="4096" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="autoInitializationFileName">$${FILENAME}_sys_ethernet_desc_mem</parameter>
+  <parameter name="deviceFamily" value="Arria V" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ </module>
+ <module kind="altera_avalon_pio" version="14.0" enabled="1" name="sys_gpio">
+  <parameter name="bitClearingEdgeCapReg" value="false" />
+  <parameter name="bitModifyingOutReg" value="false" />
+  <parameter name="captureEdge" value="false" />
+  <parameter name="direction" value="InOut" />
+  <parameter name="edgeType" value="RISING" />
+  <parameter name="generateIRQ" value="true" />
+  <parameter name="irqType" value="LEVEL" />
+  <parameter name="resetValue" value="0" />
+  <parameter name="simDoTestBenchWiring" value="false" />
+  <parameter name="simDrivenValue" value="0" />
+  <parameter name="width" value="32" />
+  <parameter name="clockRate" value="100000000" />
+ </module>
+ <module kind="altera_avalon_spi" version="14.0" enabled="1" name="sys_spi">
+  <parameter name="clockPhase" value="0" />
+  <parameter name="clockPolarity" value="0" />
+  <parameter name="dataWidth" value="8" />
+  <parameter name="disableAvalonFlowControl" value="false" />
+  <parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
+  <parameter name="insertSync" value="false" />
+  <parameter name="lsbOrderedFirst" value="false" />
+  <parameter name="masterSPI" value="true" />
+  <parameter name="numberOfSlaves" value="5" />
+  <parameter name="syncRegDepth" value="2" />
+  <parameter name="targetClockRate" value="12500000" />
+  <parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
+  <parameter name="avalonSpec" value="2.0" />
+  <parameter name="inputClockRate" value="100000000" />
+ </module>
+ <module kind="axi_dmac" version="1.0" enabled="1" name="axi_dmac">
+  <parameter name="PCORE_ID" value="0" />
+  <parameter name="C_DMA_DATA_WIDTH_SRC" value="512" />
+  <parameter name="C_DMA_DATA_WIDTH_DEST" value="128" />
+  <parameter name="C_DMA_LENGTH_WIDTH" value="23" />
+  <parameter name="C_2D_TRANSFER" value="1" />
+  <parameter name="C_CLKS_ASYNC_REQ_SRC" value="1" />
+  <parameter name="C_CLKS_ASYNC_SRC_DEST" value="1" />
+  <parameter name="C_CLKS_ASYNC_DEST_REQ" value="1" />
+  <parameter name="C_AXI_SLICE_DEST" value="0" />
+  <parameter name="C_AXI_SLICE_SRC" value="0" />
+  <parameter name="C_SYNC_TRANSFER_START" value="0" />
+  <parameter name="C_CYCLIC" value="1" />
+  <parameter name="C_DMA_TYPE_DEST" value="0" />
+  <parameter name="C_DMA_TYPE_SRC" value="2" />
+  <parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="166666666" />
+ </module>
+ <module
+   kind="altera_jesd204"
+   version="14.0"
+   enabled="1"
+   name="sys_jesd204b_s1">
+  <parameter name="wrapper_opt" value="base_phy" />
+  <parameter name="sdc_constraint" value="1.0" />
+  <parameter name="DEVICE_FAMILY" value="Arria V" />
+  <parameter name="DATA_PATH" value="RX" />
+  <parameter name="SUBCLASSV" value="0" />
+  <parameter name="lane_rate" value="3200.0" />
+  <parameter name="PCS_CONFIG" value="JESD_PCS_CFG1" />
+  <parameter name="pll_type" value="CMU" />
+  <parameter name="bonded_mode" value="bonded" />
+  <parameter name="REFCLK_FREQ" value="80.0" />
+  <parameter name="pll_reconfig_enable" value="false" />
+  <parameter name="bitrev_en" value="false" />
+  <parameter name="L" value="8" />
+  <parameter name="M" value="32" />
+  <parameter name="N" value="14" />
+  <parameter name="N_PRIME" value="16" />
+  <parameter name="S" value="1" />
+  <parameter name="K" value="4" />
+  <parameter name="SCR" value="1" />
+  <parameter name="CS" value="0" />
+  <parameter name="CF" value="0" />
+  <parameter name="HD" value="0" />
+  <parameter name="ECC_EN" value="0" />
+  <parameter name="DLB_TEST" value="0" />
+  <parameter name="PHADJ" value="0" />
+  <parameter name="ADJCNT" value="0" />
+  <parameter name="ADJDIR" value="0" />
+  <parameter name="OPTIMIZE" value="0" />
+  <parameter name="DID" value="0" />
+  <parameter name="BID" value="0" />
+  <parameter name="LID0" value="0" />
+  <parameter name="LID1" value="1" />
+  <parameter name="LID2" value="2" />
+  <parameter name="LID3" value="3" />
+  <parameter name="LID4" value="4" />
+  <parameter name="LID5" value="5" />
+  <parameter name="LID6" value="6" />
+  <parameter name="LID7" value="7" />
+  <parameter name="JESDV" value="1" />
+  <parameter name="RES1" value="0" />
+  <parameter name="RES2" value="0" />
+  <parameter name="TEST_COMPONENTS_EN" value="false" />
+  <parameter name="TERMINATE_RECONFIG_EN" value="false" />
+  <parameter name="AUTO_DEVICE" value="5AGTFD7K3F40I3" />
+ </module>
+ <module
+   kind="altera_clock_bridge"
+   version="14.0"
+   enabled="1"
+   name="sys_jesd204b_s1_rx_clk">
+  <parameter name="DERIVED_CLOCK_RATE" value="80000000" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module
+   kind="altera_pll"
+   version="14.0"
+   enabled="1"
+   name="sys_jesd204b_s1_pll">
+  <parameter name="debug_print_output" value="false" />
+  <parameter name="debug_use_rbc_taf_method" value="false" />
+  <parameter name="device_family" value="Arria V" />
+  <parameter name="device" value="5AGTFD7K3F40I3" />
+  <parameter name="gui_device_speed_grade" value="2" />
+  <parameter name="gui_pll_mode" value="Integer-N PLL" />
+  <parameter name="gui_reference_clock_frequency" value="80.0" />
+  <parameter name="gui_channel_spacing" value="0.0" />
+  <parameter name="gui_operation_mode" value="direct" />
+  <parameter name="gui_feedback_clock" value="Global Clock" />
+  <parameter name="gui_fractional_cout" value="32" />
+  <parameter name="gui_dsm_out_sel" value="1st_order" />
+  <parameter name="gui_use_locked" value="true" />
+  <parameter name="gui_en_adv_params" value="false" />
+  <parameter name="gui_number_of_clocks" value="1" />
+  <parameter name="gui_multiply_factor" value="1" />
+  <parameter name="gui_frac_multiply_factor" value="1" />
+  <parameter name="gui_divide_factor_n" value="1" />
+  <parameter name="gui_cascade_counter0" value="false" />
+  <parameter name="gui_output_clock_frequency0" value="80.0" />
+  <parameter name="gui_divide_factor_c0" value="1" />
+  <parameter name="gui_actual_output_clock_frequency0" value="0 MHz" />
+  <parameter name="gui_ps_units0" value="ps" />
+  <parameter name="gui_phase_shift0" value="0" />
+  <parameter name="gui_phase_shift_deg0" value="0.0" />
+  <parameter name="gui_actual_phase_shift0" value="0" />
+  <parameter name="gui_duty_cycle0" value="50" />
+  <parameter name="gui_cascade_counter1" value="false" />
+  <parameter name="gui_output_clock_frequency1" value="100.0" />
+  <parameter name="gui_divide_factor_c1" value="1" />
+  <parameter name="gui_actual_output_clock_frequency1" value="0 MHz" />
+  <parameter name="gui_ps_units1" value="ps" />
+  <parameter name="gui_phase_shift1" value="0" />
+  <parameter name="gui_phase_shift_deg1" value="0.0" />
+  <parameter name="gui_actual_phase_shift1" value="0" />
+  <parameter name="gui_duty_cycle1" value="50" />
+  <parameter name="gui_cascade_counter2" value="false" />
+  <parameter name="gui_output_clock_frequency2" value="100.0" />
+  <parameter name="gui_divide_factor_c2" value="1" />
+  <parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
+  <parameter name="gui_ps_units2" value="ps" />
+  <parameter name="gui_phase_shift2" value="0" />
+  <parameter name="gui_phase_shift_deg2" value="0.0" />
+  <parameter name="gui_actual_phase_shift2" value="0" />
+  <parameter name="gui_duty_cycle2" value="50" />
+  <parameter name="gui_cascade_counter3" value="false" />
+  <parameter name="gui_output_clock_frequency3" value="100.0" />
+  <parameter name="gui_divide_factor_c3" value="1" />
+  <parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
+  <parameter name="gui_ps_units3" value="ps" />
+  <parameter name="gui_phase_shift3" value="0" />
+  <parameter name="gui_phase_shift_deg3" value="0.0" />
+  <parameter name="gui_actual_phase_shift3" value="0" />
+  <parameter name="gui_duty_cycle3" value="50" />
+  <parameter name="gui_cascade_counter4" value="false" />
+  <parameter name="gui_output_clock_frequency4" value="100.0" />
+  <parameter name="gui_divide_factor_c4" value="1" />
+  <parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
+  <parameter name="gui_ps_units4" value="ps" />
+  <parameter name="gui_phase_shift4" value="0" />
+  <parameter name="gui_phase_shift_deg4" value="0.0" />
+  <parameter name="gui_actual_phase_shift4" value="0" />
+  <parameter name="gui_duty_cycle4" value="50" />
+  <parameter name="gui_cascade_counter5" value="false" />
+  <parameter name="gui_output_clock_frequency5" value="100.0" />
+  <parameter name="gui_divide_factor_c5" value="1" />
+  <parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
+  <parameter name="gui_ps_units5" value="ps" />
+  <parameter name="gui_phase_shift5" value="0" />
+  <parameter name="gui_phase_shift_deg5" value="0.0" />
+  <parameter name="gui_actual_phase_shift5" value="0" />
+  <parameter name="gui_duty_cycle5" value="50" />
+  <parameter name="gui_cascade_counter6" value="false" />
+  <parameter name="gui_output_clock_frequency6" value="100.0" />
+  <parameter name="gui_divide_factor_c6" value="1" />
+  <parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
+  <parameter name="gui_ps_units6" value="ps" />
+  <parameter name="gui_phase_shift6" value="0" />
+  <parameter name="gui_phase_shift_deg6" value="0.0" />
+  <parameter name="gui_actual_phase_shift6" value="0" />
+  <parameter name="gui_duty_cycle6" value="50" />
+  <parameter name="gui_cascade_counter7" value="false" />
+  <parameter name="gui_output_clock_frequency7" value="100.0" />
+  <parameter name="gui_divide_factor_c7" value="1" />
+  <parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
+  <parameter name="gui_ps_units7" value="ps" />
+  <parameter name="gui_phase_shift7" value="0" />
+  <parameter name="gui_phase_shift_deg7" value="0.0" />
+  <parameter name="gui_actual_phase_shift7" value="0" />
+  <parameter name="gui_duty_cycle7" value="50" />
+  <parameter name="gui_cascade_counter8" value="false" />
+  <parameter name="gui_output_clock_frequency8" value="100.0" />
+  <parameter name="gui_divide_factor_c8" value="1" />
+  <parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
+  <parameter name="gui_ps_units8" value="ps" />
+  <parameter name="gui_phase_shift8" value="0" />
+  <parameter name="gui_phase_shift_deg8" value="0.0" />
+  <parameter name="gui_actual_phase_shift8" value="0" />
+  <parameter name="gui_duty_cycle8" value="50" />
+  <parameter name="gui_cascade_counter9" value="false" />
+  <parameter name="gui_output_clock_frequency9" value="100.0" />
+  <parameter name="gui_divide_factor_c9" value="1" />
+  <parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
+  <parameter name="gui_ps_units9" value="ps" />
+  <parameter name="gui_phase_shift9" value="0" />
+  <parameter name="gui_phase_shift_deg9" value="0.0" />
+  <parameter name="gui_actual_phase_shift9" value="0" />
+  <parameter name="gui_duty_cycle9" value="50" />
+  <parameter name="gui_cascade_counter10" value="false" />
+  <parameter name="gui_output_clock_frequency10" value="100.0" />
+  <parameter name="gui_divide_factor_c10" value="1" />
+  <parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
+  <parameter name="gui_ps_units10" value="ps" />
+  <parameter name="gui_phase_shift10" value="0" />
+  <parameter name="gui_phase_shift_deg10" value="0.0" />
+  <parameter name="gui_actual_phase_shift10" value="0" />
+  <parameter name="gui_duty_cycle10" value="50" />
+  <parameter name="gui_cascade_counter11" value="false" />
+  <parameter name="gui_output_clock_frequency11" value="100.0" />
+  <parameter name="gui_divide_factor_c11" value="1" />
+  <parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
+  <parameter name="gui_ps_units11" value="ps" />
+  <parameter name="gui_phase_shift11" value="0" />
+  <parameter name="gui_phase_shift_deg11" value="0.0" />
+  <parameter name="gui_actual_phase_shift11" value="0" />
+  <parameter name="gui_duty_cycle11" value="50" />
+  <parameter name="gui_cascade_counter12" value="false" />
+  <parameter name="gui_output_clock_frequency12" value="100.0" />
+  <parameter name="gui_divide_factor_c12" value="1" />
+  <parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
+  <parameter name="gui_ps_units12" value="ps" />
+  <parameter name="gui_phase_shift12" value="0" />
+  <parameter name="gui_phase_shift_deg12" value="0.0" />
+  <parameter name="gui_actual_phase_shift12" value="0" />
+  <parameter name="gui_duty_cycle12" value="50" />
+  <parameter name="gui_cascade_counter13" value="false" />
+  <parameter name="gui_output_clock_frequency13" value="100.0" />
+  <parameter name="gui_divide_factor_c13" value="1" />
+  <parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
+  <parameter name="gui_ps_units13" value="ps" />
+  <parameter name="gui_phase_shift13" value="0" />
+  <parameter name="gui_phase_shift_deg13" value="0.0" />
+  <parameter name="gui_actual_phase_shift13" value="0" />
+  <parameter name="gui_duty_cycle13" value="50" />
+  <parameter name="gui_cascade_counter14" value="false" />
+  <parameter name="gui_output_clock_frequency14" value="100.0" />
+  <parameter name="gui_divide_factor_c14" value="1" />
+  <parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
+  <parameter name="gui_ps_units14" value="ps" />
+  <parameter name="gui_phase_shift14" value="0" />
+  <parameter name="gui_phase_shift_deg14" value="0.0" />
+  <parameter name="gui_actual_phase_shift14" value="0" />
+  <parameter name="gui_duty_cycle14" value="50" />
+  <parameter name="gui_cascade_counter15" value="false" />
+  <parameter name="gui_output_clock_frequency15" value="100.0" />
+  <parameter name="gui_divide_factor_c15" value="1" />
+  <parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
+  <parameter name="gui_ps_units15" value="ps" />
+  <parameter name="gui_phase_shift15" value="0" />
+  <parameter name="gui_phase_shift_deg15" value="0.0" />
+  <parameter name="gui_actual_phase_shift15" value="0" />
+  <parameter name="gui_duty_cycle15" value="50" />
+  <parameter name="gui_cascade_counter16" value="false" />
+  <parameter name="gui_output_clock_frequency16" value="100.0" />
+  <parameter name="gui_divide_factor_c16" value="1" />
+  <parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
+  <parameter name="gui_ps_units16" value="ps" />
+  <parameter name="gui_phase_shift16" value="0" />
+  <parameter name="gui_phase_shift_deg16" value="0.0" />
+  <parameter name="gui_actual_phase_shift16" value="0" />
+  <parameter name="gui_duty_cycle16" value="50" />
+  <parameter name="gui_cascade_counter17" value="false" />
+  <parameter name="gui_output_clock_frequency17" value="100.0" />
+  <parameter name="gui_divide_factor_c17" value="1" />
+  <parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
+  <parameter name="gui_ps_units17" value="ps" />
+  <parameter name="gui_phase_shift17" value="0" />
+  <parameter name="gui_phase_shift_deg17" value="0.0" />
+  <parameter name="gui_actual_phase_shift17" value="0" />
+  <parameter name="gui_duty_cycle17" value="50" />
+  <parameter name="gui_pll_auto_reset" value="Off" />
+  <parameter name="gui_pll_bandwidth_preset" value="Auto" />
+  <parameter name="gui_en_reconf" value="false" />
+  <parameter name="gui_en_dps_ports" value="false" />
+  <parameter name="gui_en_phout_ports" value="false" />
+  <parameter name="gui_phout_division" value="1" />
+  <parameter name="gui_en_lvds_ports" value="false" />
+  <parameter name="gui_mif_generate" value="false" />
+  <parameter name="gui_enable_mif_dps" value="false" />
+  <parameter name="gui_dps_cntr" value="C0" />
+  <parameter name="gui_dps_num" value="1" />
+  <parameter name="gui_dps_dir" value="Positive" />
+  <parameter name="gui_refclk_switch" value="false" />
+  <parameter name="gui_refclk1_frequency" value="100.0" />
+  <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+  <parameter name="gui_switchover_delay" value="0" />
+  <parameter name="gui_active_clk" value="false" />
+  <parameter name="gui_clk_bad" value="false" />
+  <parameter name="gui_enable_cascade_out" value="false" />
+  <parameter name="gui_cascade_outclk_index" value="0" />
+  <parameter name="gui_enable_cascade_in" value="false" />
+  <parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
+  <parameter name="AUTO_REFCLK_CLOCK_RATE" value="80000000" />
+ </module>
+ <module
+   kind="altera_clock_bridge"
+   version="14.0"
+   enabled="1"
+   name="sys_jesd204b_s1_ref_clk">
+  <parameter name="DERIVED_CLOCK_RATE" value="0" />
+  <parameter name="EXPLICIT_CLOCK_RATE" value="80000000" />
+  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
+ </module>
+ <module
+   kind="altera_address_span_extender"
+   version="14.0"
+   enabled="1"
+   name="sys_ddr3_cpuconnect">
+  <parameter name="DATA_WIDTH" value="512" />
+  <parameter name="MASTER_ADDRESS_WIDTH" value="30" />
+  <parameter name="SLAVE_ADDRESS_WIDTH" value="20" />
+  <parameter name="BURSTCOUNT_WIDTH" value="1" />
+  <parameter name="SUB_WINDOW_COUNT" value="1" />
+  <parameter name="MASTER_ADDRESS_DEF" value="0" />
+  <parameter name="TERMINATE_SLAVE_PORT" value="false" />
+  <parameter name="MAX_PENDING_READS" value="1" />
+  <parameter name="AUTO_CLOCK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
+ </module>
+ <module
+   kind="altera_avalon_mm_clock_crossing_bridge"
+   version="14.0"
+   enabled="1"
+   name="sys_ddr3_dmaconnect">
+  <parameter name="DATA_WIDTH" value="512" />
+  <parameter name="SYMBOL_WIDTH" value="8" />
+  <parameter name="ADDRESS_WIDTH" value="30" />
+  <parameter name="SYSINFO_ADDR_WIDTH" value="30" />
+  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
+  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
+  <parameter name="MAX_BURST_SIZE" value="1" />
+  <parameter name="COMMAND_FIFO_DEPTH" value="4" />
+  <parameter name="RESPONSE_FIFO_DEPTH" value="4" />
+  <parameter name="MASTER_SYNC_DEPTH" value="2" />
+  <parameter name="SLAVE_SYNC_DEPTH" value="2" />
+  <parameter name="AUTO_M0_CLK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_S0_CLK_CLOCK_RATE" value="166666666" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Arria V" />
+ </module>
+ <module
+   kind="altera_avalon_onchip_memory2"
+   version="14.0"
+   enabled="1"
+   name="sys_tcm_mem">
+  <parameter name="allowInSystemMemoryContentEditor" value="false" />
+  <parameter name="blockType" value="AUTO" />
+  <parameter name="dataWidth" value="32" />
+  <parameter name="dualPort" value="true" />
+  <parameter name="initMemContent" value="true" />
+  <parameter name="initializationFileName" value="onchip_mem.hex" />
+  <parameter name="instanceID" value="NONE" />
+  <parameter name="memorySize" value="4096" />
+  <parameter name="readDuringWriteMode" value="DONT_CARE" />
+  <parameter name="simAllowMRAMContentsFile" value="false" />
+  <parameter name="simMemInitOnlyFilename" value="0" />
+  <parameter name="singleClockOperation" value="false" />
+  <parameter name="slave1Latency" value="1" />
+  <parameter name="slave2Latency" value="1" />
+  <parameter name="useNonDefaultInitFile" value="false" />
+  <parameter name="useShallowMemBlocks" value="false" />
+  <parameter name="writable" value="true" />
+  <parameter name="ecc_enabled" value="false" />
+  <parameter name="resetrequest_enabled" value="true" />
+  <parameter name="autoInitializationFileName">$${FILENAME}_sys_tcm_mem</parameter>
+  <parameter name="deviceFamily" value="Arria V" />
+  <parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ </module>
+ <module kind="axi_ad9671" version="1.0" enabled="1" name="axi_ad9671_0">
+  <parameter name="PCORE_ID" value="0" />
+  <parameter name="PCORE_DEVICE_TYPE" value="0" />
+  <parameter name="PCORE_4L_2L_N" value="0" />
+  <parameter name="PCORE_AXI_ID_WIDTH" value="3" />
+  <parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_XCVR_CLK_CLOCK_RATE" value="0" />
+ </module>
+ <module kind="axi_ad9671" version="1.0" enabled="1" name="axi_ad9671_1">
+  <parameter name="PCORE_ID" value="0" />
+  <parameter name="PCORE_DEVICE_TYPE" value="0" />
+  <parameter name="PCORE_4L_2L_N" value="0" />
+  <parameter name="PCORE_AXI_ID_WIDTH" value="3" />
+  <parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_XCVR_CLK_CLOCK_RATE" value="0" />
+ </module>
+ <module kind="axi_ad9671" version="1.0" enabled="1" name="axi_ad9671_2">
+  <parameter name="PCORE_ID" value="0" />
+  <parameter name="PCORE_DEVICE_TYPE" value="0" />
+  <parameter name="PCORE_4L_2L_N" value="0" />
+  <parameter name="PCORE_AXI_ID_WIDTH" value="3" />
+  <parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_XCVR_CLK_CLOCK_RATE" value="0" />
+ </module>
+ <module kind="axi_ad9671" version="1.0" enabled="1" name="axi_ad9671_3">
+  <parameter name="PCORE_ID" value="0" />
+  <parameter name="PCORE_DEVICE_TYPE" value="0" />
+  <parameter name="PCORE_4L_2L_N" value="0" />
+  <parameter name="PCORE_AXI_ID_WIDTH" value="3" />
+  <parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="100000000" />
+  <parameter name="AUTO_XCVR_CLK_CLOCK_RATE" value="0" />
+ </module>
+ <connection kind="clock" version="14.0" start="sys_clk.clk" end="sys_pll.refclk" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_pll.reset" />
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.instruction_master"
+   end="sys_cpu.jtag_debug_module">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x05209800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.data_master"
+   end="sys_cpu.jtag_debug_module">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x05209800" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="14.0" start="sys_pll.outclk0" end="sys_cpu.clk" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_cpu.reset_n" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk0"
+   end="sys_int_mem.clk1" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk0"
+   end="sys_int_mem.clk2" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_int_mem.reset1" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_int_mem.reset2" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_ddr3_cntrl.soft_reset" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_ddr3_cntrl.afi_clk"
+   end="sys_ddr3_interconnect.m0_clk" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_ddr3_cntrl.afi_reset"
+   end="sys_ddr3_interconnect.m0_reset" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_ddr3_interconnect.s0_reset" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk0"
+   end="sys_ddr3_interconnect.s0_clk" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk0"
+   end="sys_uart.clk" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_uart.reset" />
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.data_master"
+   end="sys_uart.avalon_jtag_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0520a4e0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk0"
+   end="sys_timer.clk" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_timer.reset" />
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.data_master"
+   end="sys_timer.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0520a4a0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="14.0" start="sys_pll.outclk0" end="sys_id.clk" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_id.reset" />
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.data_master"
+   end="sys_id.control_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0520a4d8" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk0"
+   end="sys_ethernet.control_port_clock_connection" />
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.data_master"
+   end="sys_ethernet.control_port">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0520a000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_ethernet.reset_connection" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk0"
+   end="sys_ethernet.receive_clock_connection" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk0"
+   end="sys_ethernet.transmit_clock_connection" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk0"
+   end="sys_ethernet_dma_rx.clk" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_ethernet_dma_rx.reset" />
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_rx.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0520a440" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon_streaming"
+   version="14.0"
+   start="sys_ethernet.receive"
+   end="sys_ethernet_dma_rx.in" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk0"
+   end="sys_ethernet_dma_tx.clk" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_ethernet_dma_tx.reset" />
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.data_master"
+   end="sys_ethernet_dma_tx.csr">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0520a400" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon_streaming"
+   version="14.0"
+   start="sys_ethernet_dma_tx.out"
+   end="sys_ethernet.transmit" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_ethernet_desc_mem.reset1" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk0"
+   end="sys_ethernet_desc_mem.clk1" />
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_ethernet_dma_tx.descriptor_write"
+   end="sys_ethernet_desc_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_ethernet_dma_tx.descriptor_read"
+   end="sys_ethernet_desc_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_ethernet_dma_rx.descriptor_write"
+   end="sys_ethernet_desc_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_ethernet_dma_rx.descriptor_read"
+   end="sys_ethernet_desc_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk0"
+   end="sys_gpio.clk" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_gpio.reset" />
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.data_master"
+   end="sys_gpio.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0520a4c0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.data_master"
+   end="sys_spi.spi_control_port">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0520a480" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="clock" version="14.0" start="sys_pll.outclk0" end="sys_spi.clk" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_spi.reset" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="axi_dmac.s_axi_reset" />
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.data_master"
+   end="axi_dmac.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x05204000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_ddr3_cntrl.afi_reset"
+   end="axi_dmac.m_dest_axi_reset" />
+ <connection
+   kind="interrupt"
+   version="14.0"
+   start="sys_cpu.d_irq"
+   end="sys_ethernet_dma_rx.csr_irq">
+  <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="14.0"
+   start="sys_cpu.d_irq"
+   end="sys_ethernet_dma_tx.csr_irq">
+  <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="14.0"
+   start="sys_cpu.d_irq"
+   end="sys_uart.irq">
+  <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="14.0"
+   start="sys_cpu.d_irq"
+   end="sys_timer.irq">
+  <parameter name="irqNumber" value="3" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="14.0"
+   start="sys_cpu.d_irq"
+   end="sys_spi.irq">
+  <parameter name="irqNumber" value="4" />
+ </connection>
+ <connection
+   kind="interrupt"
+   version="14.0"
+   start="sys_cpu.d_irq"
+   end="sys_gpio.irq">
+  <parameter name="irqNumber" value="5" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_ddr3_interconnect.m0"
+   end="sys_ddr3_cntrl.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_ethernet_dma_rx.m_write"
+   end="sys_ddr3_interconnect.s0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_ethernet_dma_tx.m_read"
+   end="sys_ddr3_interconnect.s0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_jesd204b_s1.jesd204_rx_avs_rst_n" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_jesd204b_s1.rxlink_rst_n" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_ddr3_cntrl.global_reset" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_jesd204b_s1_ref_clk.out_clk"
+   end="sys_jesd204b_s1.pll_ref_clk" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_jesd204b_s1_ref_clk.out_clk"
+   end="sys_jesd204b_s1_pll.refclk" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_jesd204b_s1_pll.reset" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_jesd204b_s1_pll.outclk0"
+   end="sys_jesd204b_s1.rxlink_clk" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_jesd204b_s1_pll.outclk0"
+   end="sys_jesd204b_s1_rx_clk.in_clk" />
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.data_master"
+   end="sys_int_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x05000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.instruction_master"
+   end="sys_int_mem.s2">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x05000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.data_master"
+   end="sys_ddr3_cpuconnect.windowed_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.instruction_master"
+   end="sys_ddr3_cpuconnect.windowed_slave">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_ddr3_cpuconnect.expanded_master"
+   end="sys_ddr3_interconnect.s0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk0"
+   end="sys_ddr3_cpuconnect.clock" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_ddr3_cpuconnect.reset" />
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.data_master"
+   end="sys_ddr3_cpuconnect.cntl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0520a4d0" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_clk.clk"
+   end="sys_ddr3_cntrl.pll_ref_clk" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="axi_dmac.m_dest_axi_reset" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk1"
+   end="axi_dmac.m_dest_axi_clock" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk1"
+   end="sys_ddr3_dmaconnect.s0_clk" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_ddr3_dmaconnect.s0_reset" />
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="axi_dmac.m_dest_axi"
+   end="sys_ddr3_dmaconnect.s0">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_ddr3_cntrl.afi_reset"
+   end="sys_ddr3_dmaconnect.m0_reset" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_ddr3_cntrl.afi_clk"
+   end="sys_ddr3_dmaconnect.m0_clk" />
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_ddr3_dmaconnect.m0"
+   end="sys_ddr3_cntrl.avl">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x0000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk0"
+   end="sys_tcm_mem.clk1" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk0"
+   end="sys_tcm_mem.clk2" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_tcm_mem.reset1" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="sys_tcm_mem.reset2" />
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.tightly_coupled_data_master_0"
+   end="sys_tcm_mem.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x05208000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.tightly_coupled_instruction_master_0"
+   end="sys_tcm_mem.s2">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x05208000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk0"
+   end="axi_ad9671_0.s_axi_clock" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="axi_ad9671_0.s_axi_reset" />
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.data_master"
+   end="axi_ad9671_0.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x05200000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk0"
+   end="axi_ad9671_1.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk0"
+   end="axi_ad9671_2.s_axi_clock" />
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk0"
+   end="axi_ad9671_3.s_axi_clock" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="axi_ad9671_1.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="axi_ad9671_2.s_axi_reset" />
+ <connection
+   kind="reset"
+   version="14.0"
+   start="sys_clk.clk_reset"
+   end="axi_ad9671_3.s_axi_reset" />
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.data_master"
+   end="axi_ad9671_1.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x05210000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.data_master"
+   end="axi_ad9671_2.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x05220000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.data_master"
+   end="axi_ad9671_3.s_axi">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x05230000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk1"
+   end="axi_dmac.s_axi_clock" />
+ <connection
+   kind="avalon"
+   version="14.0"
+   start="sys_cpu.data_master"
+   end="sys_jesd204b_s1.jesd204_rx_avs">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x04000000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+   kind="clock"
+   version="14.0"
+   start="sys_pll.outclk0"
+   end="sys_jesd204b_s1.jesd204_rx_avs_clk" />
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
+</system>
diff --git a/projects/usdrx1/a5gt/system_constr.sdc b/projects/usdrx1/a5gt/system_constr.sdc
new file mode 100644
index 000000000..162bc6cde
--- /dev/null
+++ b/projects/usdrx1/a5gt/system_constr.sdc
@@ -0,0 +1,34 @@
+
+create_clock -period "10.000 ns" -name n_clk_100m [get_ports {sys_clk}]
+create_clock -period "12.500 ns" -name n_clk_80m [get_ports {ref_clk}]
+create_clock -period "8.000 ns" -name n_eth_rx_clk_125m [get_ports {eth_rx_clk}]
+create_clock -period "8.000 ns" -name n_eth_tx_clk_125m [get_nets {eth_tx_clk}]
+#create_clock -period "80.000 ns" -name spi_clk [get_nets {system_bd:i_system_bd|system_bd_sys_spi:sys_spi|SCLK_reg}]
+
+
+derive_pll_clocks
+derive_clock_uncertainty
+
+set clk_100m    [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
+set clk_166m    [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}]
+set clk_125m    [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
+set clk_25m     [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]
+set clk_2m5     [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}]
+set clk_rxlink  [get_clocks {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
+
+set_false_path -from {sys_resetn} -to *
+set_false_path -from $clk_100m -to $clk_166m
+set_false_path -from $clk_100m -to $clk_rxlink
+set_false_path -from $clk_166m -to $clk_100m
+set_false_path -from $clk_166m -to $clk_rxlink
+set_false_path -from $clk_rxlink -to $clk_100m
+set_false_path -from $clk_rxlink -to $clk_166m
+
+set_false_path -from $clk_125m -to $clk_25m
+set_false_path -from $clk_125m -to $clk_2m5
+set_false_path -from $clk_25m -to $clk_125m
+set_false_path -from $clk_25m -to $clk_2m5
+set_false_path -from $clk_2m5 -to $clk_125m
+set_false_path -from $clk_2m5 -to $clk_25m
+
+
diff --git a/projects/usdrx1/a5gt/system_project.tcl b/projects/usdrx1/a5gt/system_project.tcl
new file mode 100644
index 000000000..8bf4232aa
--- /dev/null
+++ b/projects/usdrx1/a5gt/system_project.tcl
@@ -0,0 +1,167 @@
+
+load_package flow
+
+source ../../scripts/adi_env.tcl
+project_new usdrx1_a5gt -overwrite
+
+source $ad_hdl_dir/projects/common/a5gt/a5gt_system_assign.tcl
+
+set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_jesd_align.v
+set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_xcvr_rx_rst.v
+set_global_assignment -name VERILOG_FILE ../common/usdrx1_spi.v
+
+# reference clock
+
+set_location_assignment PIN_AB9   -to ref_clk
+set_location_assignment PIN_AB8   -to "ref_clk(n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to ref_clk
+set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION AC_COUPLING -to ref_clk
+set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to ref_clk
+
+# lane data
+
+set_location_assignment PIN_AE1   -to rx_data[0]
+set_location_assignment PIN_AE2   -to "rx_data[0](n)"
+set_location_assignment PIN_AA1    -to rx_data[1]
+set_location_assignment PIN_AA2   -to "rx_data[1](n)"
+set_location_assignment PIN_U1    -to rx_data[2]
+set_location_assignment PIN_U2    -to "rx_data[2](n)"
+set_location_assignment PIN_R1    -to rx_data[3]
+set_location_assignment PIN_R2    -to "rx_data[3](n)"
+set_location_assignment PIN_J1    -to rx_data[4]
+set_location_assignment PIN_J2    -to "rx_data[4](n)"
+set_location_assignment PIN_N1    -to rx_data[5]
+set_location_assignment PIN_N2    -to "rx_data[5](n)"
+set_location_assignment PIN_L1    -to rx_data[6]
+set_location_assignment PIN_L2    -to "rx_data[6](n)"
+set_location_assignment PIN_G1    -to rx_data[7]
+set_location_assignment PIN_G2    -to "rx_data[7](n)"
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[0]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[1]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[2]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[3]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[4]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[5]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[6]
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to rx_data[7]
+set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[0]
+set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[1]
+set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[2]
+set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[3]
+set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[4]
+set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[5]
+set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[6]
+set_instance_assignment -name XCVR_IO_PIN_TERMINATION 100_OHMS -to rx_data[7]
+
+# jesd signals
+
+set_location_assignment PIN_AL22   -to rx_sync
+set_location_assignment PIN_AK22   -to "rx_sync(n)"
+set_instance_assignment -name IO_STANDARD LVDS -to rx_sync
+
+set_location_assignment PIN_AW18   -to rx_sysref
+set_location_assignment PIN_AV18   -to "rx_sysref(n)"
+set_instance_assignment -name IO_STANDARD LVDS -to rx_sysref
+
+set_location_assignment PIN_AL23   -to afe_rst
+set_location_assignment PIN_AK23   -to "afe_rst(n)"
+set_instance_assignment -name IO_STANDARD LVDS -to afe_rst
+
+set_location_assignment PIN_AK25   -to afe_trig
+set_location_assignment PIN_AJ25   -to "afe_trig(n)"
+set_instance_assignment -name IO_STANDARD LVDS -to afe_trig
+
+# spi
+
+set_location_assignment PIN_AM9   -to spi_fout_clk
+set_location_assignment PIN_AL9   -to spi_fout_sdio
+set_location_assignment PIN_AV6   -to spi_fout_enb_clk
+set_location_assignment PIN_AV7   -to spi_fout_enb_mlo
+set_location_assignment PIN_AU13  -to spi_fout_enb_rst
+set_location_assignment PIN_AT13  -to spi_fout_enb_sync
+set_location_assignment PIN_AD16  -to spi_fout_enb_sysref
+set_location_assignment PIN_AC16  -to spi_fout_enb_trig
+set_location_assignment PIN_AW13  -to spi_afe_clk
+set_location_assignment PIN_AV13  -to spi_afe_sdio
+set_location_assignment PIN_AP7   -to spi_afe_csn[0]
+set_location_assignment PIN_AN7   -to spi_afe_csn[1]
+set_location_assignment PIN_AH17  -to spi_afe_csn[2]
+set_location_assignment PIN_AG17  -to spi_afe_csn[3]
+set_location_assignment PIN_AW14  -to spi_clk_csn
+set_location_assignment PIN_AN9   -to spi_clk_clk
+set_location_assignment PIN_AP9   -to spi_clk_sdio
+set_location_assignment PIN_AJ16  -to clk_resetn
+set_location_assignment PIN_AK16  -to clk_syncn
+set_location_assignment PIN_AL24  -to clk_status
+
+set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_fout_enb_clk
+set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_fout_enb_mlo
+set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_fout_enb_rst
+set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_fout_enb_sync
+set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_fout_enb_sysref
+set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_fout_enb_trig
+set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_fout_clk
+set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_fout_sdio
+set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_afe_csn[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_afe_csn[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_afe_csn[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_afe_csn[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_afe_clk
+set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_afe_sdio
+set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_clk_csn
+set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_clk_clk
+set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_clk_sdio
+set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_resetn
+set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_syncn
+set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_status
+
+# gpio
+
+set_location_assignment PIN_AL14  -to afe_pdn
+set_location_assignment PIN_AK14  -to afe_stby
+set_location_assignment PIN_AK24  -to amp_disbn
+set_location_assignment PIN_AT16  -to prc_sck
+set_location_assignment PIN_AR16  -to prc_cnv
+set_location_assignment PIN_AC22  -to prc_sdo_i
+set_location_assignment PIN_AD21  -to prc_sdo_q
+set_location_assignment PIN_AW15  -to dac_sleep
+set_location_assignment PIN_AG22  -to dac_data[0]
+set_location_assignment PIN_AH22  -to dac_data[1]
+set_location_assignment PIN_AV22  -to dac_data[2]
+set_location_assignment PIN_AW22  -to dac_data[3]
+set_location_assignment PIN_AL16  -to dac_data[4]
+set_location_assignment PIN_AM16  -to dac_data[5]
+set_location_assignment PIN_AK15  -to dac_data[6]
+set_location_assignment PIN_AL15  -to dac_data[7]
+set_location_assignment PIN_AU6   -to dac_data[8]
+set_location_assignment PIN_AT6   -to dac_data[9]
+set_location_assignment PIN_AK8   -to dac_data[10]
+set_location_assignment PIN_AL8   -to dac_data[11]
+set_location_assignment PIN_AT15  -to dac_data[12]
+set_location_assignment PIN_AU15  -to dac_data[13]
+
+set_instance_assignment -name IO_STANDARD "2.5 V" -to afe_pdn
+set_instance_assignment -name IO_STANDARD "2.5 V" -to afe_stby
+set_instance_assignment -name IO_STANDARD "2.5 V" -to amp_disbn
+set_instance_assignment -name IO_STANDARD "2.5 V" -to prc_sck
+set_instance_assignment -name IO_STANDARD "2.5 V" -to prc_cnv
+set_instance_assignment -name IO_STANDARD "2.5 V" -to prc_sdo_i
+set_instance_assignment -name IO_STANDARD "2.5 V" -to prc_sdo_q
+set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_sleep
+set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[7]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[8]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[9]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[10]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[11]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[12]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to dac_data[13]
+
+execute_flow -compile
+
diff --git a/projects/usdrx1/a5gt/system_timing.tcl b/projects/usdrx1/a5gt/system_timing.tcl
new file mode 100644
index 000000000..e1f355d44
--- /dev/null
+++ b/projects/usdrx1/a5gt/system_timing.tcl
@@ -0,0 +1,3 @@
+
+report_timing -detail path_only -npaths 20 -file timing_impl.log
+  
diff --git a/projects/usdrx1/a5gt/system_top.v b/projects/usdrx1/a5gt/system_top.v
new file mode 100644
index 000000000..872385a86
--- /dev/null
+++ b/projects/usdrx1/a5gt/system_top.v
@@ -0,0 +1,515 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  // clock and resets
+
+  sys_clk,
+  sys_resetn,
+
+  // ddr3
+
+  ddr3_a,
+  ddr3_ba,
+  ddr3_clk_p,
+  ddr3_clk_n,
+  ddr3_cke,
+  ddr3_cs_n,
+  ddr3_dm,
+  ddr3_ras_n,
+  ddr3_cas_n,
+  ddr3_we_n,
+  ddr3_reset_n,
+  ddr3_dq,
+  ddr3_dqs_p,
+  ddr3_dqs_n,
+  ddr3_odt,
+  ddr3_rzq,
+
+  // ethernet
+
+  eth_rx_clk,
+  eth_rx_data,
+  eth_rx_cntrl,
+  eth_tx_clk_out,
+  eth_tx_data,
+  eth_tx_cntrl,
+  eth_mdc,
+  eth_mdio_i,
+  eth_mdio_o,
+  eth_mdio_t,
+
+  // board gpio
+
+  led_grn,
+  led_red,
+  push_buttons,
+  dip_switches,
+
+  // lane interface
+
+  ref_clk,
+  rx_data,
+  rx_sync,
+  rx_sysref,
+
+  // spi
+
+  spi_fout_enb_clk,
+  spi_fout_enb_mlo,
+  spi_fout_enb_rst,
+  spi_fout_enb_sync,
+  spi_fout_enb_sysref,
+  spi_fout_enb_trig,
+  spi_fout_clk,
+  spi_fout_sdio,
+  spi_afe_csn,
+  spi_afe_clk,
+  spi_afe_sdio,
+  spi_clk_csn,
+  spi_clk_clk,
+  spi_clk_sdio,
+
+  afe_rst,
+  afe_trig,
+
+  // gpio
+
+  dac_sleep,
+  dac_data,
+  afe_pdn,
+  afe_stby,
+  clk_resetn,
+  clk_syncn,
+  clk_status,
+  amp_disbn,
+  prc_sck,
+  prc_cnv,
+  prc_sdo_i,
+  prc_sdo_q);
+
+  // clock and resets
+
+  input             sys_clk;
+  input             sys_resetn;
+
+  // ddr3
+
+  output  [ 13:0]   ddr3_a;
+  output  [  2:0]   ddr3_ba;
+  output            ddr3_clk_p;
+  output            ddr3_clk_n;
+  output            ddr3_cke;
+  output            ddr3_cs_n;
+  output  [  7:0]   ddr3_dm;
+  output            ddr3_ras_n;
+  output            ddr3_cas_n;
+  output            ddr3_we_n;
+  output            ddr3_reset_n;
+  inout   [ 63:0]   ddr3_dq;
+  inout   [  7:0]   ddr3_dqs_p;
+  inout   [  7:0]   ddr3_dqs_n;
+  output            ddr3_odt;
+  input             ddr3_rzq;
+
+  // ethernet
+
+  input             eth_rx_clk;
+  input   [  3:0]   eth_rx_data;
+  input             eth_rx_cntrl;
+  output            eth_tx_clk_out;
+  output  [  3:0]   eth_tx_data;
+  output            eth_tx_cntrl;
+  output            eth_mdc;
+  input             eth_mdio_i;
+  output            eth_mdio_o;
+  output            eth_mdio_t;
+
+  // board gpio
+
+  output  [  7:0]   led_grn;
+  output  [  7:0]   led_red;
+  input   [  2:0]   push_buttons;
+  input   [  7:0]   dip_switches;
+
+  // lane interface
+
+  input           ref_clk;
+  input   [ 7:0]  rx_data;
+  output          rx_sysref;
+  output          rx_sync;
+
+  // spi
+
+  output          spi_fout_enb_clk;
+  output          spi_fout_enb_mlo;
+  output          spi_fout_enb_rst;
+  output          spi_fout_enb_sync;
+  output          spi_fout_enb_sysref;
+  output          spi_fout_enb_trig;
+  output          spi_fout_clk;
+  output          spi_fout_sdio;
+  output  [ 3:0]  spi_afe_csn;
+  output          spi_afe_clk;
+  inout           spi_afe_sdio;
+  output          spi_clk_csn;
+  output          spi_clk_clk;
+  inout           spi_clk_sdio;
+
+  output          afe_rst;
+  output          afe_trig;
+  // gpio
+
+  output          dac_sleep;
+  output  [13:0]  dac_data;
+  output          afe_pdn;
+  output          afe_stby;
+  output          clk_resetn;
+  output          clk_syncn;
+  input           clk_status;
+  output          amp_disbn;
+  inout           prc_sck;
+  inout           prc_cnv;
+  inout           prc_sdo_i;
+  inout           prc_sdo_q;
+
+  // internal registers
+
+  reg             rx_sysref_m1 = 'd0;
+  reg             rx_sysref_m2 = 'd0;
+  reg             rx_sysref_m3 = 'd0;
+  reg             rx_sysref = 'd0;
+
+  // internal clocks and resets
+
+  wire            sys_125m_clk;
+  wire            sys_25m_clk;
+  wire            sys_2m5_clk;
+  wire            eth_tx_clk;
+  wire            rx_clk;
+  wire            adc_clk;
+
+  // internal registers
+
+  reg             dma_sync = 'd0;
+  reg             dma_wr = 'd0;
+  reg             adc_dovf;
+  reg     [511:0] dma_data = 'd0;
+  reg             rx_sof_0_s = 'd0;
+  reg             rx_sof_1_s = 'd0;
+  reg             rx_sof_2_s = 'd0;
+  reg             rx_sof_3_s = 'd0;
+
+  // internal signals
+
+  wire            sys_pll_locked_s;
+  wire            eth_tx_reset_s;
+  wire            eth_tx_mode_1g_s;
+  wire            eth_tx_mode_10m_100m_n_s;
+
+  wire    [ 4:0]  spi_csn;
+  wire            spi_clk;
+  wire            spi_mosi;
+  wire            spi_miso;
+  wire            rx_ref_clk;
+  wire            rx_sync;
+  wire   [127:0]  adc_data_0;
+  wire   [127:0]  adc_data_1;
+  wire   [127:0]  adc_data_2;
+  wire   [127:0]  adc_data_3;
+  wire            adc_valid;
+  wire   [  7:0]  adc_valid_0;
+  wire   [  7:0]  adc_valid_1;
+  wire   [  7:0]  adc_valid_2;
+  wire   [  7:0]  adc_valid_3;
+  wire   [  7:0]  adc_enable_0;
+  wire   [  7:0]  adc_enable_1;
+  wire   [  7:0]  adc_enable_2;
+  wire   [  7:0]  adc_enable_3;
+  wire            adc_dovf_0;
+  wire            adc_dovf_1;
+  wire            adc_dovf_2;
+  wire            adc_dovf_3;
+
+  wire   [  3:0]  rx_ip_sof_s;
+  wire   [255:0]  rx_ip_data_s;
+  wire   [255:0]  rx_data_s;
+  wire            rx_sw_rstn_s;
+  wire            rx_sysref_s;
+  wire            rx_err_s;
+  wire            rx_ready_s;
+  wire    [  3:0] rx_rst_state_s;
+  wire            rx_lane_aligned_s;
+  wire    [  7:0] rx_analog_reset_s;
+  wire    [  7:0] rx_digital_reset_s;
+  wire    [  7:0] rx_cdr_locked_s;
+  wire    [  7:0] rx_cal_busy_s;
+  wire            rx_pll_locked_s;
+  wire    [ 22:0] rx_xcvr_status_s;
+  wire    [  7:0] rx_data_sof;
+
+  // ethernet transmit clock
+
+  assign eth_tx_clk = (eth_tx_mode_1g_s == 1'b1) ? sys_125m_clk :
+    (eth_tx_mode_10m_100m_n_s == 1'b0) ? sys_25m_clk : sys_2m5_clk;
+
+  altddio_out #(.width(1)) i_eth_tx_clk_out (
+    .aset (1'b0),
+    .sset (1'b0),
+    .sclr (1'b0),
+    .oe (1'b1),
+    .oe_out (),
+    .datain_h (1'b1),
+    .datain_l (1'b0),
+    .outclocken (1'b1),
+    .aclr (eth_tx_reset_s),
+    .outclock (eth_tx_clk),
+    .dataout (eth_tx_clk_out));
+
+  assign eth_tx_reset_s = ~sys_pll_locked_s;
+
+  always @(posedge adc_clk) begin
+    dma_sync <= 1'b1;
+    dma_wr <= (|adc_enable_0)| (| adc_enable_1) | (|adc_enable_2) | (|adc_enable_3);
+    dma_data <= {adc_data_3, adc_data_2, adc_data_1, adc_data_0};
+    adc_dovf <= adc_dovf_3 | adc_dovf_2 | adc_dovf_1 | adc_dovf_0;
+  end
+
+  always @(posedge rx_clk) begin
+    rx_sysref_m1 <= rx_sysref_s;
+    rx_sysref_m2 <= rx_sysref_m1;
+    rx_sysref_m3 <= rx_sysref_m2;
+    rx_sysref <= rx_sysref_m2 & ~rx_sysref_m3;
+  end
+
+  sld_signaltap #(
+    .sld_advanced_trigger_entity ("basic,1,"),
+    .sld_data_bits (258),
+    .sld_data_bit_cntr_bits (8),
+    .sld_enable_advanced_trigger (0),
+    .sld_mem_address_bits (10),
+    .sld_node_crc_bits (32),
+    .sld_node_crc_hiword (10311),
+    .sld_node_crc_loword (14297),
+    .sld_node_info (1076736),
+    .sld_ram_block_type ("AUTO"),
+    .sld_sample_depth (1024),
+    .sld_storage_qualifier_gap_record (0),
+    .sld_storage_qualifier_mode ("OFF"),
+    .sld_trigger_bits (2),
+    .sld_trigger_in_enabled (0),
+    .sld_trigger_level (1),
+    .sld_trigger_level_pipeline (1))
+  i_signaltap (
+    .acq_clk (rx_clk),
+    .acq_data_in ({rx_sysref, rx_sync, rx_ip_data_s}),
+    .acq_trigger_in ({rx_sysref, rx_sync}));
+
+  genvar n;
+  generate
+  for (n = 0; n < 8; n = n + 1) begin: g_align_1
+  ad_jesd_align i_jesd_align (
+    .rx_clk (rx_clk),
+    .rx_sof (rx_ip_sof_s),
+    .rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
+    .rx_data_sof(rx_data_sof[n]),
+    .rx_data (rx_data_s[n*32+31:n*32]));
+  end
+  endgenerate
+
+  assign rx_xcvr_status_s[22:22] = rx_sync;
+  assign rx_xcvr_status_s[21:21] = rx_ready_s;
+  assign rx_xcvr_status_s[20:20] = rx_pll_locked_s;
+  assign rx_xcvr_status_s[19:16] = rx_rst_state_s;
+  assign rx_xcvr_status_s[15: 8] = rx_cdr_locked_s;
+  assign rx_xcvr_status_s[ 7: 0] = rx_cal_busy_s;
+
+  ad_xcvr_rx_rst #(.NUM_OF_LANES (8)) i_xcvr_rx_rst (
+    .rx_clk (rx_clk),
+    .rx_rstn (sys_resetn),
+    .rx_sw_rstn (rx_sw_rstn_s),
+    .rx_pll_locked (rx_pll_locked_s),
+    .rx_cal_busy (rx_cal_busy_s),
+    .rx_cdr_locked (rx_cdr_locked_s),
+    .rx_analog_reset (rx_analog_reset_s),
+    .rx_digital_reset (rx_digital_reset_s),
+    .rx_ready (rx_ready_s),
+    .rx_rst_state (rx_rst_state_s));
+
+  assign spi_fout_enb_clk     = 1'b0;
+  assign spi_fout_enb_mlo     = 1'b0;
+  assign spi_fout_enb_rst     = 1'b0;
+  assign spi_fout_enb_sync    = 1'b0;
+  assign spi_fout_enb_sysref  = 1'b0;
+  assign spi_fout_enb_trig    = 1'b0;
+  assign spi_fout_clk         = 1'b0;
+  assign spi_fout_sdio        = 1'b0;
+  assign spi_afe_csn          = spi_csn[ 4: 1];
+  assign spi_clk_csn          = spi_csn[ 0: 0];
+  assign spi_afe_clk          = spi_clk;
+  assign spi_clk_clk          = spi_clk;
+
+  always @(posedge rx_clk)
+  begin
+    rx_sof_0_s <= rx_data_sof[0] | rx_data_sof[1];
+    rx_sof_1_s <= rx_data_sof[2] | rx_data_sof[3];
+    rx_sof_2_s <= rx_data_sof[4] | rx_data_sof[5];
+    rx_sof_3_s <= rx_data_sof[6] | rx_data_sof[7];
+  end
+
+   usdrx1_spi i_spi (
+    .spi_afe_csn (spi_csn[4:1]),
+    .spi_clk_csn (spi_csn[0]),
+    .spi_clk (spi_clk),
+    .spi_mosi (spi_mosi),
+    .spi_miso (spi_miso),
+    .spi_afe_sdio (spi_afe_sdio),
+    .spi_clk_sdio (spi_clk_sdio));
+
+  system_bd i_system_bd (
+    .sys_clk_clk (sys_clk),
+    .sys_reset_reset_n (sys_resetn),
+    .sys_125m_clk_clk (sys_125m_clk),
+    .sys_25m_clk_clk (sys_25m_clk),
+    .sys_2m5_clk_clk (sys_2m5_clk),
+    .sys_pll_locked_export (sys_pll_locked_s),
+    .sys_ddr3_phy_mem_a (ddr3_a),
+    .sys_ddr3_phy_mem_ba (ddr3_ba),
+    .sys_ddr3_phy_mem_ck (ddr3_clk_p),
+    .sys_ddr3_phy_mem_ck_n (ddr3_clk_n),
+    .sys_ddr3_phy_mem_cke (ddr3_cke),
+    .sys_ddr3_phy_mem_cs_n (ddr3_cs_n),
+    .sys_ddr3_phy_mem_dm (ddr3_dm),
+    .sys_ddr3_phy_mem_ras_n (ddr3_ras_n),
+    .sys_ddr3_phy_mem_cas_n (ddr3_cas_n),
+    .sys_ddr3_phy_mem_we_n (ddr3_we_n),
+    .sys_ddr3_phy_mem_reset_n (ddr3_reset_n),
+    .sys_ddr3_phy_mem_dq (ddr3_dq),
+    .sys_ddr3_phy_mem_dqs (ddr3_dqs_p),
+    .sys_ddr3_phy_mem_dqs_n (ddr3_dqs_n),
+    .sys_ddr3_phy_mem_odt (ddr3_odt),
+    .sys_ddr3_oct_rzqin (ddr3_rzq),
+    .sys_ethernet_tx_clk_clk (eth_tx_clk),
+    .sys_ethernet_rx_clk_clk (eth_rx_clk),
+    .sys_ethernet_status_set_10 (),
+    .sys_ethernet_status_set_1000 (),
+    .sys_ethernet_status_eth_mode (eth_tx_mode_1g_s),
+    .sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n_s),
+    .sys_ethernet_rgmii_rgmii_in (eth_rx_data),
+    .sys_ethernet_rgmii_rgmii_out (eth_tx_data),
+    .sys_ethernet_rgmii_rx_control (eth_rx_cntrl),
+    .sys_ethernet_rgmii_tx_control (eth_tx_cntrl),
+    .sys_ethernet_mdio_mdc (eth_mdc),
+    .sys_ethernet_mdio_mdio_in (eth_mdio_i),
+    .sys_ethernet_mdio_mdio_out (eth_mdio_o),
+    .sys_ethernet_mdio_mdio_oen (eth_mdio_t),
+    .sys_gpio_in_port ({25'h0, clk_status, 6'h0 }),
+    .sys_gpio_out_port ({3'h0, rx_sysref_s,
+      rx_sw_rstn_s, dac_data, dac_sleep,
+      1'b0, 1'b0, 1'b0, 1'b0,
+      amp_disbn, 1'b0, clk_syncn, clk_resetn,
+      afe_stby, afe_pdn, afe_trig, afe_rst}),
+    .sys_spi_MISO (spi_miso),
+    .sys_spi_MOSI (spi_mosi),
+    .sys_spi_SCLK (spi_clk),
+    .sys_spi_SS_n (spi_csn),
+    .axi_dmac_0_fifo_wr_clock_clk (adc_clk),
+    .axi_dmac_0_fifo_wr_if_ovf (adc_dovf),
+    .axi_dmac_0_fifo_wr_if_wren (dma_wr),
+    .axi_dmac_0_fifo_wr_if_data (dma_data),
+    .axi_dmac_0_fifo_wr_if_sync (dma_sync),
+    .sys_jesd204b_s1_rx_link_data (rx_ip_data_s),
+    .sys_jesd204b_s1_rx_link_valid (),
+    .sys_jesd204b_s1_rx_link_ready (1'b1),
+    .sys_jesd204b_s1_lane_aligned_all_export (rx_lane_aligned_s),
+    .sys_jesd204b_s1_sysref_export (rx_sysref),
+    .sys_jesd204b_s1_rx_ferr_export (rx_err_s),
+    .sys_jesd204b_s1_lane_aligned_export (rx_lane_aligned_s),
+    .sys_jesd204b_s1_sync_n_export (rx_sync),
+    .sys_jesd204b_s1_rx_sof_export (rx_ip_sof_s),
+    .sys_jesd204b_s1_rx_xcvr_data_rx_serial_data (rx_data),
+    .sys_jesd204b_s1_rx_analogreset_rx_analogreset (rx_analog_reset_s),
+    .sys_jesd204b_s1_rx_digitalreset_rx_digitalreset (rx_digital_reset_s),
+    .sys_jesd204b_s1_locked_export (rx_cdr_locked_s),
+    .sys_jesd204b_s1_rx_cal_busy_export (rx_cal_busy_s),
+    .sys_jesd204b_s1_ref_clk_clk (ref_clk),
+    .sys_jesd204b_s1_rx_clk_clk (rx_clk),
+    .sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s),
+    .axi_ad9671_0_xcvr_clk_clk (rx_clk),
+    .axi_ad9671_0_xcvr_data_data (rx_data_s[63:0]),
+    .axi_ad9671_0_xcvr_data_data_sof(rx_sof_0_s),
+    .axi_ad9671_0_adc_clock_clk (adc_clk),
+    .axi_ad9671_0_adc_dma_if_valid (adc_valid_0),
+    .axi_ad9671_0_adc_dma_if_enable (adc_enable_0),
+    .axi_ad9671_0_adc_dma_if_data (adc_data_0),
+    .axi_ad9671_0_adc_dma_if_dovf (adc_dovf_0),
+    .axi_ad9671_0_adc_dma_if_dunf (1'b0),
+    .axi_ad9671_1_xcvr_clk_clk (rx_clk),
+    .axi_ad9671_1_xcvr_data_data (rx_data_s[127:64]),
+    .axi_ad9671_1_xcvr_data_data_sof(rx_sof_1_s),
+    .axi_ad9671_1_adc_clock_clk (),
+    .axi_ad9671_1_adc_dma_if_valid (adc_valid_1),
+    .axi_ad9671_1_adc_dma_if_enable (adc_enable_1),
+    .axi_ad9671_1_adc_dma_if_data (adc_data_1),
+    .axi_ad9671_1_adc_dma_if_dovf (adc_dovf_1),
+    .axi_ad9671_1_adc_dma_if_dunf (1'b0),
+    .axi_ad9671_2_xcvr_clk_clk (rx_clk),
+    .axi_ad9671_2_xcvr_data_data (rx_data_s[191:128]),
+    .axi_ad9671_2_xcvr_data_data_sof(rx_sof_2_s),
+    .axi_ad9671_2_adc_clock_clk (),
+    .axi_ad9671_2_adc_dma_if_valid (adc_valid_2),
+    .axi_ad9671_2_adc_dma_if_enable (adc_enable_2),
+    .axi_ad9671_2_adc_dma_if_data (adc_data_2),
+    .axi_ad9671_2_adc_dma_if_dovf (adc_dovf_2),
+    .axi_ad9671_2_adc_dma_if_dunf (1'b0),
+    .axi_ad9671_3_xcvr_clk_clk (rx_clk),
+    .axi_ad9671_3_xcvr_data_data (rx_data_s[255:192]),
+    .axi_ad9671_3_xcvr_data_data_sof(rx_sof_3_s),
+    .axi_ad9671_3_adc_clock_clk (),
+    .axi_ad9671_3_adc_dma_if_valid (adc_valid_3),
+    .axi_ad9671_3_adc_dma_if_enable (adc_enable_3),
+    .axi_ad9671_3_adc_dma_if_data (adc_data_3),
+    .axi_ad9671_3_adc_dma_if_dovf (adc_dovf_3),
+    .axi_ad9671_3_adc_dma_if_dunf (1'b0));
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************